Inquiring about the arrangement of the VRF (Vector Register File) configuration

[TimLee-123]

Issue

Hello, I would like to inquire about the scenario when VLEN = 128 and Nrlanes = 4. In lane 0, bank 0, with 128 bits, does this mean that each vector register individually possesses 4 bits? Or is there another interpretation? If I have misunderstood, please correct me. Thank you.

[ckf104]

This docs explains arrangement of ara's vrf detailedly.