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Added Encryption FSM, Modified modules for status signal, Fixes in aes_KeySchedule_FSM, rename Rocn to Rcon_const in aes_types
1 parent 351252e commit 010a960

6 files changed

+283
-28
lines changed

‎aes_AddRoundKey.vhd

+2-2
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ entity aes_AddRoundKey is
1111
key_in : in matrix(3 downto 0, 3 downto 0);
1212
data_out : out matrix(3 downto 0, 3 downto 0);
1313

14-
start : in std_logic;
15-
done : out std_logic;
14+
-- start : in std_logic;
15+
-- done : out std_logic;
1616

1717
clk : in std_logic;
1818
rst : in std_logic

‎aes_Encrypt_FSM.vhd

+214
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,214 @@
1+
library ieee;
2+
use ieee.std_logic_1164.all;
3+
use ieee.numeric_std.all;
4+
5+
library work;
6+
use work.aes_types.all;
7+
8+
entity aes_Encrypt_FSM is
9+
port(
10+
key_in : in matrix(3 downto 0, 3 downto 0);
11+
12+
data_block_in : in matrix(3 downto 0, 3 downto 0);
13+
data_block_out : out matrix(3 downto 0, 3 downto 0);
14+
15+
key_load : in std_logic;
16+
17+
start : in std_logic;
18+
done : out std_logic;
19+
20+
busy : out std_logic;
21+
22+
clk : in std_logic;
23+
rst : in std_logic
24+
);
25+
end entity aes_Encrypt_FSM;
26+
27+
architecture RTL of aes_Encrypt_FSM is
28+
component aes_KeySchedule_FSM
29+
port(key_in : in matrix(3 downto 0, 3 downto 0);
30+
keychain_out : out matrix_128(10 downto 0);
31+
start : in std_logic;
32+
done : out std_logic;
33+
clk : in std_logic;
34+
rst : in std_logic);
35+
end component aes_KeySchedule_FSM;
36+
37+
component aes_SubBytes_ShiftRows
38+
port(data_in : in matrix(3 downto 0, 3 downto 0);
39+
data_out : out matrix(3 downto 0, 3 downto 0);
40+
start : in std_logic;
41+
done : out std_logic;
42+
clk : in std_logic;
43+
rst : in std_logic);
44+
end component aes_SubBytes_ShiftRows;
45+
46+
component aes_MixColumns
47+
port(data_in : in matrix(3 downto 0, 3 downto 0);
48+
data_out : out matrix(3 downto 0, 3 downto 0);
49+
start : in std_logic;
50+
done : out std_logic;
51+
clk : in std_logic;
52+
rst : in std_logic);
53+
end component aes_MixColumns;
54+
55+
component aes_AddRoundKey
56+
port(data_in : in matrix(3 downto 0, 3 downto 0);
57+
key_in : in matrix(3 downto 0, 3 downto 0);
58+
data_out : out matrix(3 downto 0, 3 downto 0);
59+
60+
clk : in std_logic;
61+
rst : in std_logic);
62+
end component aes_AddRoundKey;
63+
64+
signal latched_data_in, round_data_out, round_data_in, round_key, latched_key_in : matrix(3 downto 0, 3 downto 0);
65+
signal ss_data_in, ss_data_out, mc_data_in, mc_data_out : matrix(3 downto 0, 3 downto 0);
66+
signal mc_start, mc_done, ss_done, ss_start : std_logic;
67+
signal ss_start_tmp : integer range 0 to 1 := 0;
68+
signal keychain : matrix_128(10 downto 0);
69+
signal round_counter : integer range 1 to 10 := 1;
70+
signal ks_start, ks_done : std_logic;
71+
72+
type state is (IDLE, KEYSCHEDULE, INITIAL_ROUND, MAIN_ROUND, ENC_OUTPUT);
73+
signal current_state : state := IDLE;
74+
begin
75+
Inst_aes_KeySchedule_FSM : aes_KeySchedule_FSM
76+
port map(
77+
key_in => latched_key_in,
78+
keychain_out => keychain,
79+
start => ks_start,
80+
done => ks_done,
81+
clk => clk,
82+
rst => rst
83+
);
84+
Inst_aes_SubBytes_ShiftRows : aes_SubBytes_ShiftRows
85+
port map(
86+
data_in => ss_data_in,
87+
data_out => ss_data_out,
88+
done => ss_done,
89+
start => ss_start,
90+
clk => clk,
91+
rst => rst
92+
);
93+
Inst_aes_MixColumns : aes_MixColumns
94+
port map(
95+
data_in => mc_data_in,
96+
data_out => mc_data_out,
97+
start => mc_start,
98+
done => mc_done,
99+
clk => clk,
100+
rst => rst
101+
);
102+
-- Inst_aes_AddRoundKey : aes_AddRoundKey
103+
-- port map(
104+
-- data_in => a_data_in,
105+
-- key_in => key_in,
106+
-- data_out => data_out,
107+
-- clk => clk,
108+
-- rst => rst
109+
-- );
110+
111+
state_proc : process(clk) is
112+
begin
113+
if (rising_edge(clk)) then
114+
if (rst = '1') then
115+
current_state <= IDLE;
116+
for i in 0 to 3 loop
117+
for j in 0 to 3 loop
118+
round_data_in(i, j) <= (others => '0');
119+
round_data_out(i, j) <= (others => '0');
120+
latched_key_in(i, j) <= (others => '0');
121+
round_counter <= 1;
122+
end loop;
123+
end loop;
124+
else
125+
if (start = '1') then
126+
latched_data_in <= data_block_in;
127+
if (key_load = '1') then
128+
latched_key_in <= key_in;
129+
current_state <= KEYSCHEDULE;
130+
else
131+
latched_key_in <= latched_key_in;
132+
current_state <= INITIAL_ROUND;
133+
end if;
134+
else
135+
latched_key_in <= latched_key_in;
136+
current_state <= current_state;
137+
end if;
138+
139+
case current_state is
140+
when IDLE =>
141+
null;
142+
when KEYSCHEDULE =>
143+
if (ks_done = '1') then
144+
current_state <= INITIAL_ROUND;
145+
ks_start <= '0';
146+
else
147+
current_state <= current_state;
148+
ks_start <= '1';
149+
end if;
150+
151+
when INITIAL_ROUND =>
152+
round_key <= keychain(0);
153+
round_data_in <= round_data_out;
154+
round_data_out <= latched_data_in XOR round_key;
155+
current_state <= MAIN_ROUND;
156+
done <= '0';
157+
when MAIN_ROUND =>
158+
round_key <= keychain(round_counter);
159+
160+
if (round_counter = 10) then
161+
ss_data_in <= round_data_in;
162+
round_data_out <= ss_data_in XOR round_data_out;
163+
164+
if (ss_start_tmp = 0) then
165+
ss_start <= '1';
166+
ss_start_tmp <= 1;
167+
else
168+
ss_start <= '0';
169+
end if;
170+
171+
if (ss_done = '1') then
172+
current_state <= ENC_OUTPUT;
173+
round_counter <= 1;
174+
ss_start_tmp <= 0;
175+
else
176+
current_state <= current_state;
177+
end if;
178+
else
179+
ss_data_in <= round_data_in;
180+
mc_data_in <= ss_data_out;
181+
round_data_out <= mc_data_out XOR round_key;
182+
183+
if (ss_start_tmp = 0) then
184+
ss_start <= '1';
185+
ss_start_tmp <= 1;
186+
else
187+
ss_start <= '0';
188+
end if;
189+
190+
if (ss_done = '1') then
191+
mc_start <= '1';
192+
else
193+
mc_start <= '0';
194+
end if;
195+
196+
if (mc_done = '1') then
197+
round_counter <= round_counter + 1;
198+
round_data_in <= round_data_out;
199+
ss_start_tmp <= 0;
200+
end if;
201+
current_state <= current_state;
202+
end if;
203+
done <= '0';
204+
205+
when ENC_OUTPUT =>
206+
done <= '1';
207+
data_block_out <= round_data_out;
208+
current_state <= IDLE;
209+
end case;
210+
end if;
211+
end if;
212+
end process state_proc;
213+
214+
end architecture RTL;

‎aes_KeySchedule_FSM.vhd

+24-20
Original file line numberDiff line numberDiff line change
@@ -39,20 +39,21 @@ architecture RTL of aes_KeySchedule_FSM is
3939
signal latched_key_in : matrix(3 downto 0, 3 downto 0);
4040
signal round_counter : integer range 1 to 10 := 1;
4141

42-
signal ks_en, ks_done, ks_start : std_logic;
43-
42+
signal ks_en, ks_done, ks_start : std_logic;
43+
signal Rcon_round : std_logic_vector(7 downto 0);
4444
signal round_key_in, round_key_out : matrix(3 downto 0, 3 downto 0);
4545

4646
begin
4747
KeySchedule_Module : aes_KeySchedule
4848
port map(
49-
key_in => round_key_in,
50-
rcon => Rcon(round_counter - 1),
51-
en => ks_en,
52-
start => ks_start,
53-
clk => clk,
54-
done => ks_done,
55-
rst => rst
49+
key_in => round_key_in,
50+
rcon => Rcon_round,
51+
key_out => round_key_out,
52+
en => ks_en,
53+
start => ks_start,
54+
clk => clk,
55+
done => ks_done,
56+
rst => rst
5657
);
5758
process(clk)
5859
begin
@@ -67,22 +68,21 @@ begin
6768
end loop;
6869
end loop;
6970
else
71+
Rcon_round <= Rcon_const(round_counter - 1);
7072
if (ks_done = '1') then
7173
keychain_out(round_counter) <= round_key_out;
7274
round_key_in <= round_key_out;
73-
else
74-
round_key_in <= round_key_in;
75-
keychain_out(round_counter) <= keychain_out(round_counter);
7675
end if;
7776

7877
case current_state is
7978
when IDLE =>
8079
if (start = '1') then
81-
current_state <= PROCESSING;
82-
latched_key_in <= key_in;
83-
done <= '0';
80+
current_state <= PROCESSING;
81+
latched_key_in <= key_in;
82+
done <= '0';
83+
8484
keychain_out(0) <= key_in;
85-
round_key_in <= key_in;
85+
round_key_in <= latched_key_in;
8686

8787
ks_start <= '1';
8888
ks_en <= '1';
@@ -93,12 +93,16 @@ begin
9393
end if;
9494
when PROCESSING =>
9595
if (round_counter = 10) then
96-
done <= '1';
97-
current_state <= IDLE;
98-
round_counter <= 0;
96+
if (ks_done = '1') then
97+
done <= '1';
98+
current_state <= IDLE;
99+
round_counter <= 1;
100+
end if;
99101
else
102+
if (ks_done = '1') then
103+
round_counter <= round_counter + 1;
104+
end if;
100105
current_state <= PROCESSING;
101-
round_counter <= round_counter + 1;
102106
end if;
103107
end case;
104108
end if;

‎aes_MixColumns.vhd

+18
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,8 @@ entity aes_MixColumns is
1919
end entity aes_MixColumns;
2020

2121
architecture RTL of aes_MixColumns is
22+
type state is (IDLE, PROCESSING, PROCDONE);
23+
signal current_state : state := IDLE;
2224
begin
2325
process(clk)
2426
begin
@@ -36,6 +38,22 @@ begin
3638
end loop;
3739
end loop;
3840

41+
if (start = '1') then
42+
current_state <= PROCESSING;
43+
else
44+
current_state <= current_state;
45+
end if;
46+
47+
case current_state is
48+
when IDLE =>
49+
done <= '0';
50+
when PROCESSING =>
51+
current_state <= PROCDONE;
52+
done <= '0';
53+
when PROCDONE =>
54+
done <= '1';
55+
current_state <= IDLE;
56+
end case;
3957
end if;
4058
end if;
4159

‎aes_SubBytes_ShiftRows.vhd

+22-3
Original file line numberDiff line numberDiff line change
@@ -10,18 +10,20 @@ entity aes_SubBytes_ShiftRows is
1010
data_in : in matrix(3 downto 0, 3 downto 0);
1111
data_out : out matrix(3 downto 0, 3 downto 0);
1212

13-
-- start : in std_logic;
14-
-- done : out std_logic;
13+
start : in std_logic;
14+
done : out std_logic;
1515

1616
clk : in std_logic;
1717
rst : in std_logic
1818
);
1919
end entity aes_SubBytes_ShiftRows;
2020

2121
architecture RTL of aes_SubBytes_ShiftRows is
22+
type state is (IDLE, PROCESSING, PROCDONE);
23+
signal current_state : state := IDLE;
24+
2225
begin
2326
process(clk)
24-
variable temp_reg : generic_memory(3 downto 0);
2527
begin
2628
if (rising_edge(clk)) then
2729
if (rst = '1') then
@@ -31,6 +33,23 @@ begin
3133
end loop;
3234
end loop;
3335
else
36+
if (start = '1') then
37+
current_state <= PROCESSING;
38+
else
39+
current_state <= current_state;
40+
end if;
41+
42+
case current_state is
43+
when IDLE =>
44+
done <= '0';
45+
when PROCESSING =>
46+
current_state <= PROCDONE;
47+
done <= '0';
48+
when PROCDONE =>
49+
done <= '1';
50+
current_state <= IDLE;
51+
end case;
52+
3453
--Substitute
3554
for J in 0 to 3 loop
3655
data_out(J, 0) <= Sbox(to_integer(unsigned(data_in(J, 0))));

‎aes_types.vhd

+3-3
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,9 @@ package aes_types is
77
type matrix is array (integer range <>, integer range <>) of std_logic_vector(7 downto 0);
88
type generic_memory is array (integer range <>) of std_logic_vector(7 downto 0);
99
type matrix_128 is array (integer range <>) of matrix(3 downto 0, 3 downto 0);
10-
11-
constant Rcon : generic_memory(9 downto 0) := (
12-
X"01",X"02",X"04",X"08",X"10",X"20",X"40",X"80",X"1b",X"36"
10+
11+
constant Rcon_const : generic_memory(9 downto 0) := (
12+
X"01", X"02", X"04", X"08", X"10", X"20", X"40", X"80", X"1b", X"36"
1313
);
1414
constant Sbox : generic_memory(255 downto 0) := (
1515
X"16", X"bb", X"54", X"b0", X"0f", X"2d", X"99", X"41", X"68", X"42", X"e6", X"bf", X"0d", X"89", X"a1", X"8c",

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