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markram1729markram1729
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add : tests
1 parent 3ada6ae commit 7e2df0c

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‎CMakeLists.txt‎

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Original file line numberDiff line numberDiff line change
@@ -114,6 +114,7 @@ set(STA_SOURCE
114114
liberty/TimingRole.cc
115115
liberty/Units.cc
116116
liberty/Wireload.cc
117+
liberty/GeneratedClock.cc
117118

118119
network/ConcreteLibrary.cc
119120
network/ConcreteNetwork.cc

‎test/generated_clock.lib‎

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library (generated_clock) {
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delay_model : "table_lookup";
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time_unit : "1ns";
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voltage_unit : "1v";
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input_threshold_pct_rise : 50;
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input_threshold_pct_fall : 50;
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output_threshold_pct_rise : 50;
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output_threshold_pct_fall : 50;
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slew_lower_threshold_pct_rise : 30;
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slew_lower_threshold_pct_fall : 30;
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slew_upper_threshold_pct_rise : 70;
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slew_upper_threshold_pct_fall : 70;
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cell (CLK_GEN) {
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area : 10.0;
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pin (CLK_IN) {
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direction : input;
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clock : true;
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}
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pin (CLK_OUT_DIV) {
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direction : output;
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}
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pin (CLK_OUT_MUL) {
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direction : output;
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}
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generated_clock (gen_clk_div2) {
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clock_pin : " CLK_OUT_DIV ";
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master_pin : CLK_IN ;
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divided_by : 2;
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}
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generated_clock (gen_clk_mul2_inv_dut_80) {
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clock_pin : " CLK_OUT_MUL ";
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master_pin : CLK_IN ;
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multiplied_by : 2;
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invert : true; /* inverted duty cycle of 80, so 20 */
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duty_cycle : 80.0;
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}
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timing () {
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related_pin : CLK_IN;
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timing_type : rising_edge;
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intrinsic_rise : 10;
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intrinsic_fall : 10;
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}
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}
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cell (CLK_EDGE_SHIFT) {
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area : 10.0;
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pin (CLK_IN) {
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direction : input;
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clock : true;
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}
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pin (CLK_OUT) {
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direction : output;
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}
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generated_clock (shift) {
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clock_pin : CLK_OUT ;
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master_pin : CLK_IN;
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edges (1, 3, 5);
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shifts (0, 0, 0)
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}
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timing () {
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related_pin : CLK_IN;
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timing_type : rising_edge;
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intrinsic_rise : 10;
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intrinsic_fall : 10;
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}
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}
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}

‎test/generated_clock.ok‎

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Warning: generated_clock.lib line 57, shifts are not supported yet, may cause malformed waveforms.
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Number of clocks: 9
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clk period: 10.000000
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u_second_hierarchy/clk_gen/CLK_OUT_DIV period: 20.000000
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u_second_hierarchy/clk_gen2/CLK_OUT_DIV period: 40.000000
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u_second_hierarchy/clk_gen3/CLK_OUT_DIV period: 80.000000
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u_second_hierarchy/clk_gen3/CLK_OUT_MUL period: 20.000000
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u_second_hierarchy/clk_gen2/CLK_OUT_MUL period: 10.000000
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u_second_hierarchy/clk_gen/CLK_OUT_MUL period: 5.000000
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clk2 period: 100.000000
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clk_edge_shift/CLK_OUT period: 200.000000
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Number of clocks: 10
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Clock Period Waveform
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----------------------------------------------------
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clk 10.00 0.00 5.00
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u_second_hierarchy/clk_gen/CLK_OUT_DIV 20.00 0.00 10.00 (generated)
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u_second_hierarchy/clk_gen2/CLK_OUT_DIV 40.00 0.00 20.00 (generated)
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u_second_hierarchy/clk_gen3/CLK_OUT_DIV 80.00 0.00 40.00 (generated)
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u_second_hierarchy/clk_gen3/CLK_OUT_MUL 20.00 16.00 20.00 (generated)
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u_second_hierarchy/clk_gen2/CLK_OUT_MUL 10.00 8.00 10.00 (generated)
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u_second_hierarchy/clk_gen/CLK_OUT_MUL 5.00 4.00 5.00 (generated)
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clk2 100.00 0.00 50.00
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clk_edge_shift/CLK_OUT 200.00 0.00 100.00 (generated)
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clk_manual 400.00 0.00 200.00 (generated)

‎test/generated_clock.tcl‎

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read_liberty generated_clock.lib
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read_verilog generated_clock.v
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link_design generated_clock
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create_clock -name clk -period 10 [get_ports CLK_IN_1]
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create_clock -name clk2 -period 100 [get_ports CLK_IN_2]
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# Should see 9 clocks
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puts "Number of clocks: [ llength [get_clocks]]"
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# Report all clock periods
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foreach_in_collection clk [get_clocks] {
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puts "[get_object_name $clk] period: [get_attribute $clk period]"
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}
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# Use TCL command to create a generated clock from generated clock
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create_generated_clock \
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-name clk_manual \
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-source [get_pins clk_edge_shift/CLK_OUT] \
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-master_clock clk_edge_shift/CLK_OUT \
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-divide_by 2 \
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[get_ports CLK_OUT_2]
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# Should see 10 clocks
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puts "Number of clocks: [ llength [get_clocks]]"
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# Use command to validate waveforms
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report_clock_properties

‎test/generated_clock.v‎

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1+
module generated_clock (
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// Test basic test cases
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input wire CLK_IN_1,
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output wire slow_clk_int,
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output wire fast_clk_int,
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output wire slow_clk_out2,
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output wire fast_clk_out2,
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// Test liberty-defined nested clock output
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output wire slow_clk_out3,
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output wire fast_clk_out3,
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// Test edges/shifts (shifts not supported)
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input wire CLK_IN_2,
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output wire CLK_OUT_2
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);
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// Give one more level of hierarchy to test names
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second_hierarchy u_second_hierarchy (
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.clk_in(CLK_IN_1),
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.slow_clk_out(slow_clk_int),
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.fast_clk_out(fast_clk_int),
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.slow_clk_out2(slow_clk_out2),
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.fast_clk_out2(fast_clk_out2),
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.slow_clk_out3(slow_clk_out3),
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.fast_clk_out3(fast_clk_out3)
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);
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CLK_EDGE_SHIFT clk_edge_shift (
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.CLK_IN(CLK_IN_2),
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.CLK_OUT(CLK_OUT_2)
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);
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endmodule
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37+
module second_hierarchy (
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input wire clk_in,
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output wire slow_clk_out,
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output wire fast_clk_out,
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output wire slow_clk_out2,
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output wire fast_clk_out2,
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output wire slow_clk_out3,
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output wire fast_clk_out3
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);
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CLK_GEN clk_gen (
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.CLK_IN(clk_in),
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.CLK_OUT_DIV(slow_clk_out),
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.CLK_OUT_MUL(fast_clk_out)
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);
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CLK_GEN clk_gen2 (
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.CLK_IN(slow_clk_out),
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.CLK_OUT_DIV(slow_clk_out2),
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.CLK_OUT_MUL(fast_clk_out2)
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);
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CLK_GEN clk_gen3 (
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.CLK_IN(slow_clk_out2),
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.CLK_OUT_DIV(slow_clk_out3),
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.CLK_OUT_MUL(fast_clk_out3)
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);
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endmodule

‎test/regression_vars.tcl‎

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@@ -151,6 +151,7 @@ record_public_tests {
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get_lib_pins_of_objects
152152
get_noargs
153153
get_objrefs
154+
generated_clock
154155
liberty_arcs_one2one_1
155156
liberty_arcs_one2one_2
156157
liberty_backslash_eol

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