Skip to content

Latest commit

 

History

History

four_bit_ripple_adder

Folders and files

NameName
Last commit message
Last commit date

parent directory

..
 
 
 
 
 
 
 
 

Four-Bit Ripple Adder

Objective

This 4-bit adder takes advantage of the full adder module by taking four full adders and linking them together to add 2 four bit inputs. In the 4-bit adder, the first carry bit is set to zero because there is no initial carry bit as an input.

Waveforms

Simulation results from the Verilog representation of this Four-Bit Ripple Adder

Project%202%20Waveform%20for%20Four-Sixteen%20Decoder

Source Files

  • Four-Bit Ripple Adder Module - four_bit_adder.v
  • Four-Bit Ripple Adder Test Bench - four_bit_adder_test.v