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yatsenayatsena
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fix memory access ap to ubyte, fix error on without number, add support for custom
1 parent 5bc5f1b commit 190c5da

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4 files changed

+99
-20
lines changed

4 files changed

+99
-20
lines changed

‎increase_ap.crabox

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
; INCREASE AP INFINITELY
2+
inc ap
3+
j 0

‎source/app.d

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
import std.stdio;
22
import std.file;
33
import std.string;
4+
import std.conv;
45

56
import arsd.terminal;
67

@@ -30,6 +31,8 @@ void main(const string[] args)
3031

3132
if (args[1] == "simulate")
3233
{
34+
auto tps_arg = cli.find_opt(args, "-tps");
35+
3336
if (!source_arg.found)
3437
{
3538
writeln("source file not given");
@@ -52,7 +55,18 @@ void main(const string[] args)
5255
else
5356
{
5457
Simulator simulator = Simulator(instructions);
55-
simulator.start();
58+
double ticks_per_second = 1;
59+
if (tps_arg.found)
60+
{
61+
try
62+
ticks_per_second = to!double(tps_arg.option);
63+
catch(ConvException err)
64+
{
65+
writeln("expected double for `ticks per second`, got: ", tps_arg.option);
66+
return;
67+
}
68+
}
69+
simulator.start(ticks_per_second);
5670
}
5771

5872

‎source/lexer.d

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,10 @@ struct Lexer
7474
current++;
7575
if (current >= source.length) break;
7676
}
77-
tokens ~= Token(TokenType.number, value);
77+
if (value == "-")
78+
tokens ~= Token(TokenType.illegal, value);
79+
else
80+
tokens ~= Token(TokenType.number, value);
7881
break;
7982
default:
8083
string value;

‎source/simulator.d

Lines changed: 77 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -70,13 +70,41 @@ struct RegisterFile
7070
const byte r0 = 0;
7171

7272
private:
73-
byte r1;
74-
byte r2;
75-
byte r3;
76-
byte r4;
77-
byte r5;
78-
byte r6;
79-
byte ap;
73+
union
74+
{
75+
byte r1;
76+
ubyte r1_u;
77+
}
78+
union
79+
{
80+
byte r2;
81+
ubyte r2_u;
82+
}
83+
union
84+
{
85+
byte r3;
86+
ubyte r3_u;
87+
}
88+
union
89+
{
90+
byte r4;
91+
ubyte r4_u;
92+
}
93+
union
94+
{
95+
byte r5;
96+
ubyte r5_u;
97+
}
98+
union
99+
{
100+
byte r6;
101+
ubyte r6_u;
102+
}
103+
union
104+
{
105+
byte ap;
106+
ubyte ap_u;
107+
}
80108

81109
public:
82110
void reset()
@@ -106,6 +134,22 @@ public:
106134
}
107135
}
108136

137+
ubyte read_u(RegisterType r)
138+
{
139+
switch (r)
140+
{
141+
case RegisterType.r0: return r0;
142+
case RegisterType.r1: return r1_u;
143+
case RegisterType.r2: return r2_u;
144+
case RegisterType.r3: return r3_u;
145+
case RegisterType.r4: return r4_u;
146+
case RegisterType.r5: return r5_u;
147+
case RegisterType.r6: return r6_u;
148+
case RegisterType.ap: return ap_u;
149+
default: return r0;
150+
}
151+
}
152+
109153
void write(RegisterType rs, byte data)
110154
{
111155
switch (rs)
@@ -120,6 +164,21 @@ public:
120164
default: return;
121165
}
122166
}
167+
168+
void write_u(RegisterType rs, ubyte data)
169+
{
170+
switch (rs)
171+
{
172+
case RegisterType.r1: r1_u = data; return;
173+
case RegisterType.r2: r2_u = data; return;
174+
case RegisterType.r3: r3_u = data; return;
175+
case RegisterType.r4: r4_u = data; return;
176+
case RegisterType.r5: r5_u = data; return;
177+
case RegisterType.r6: r6_u = data; return;
178+
case RegisterType.ap: ap_u = data; return;
179+
default: return;
180+
}
181+
}
123182
}
124183

125184

@@ -210,17 +269,17 @@ struct Simulator
210269
this.registers.write(current_instruction.parameters[0].register, 0);
211270
break;
212271
case InstructionType.inc:
213-
this.registers.write(
272+
this.registers.write_u(
214273
current_instruction.parameters[0].register,
215-
ALU(ALU_OP.ADD, this.registers.read(current_instruction.parameters[0].register), 1));
274+
ALU(ALU_OP.ADD, this.registers.read_u(current_instruction.parameters[0].register), 1));
216275
break;
217276
case InstructionType.dec:
218-
this.registers.write(
277+
this.registers.write_u(
219278
current_instruction.parameters[0].register,
220-
ALU(ALU_OP.SUB, this.registers.read(current_instruction.parameters[0].register), 1));
279+
ALU(ALU_OP.SUB, this.registers.read_u(current_instruction.parameters[0].register), 1));
221280
break;
222281
case InstructionType.inv:
223-
this.memory[this.registers.read(RegisterType.ap)] =
282+
this.memory[this.registers.read_u(RegisterType.ap)] =
224283
ALU(ALU_OP.INV, this.registers.read(current_instruction.parameters[0].register), 0);
225284
break;
226285
case InstructionType.load:
@@ -229,34 +288,34 @@ struct Simulator
229288
this.memory[this.registers.read(RegisterType.ap)]);
230289
break;
231290
case InstructionType.store:
232-
this.memory[this.registers.read(RegisterType.ap)] =
291+
this.memory[this.registers.read_u(RegisterType.ap)] =
233292
this.registers.read(current_instruction.parameters[0].register);
234293
break;
235294
case InstructionType.brnz:
236-
if (this.memory[this.registers.read(RegisterType.ap)] != 0)
295+
if (this.memory[this.registers.read_u(RegisterType.ap)] != 0)
237296
pc.clock(BranchType.relative, cast(byte)(current_instruction.parameters[0].number));
238297
return;
239298
case InstructionType.j:
240299
pc.clock(BranchType.absolute, cast(ubyte)(current_instruction.parameters[0].number));
241300
return;
242301
case InstructionType.jal:
243-
this.memory[this.registers.read(RegisterType.ap)] = this.pc.address;
302+
this.memory[this.registers.read_u(RegisterType.ap)] = this.pc.address;
244303
pc.clock(BranchType.absolute, cast(ubyte)(current_instruction.parameters[0].number));
245304
return;
246305
case InstructionType.or:
247-
this.memory[this.registers.read(RegisterType.ap)] =
306+
this.memory[this.registers.read_u(RegisterType.ap)] =
248307
ALU(ALU_OP.OR,
249308
this.registers.read(current_instruction.parameters[0].register),
250309
this.registers.read(current_instruction.parameters[1].register));
251310
break;
252311
case InstructionType.add:
253-
this.memory[this.registers.read(RegisterType.ap)] =
312+
this.memory[this.registers.read_u(RegisterType.ap)] =
254313
ALU(ALU_OP.ADD,
255314
this.registers.read(current_instruction.parameters[0].register),
256315
this.registers.read(current_instruction.parameters[1].register));
257316
break;
258317
case InstructionType.sub:
259-
this.memory[this.registers.read(RegisterType.ap)] =
318+
this.memory[this.registers.read_u(RegisterType.ap)] =
260319
ALU(ALU_OP.SUB,
261320
this.registers.read(current_instruction.parameters[0].register),
262321
this.registers.read(current_instruction.parameters[1].register));

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