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lk2nd: smp: add msm8994 cpu boot support
Signed-off-by: Eugene Lepshy <[email protected]>
1 parent 2008249 commit 7f91ae3

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4 files changed

+301
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‎lk2nd/smp/cpu-boot.c

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@@ -90,6 +90,8 @@ bool cpu_boot(const void *dtb, int node, uint32_t mpidr)
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*/
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extra_reg = read_phandle_reg(dtb, node, "clocks");
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cpu_boot_cortex_a(acc, extra_reg);
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#elif CPU_BOOT_CORTEX_A_MSM8994
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cpu_boot_cortex_a_msm8994(mpidr);
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#elif CPU_BOOT_KPSSV1
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extra_reg = read_phandle_reg(dtb, node, "qcom,saw");
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if (!extra_reg)

‎lk2nd/smp/cpu-boot.h

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@@ -6,6 +6,15 @@ int cpu_boot_set_addr(uintptr_t addr, bool arm64);
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bool cpu_boot(const void *dtb, int node, uint32_t mpidr);
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void cpu_boot_cortex_a(uint32_t base, uint32_t apcs_base);
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/**
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* cpu_boot_cortex_a_msm8994() - This function enables msm8994/2 core
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* @mpidr: This param used to determine which exactly core this function enables
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*
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* As l2 cache for first(boot) cluster enabled by lk1st,
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* this function skips it and work only for second cluster
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*/
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void cpu_boot_cortex_a_msm8994(uint32_t mpidr);
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void cpu_boot_kpssv1(uint32_t reg, uint32_t saw_reg);
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void cpu_boot_kpssv2(uint32_t reg, uint32_t l2_saw_base);
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‎lk2nd/smp/gpl/cortex-a-msm8994.c

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@@ -0,0 +1,287 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <arch/defines.h>
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#include <bits.h>
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#include <debug.h>
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#include <kernel/thread.h>
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#include <platform/timer.h>
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#include <reg.h>
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#include "../cpu-boot.h"
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#define CPU_PWR_CTL 0x4
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#define APC_PWR_GATE_CTL 0x14
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#define L1_RST_DIS 0x284
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#define L2_VREG_CTL 0x1c
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#define L2_PWR_CTL 0x14
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#define L2_PWR_CTL_OVERRIDE 0xc
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#define L2_PWR_STATUS_L2_HS_STS_MSM8994 (BIT(9) | BIT(28))
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// delay for voltage to settle on the core
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#define REGULATOR_SETUP_VOLTAGE_TIMEOUT 2000
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/**
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* enum msm8994_cpu_node_mpidrs - Enum that used for mapping cores and its mpidrs
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*/
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enum msm8994_cpu_node_mpidrs {
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CPU0 = 0x0,
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CPU1 = 0x1,
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CPU2 = 0x2,
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CPU3 = 0x3,
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CPU4 = 0x100,
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CPU5 = 0x101,
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CPU6 = 0x102,
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CPU7 = 0x103,
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};
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/**
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* enum msm8994_cpu_clusters - Enum that used for clusters
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* @first: describes little cluster
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* @second: describes BIG cluster
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*/
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enum msm8994_cpu_clusters {
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first,
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second,
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};
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/**
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* struct msm8994_cpu_info - This struct used to describe the core values
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* needed to enable it
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* @base: this value had got from downstream dts this way: cpu@X -> qcom,acc -> reg
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* @cache_info: description of next-level-cache node in cpu@X
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*/
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struct msm8994_cpu_info {
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uint32_t base;
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const struct msm8994_cpu_cache_info *cache_info;
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};
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/**
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* struct msm8994_cpu_cache_info - This struct used to describe cache node
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* (and children's) values needed to enable the cpu cache
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* @l2ccc_base: this value had got from downstream dts this way: l2-cache -> power-domain -> reg
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* @vctl_base_0: l2-cache -> power-domain -> qcom,vctl-node -> reg (first value of first tuple)
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* @vctl_base_1: l2-cache -> power-domain -> qcom,vctl-node -> reg (first value of second tuple)
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* @vctl_val: l2-cache -> power-domain -> qcom,vctl-val (may be absent, then set as 0)
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*/
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struct msm8994_cpu_cache_info {
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uint32_t l2ccc_base;
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uint32_t vctl_base_0;
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uint32_t vctl_base_1;
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uint32_t vctl_val;
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};
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static const struct msm8994_cpu_cache_info cache_info[] = {
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[first] = {
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.l2ccc_base = 0xf900d000,
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.vctl_base_0 = 0xf9012000,
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.vctl_base_1 = 0xf900d210,
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.vctl_val = 0,
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},
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[second] = {
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.l2ccc_base = 0xf900f000,
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.vctl_base_0 = 0xf9013000,
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.vctl_base_1 = 0xf900f210,
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.vctl_val = 0xb8,
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},
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};
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static const struct msm8994_cpu_info cpu_info[] = {
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[CPU0] = {
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.base = 0xf908b000,
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.cache_info = &cache_info[first],
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},
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[CPU1] = {
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.base = 0xf909b000,
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.cache_info = &cache_info[first],
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},
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[CPU2] = {
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.base = 0xf90ab000,
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.cache_info = &cache_info[first],
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},
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[CPU3] = {
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.base = 0xf90bb000,
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.cache_info = &cache_info[first],
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},
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[CPU4] = {
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.base = 0xf90cb000,
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.cache_info = &cache_info[second],
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},
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[CPU5] = {
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.base = 0xf90db000,
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.cache_info = &cache_info[second],
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},
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[CPU6] = {
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.base = 0xf90eb000,
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.cache_info = &cache_info[second],
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},
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[CPU7] = {
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.base = 0xf90fb000,
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.cache_info = &cache_info[second],
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},
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};
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/**
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* msm_spm_turn_on_cpu_rail() - Power on cpu rail before turning on core
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* @vctl_base_0: first qcom,vctl-node reg address
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* @vctl_base_1: second qcom,vctl-node reg address
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* @vctl_val: The value to be set on the rail
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*/
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static void msm_spm_turn_on_cpu_rail(uint32_t vctl_base_0, uint32_t vctl_base_1,
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unsigned int vctl_val)
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{
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if (vctl_base_1) {
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/*
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* Program Q2S to disable SPM legacy mode and ignore Q2S
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* channel requests.
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* bit[1] = qchannel_ignore = 1
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* bit[2] = spm_legacy_mode = 0
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*/
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writel(0x2, vctl_base_1);
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dsb();
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}
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/* Set the CPU supply regulator voltage */
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vctl_val = (vctl_val & 0xFF);
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writel(vctl_val, vctl_base_0 + L2_VREG_CTL);
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dsb();
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udelay(REGULATOR_SETUP_VOLTAGE_TIMEOUT);
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/* Enable the CPU supply regulator*/
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vctl_val = 0x30080;
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writel(vctl_val, vctl_base_0 + L2_VREG_CTL);
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dsb();
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udelay(REGULATOR_SETUP_VOLTAGE_TIMEOUT);
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}
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/**
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* power_on_l2_cache_msm8994() - This function used to enable l2 cache
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* @l2ccc_base: value of l2 clock controller reg
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* @vctl_base_0: first qcom,vctl-node reg address
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* @vctl_base_1: second qcom,vctl-node reg address
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* @vctl_val: The value to be set on the rail
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*
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* As l2 cache for first(boot) cluster enabled by lk1st,
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* this function skips it and work only for second cluster
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* Function has a check if cache at @l2ccc_base already enabled
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*/
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static void power_on_l2_cache_msm8994(uint32_t l2ccc_base, uint32_t vctl_base_0,
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uint32_t vctl_base_1, uint32_t vctl_val) {
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/* Skip if cluster L2 is already powered on */
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if (readl(l2ccc_base + L2_PWR_CTL) & L2_PWR_STATUS_L2_HS_STS_MSM8994)
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return;
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dprintf(INFO, "Powering on L2 cache @ %#08x\n", l2ccc_base);
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if(vctl_val != 0) {
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dprintf(INFO, "Not found qcom,vctl-val for this l2 cache node, so skip msm_spm_turn_on_cpu_rail\n");
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msm_spm_turn_on_cpu_rail(vctl_base_0, vctl_base_1, vctl_val);
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}
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enter_critical_section();
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/* Enable L1 invalidation by h/w */
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writel(0x00000000, l2ccc_base + L1_RST_DIS);
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dsb();
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/* Assert PRESETDBGn */
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writel(0x00400000 , l2ccc_base + L2_PWR_CTL_OVERRIDE);
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dsb();
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/* Close L2/SCU Logic GDHS and power up the cache */
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writel(0x00029716 , l2ccc_base + L2_PWR_CTL);
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dsb();
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udelay(8);
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/* De-assert L2/SCU memory Clamp */
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writel(0x00023716 , l2ccc_base + L2_PWR_CTL);
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dsb();
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/* Wakeup L2/SCU RAMs by deasserting sleep signals */
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writel(0x0002371E , l2ccc_base + L2_PWR_CTL);
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dsb();
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udelay(8);
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/* Un-gate clock and wait for sequential waking up
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* of L2 rams with a delay of 2*X0 cycles
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*/
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writel(0x0002371C , l2ccc_base + L2_PWR_CTL);
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dsb();
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udelay(4);
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/* De-assert L2/SCU logic clamp */
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writel(0x0002361C , l2ccc_base + L2_PWR_CTL);
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dsb();
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udelay(2);
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/* De-assert L2/SCU logic reset */
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writel(0x00022218 , l2ccc_base + L2_PWR_CTL);
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dsb();
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udelay(4);
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/* Turn on the PMIC_APC */
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writel(0x10022218 , l2ccc_base + L2_PWR_CTL);
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dsb();
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/* De-assert PRESETDBGn */
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writel(0x00000000 , l2ccc_base + L2_PWR_CTL_OVERRIDE);
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dsb();
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exit_critical_section();
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}
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void cpu_boot_cortex_a_msm8994(uint32_t mpidr)
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{
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uint32_t base, l2ccc_base, vctl_base_0, vctl_base_1, vctl_val;
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struct msm8994_cpu_info *info = &cpu_info[mpidr];
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base = info->base;
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l2ccc_base = info->cache_info->l2ccc_base;
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vctl_base_0 = info->cache_info->vctl_base_0;
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vctl_base_1 = info->cache_info->vctl_base_1;
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vctl_val = info->cache_info->vctl_val;
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if (l2ccc_base)
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power_on_l2_cache_msm8994(l2ccc_base, vctl_base_0, vctl_base_1, vctl_val);
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enter_critical_section();
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/* Assert head switch enable few */
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writel(0x00000001, base + APC_PWR_GATE_CTL);
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dsb();
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udelay(1);
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/* Assert head switch enable rest */
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writel(0x00000003, base + APC_PWR_GATE_CTL);
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dsb();
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udelay(1);
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/* De-assert coremem clamp. This is asserted by default */
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writel(0x00000079, base + CPU_PWR_CTL);
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dsb();
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udelay(2);
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/* Close coremem array gdhs */
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writel(0x0000007D, base + CPU_PWR_CTL);
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dsb();
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udelay(2);
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/* De-assert clamp */
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writel(0x0000003D, base + CPU_PWR_CTL);
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dsb();
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/* De-assert clamp */
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writel(0x0000003C, base + CPU_PWR_CTL);
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dsb();
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udelay(1);
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/* De-assert core0 reset */
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writel(0x0000000C, base + CPU_PWR_CTL);
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dsb();
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/* Assert PWRDUP */
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writel(0x0000008C, base + CPU_PWR_CTL);
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dsb();
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exit_critical_section();
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}

‎lk2nd/smp/rules.mk

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@@ -8,6 +8,9 @@ OBJS += $(patsubst %.c,%.o, $(wildcard $(LOCAL_DIR)/clock-$(PLATFORM).c))
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ifneq ($(filter msm8226 msm8610 msm8909 msm8916, $(PLATFORM)),)
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CPU_BOOT_OBJ := $(LOCAL_DIR)/cortex-a.o
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DEFINES += CPU_BOOT_CORTEX_A=1
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else ifneq ($(filter msm8994, $(PLATFORM)),)
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CPU_BOOT_OBJ := $(if $(BUILD_GPL), $(LOCAL_DIR)/gpl/cortex-a-msm8994.o)
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DEFINES += CPU_BOOT_CORTEX_A_MSM8994=1
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else ifneq ($(filter apq8084 msm8974, $(PLATFORM)),)
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CPU_BOOT_OBJ := $(if $(BUILD_GPL), $(LOCAL_DIR)/gpl/krait.o)
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DEFINES += CPU_BOOT_KPSSV2=1

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