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DE2_115_uClinux.qsf
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DE2_115_uClinux.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2012 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 12.1 Build 177 11/07/2012 SJ Full Version
# Date created = 07:38:54 March 14, 2013
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# DE2_115_uClinux_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY DE2_115_uClinux
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:38:54 MARCH 14, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_Y2 -to CLOCK_50
set_location_assignment PIN_Y7 -to SDRAM_ADD[12]
set_location_assignment PIN_AA5 -to SDRAM_ADD[11]
set_location_assignment PIN_R5 -to SDRAM_ADD[10]
set_location_assignment PIN_Y6 -to SDRAM_ADD[9]
set_location_assignment PIN_Y5 -to SDRAM_ADD[8]
set_location_assignment PIN_AA7 -to SDRAM_ADD[7]
set_location_assignment PIN_W7 -to SDRAM_ADD[6]
set_location_assignment PIN_W8 -to SDRAM_ADD[5]
set_location_assignment PIN_V5 -to SDRAM_ADD[4]
set_location_assignment PIN_P1 -to SDRAM_ADD[3]
set_location_assignment PIN_U8 -to SDRAM_ADD[2]
set_location_assignment PIN_V8 -to SDRAM_ADD[1]
set_location_assignment PIN_R6 -to SDRAM_ADD[0]
set_location_assignment PIN_R4 -to SDRAM_BA[1]
set_location_assignment PIN_U7 -to SDRAM_BA[0]
set_location_assignment PIN_V7 -to SDRAM_CASn
set_location_assignment PIN_AA6 -to SDRAM_CKE
set_location_assignment PIN_AE5 -to SDRAM_CLK
set_location_assignment PIN_T4 -to SDRAM_CSn
set_location_assignment PIN_U1 -to SDRAM_DQ[31]
set_location_assignment PIN_U4 -to SDRAM_DQ[30]
set_location_assignment PIN_T3 -to SDRAM_DQ[29]
set_location_assignment PIN_R3 -to SDRAM_DQ[28]
set_location_assignment PIN_R2 -to SDRAM_DQ[27]
set_location_assignment PIN_R1 -to SDRAM_DQ[26]
set_location_assignment PIN_R7 -to SDRAM_DQ[25]
set_location_assignment PIN_U5 -to SDRAM_DQ[24]
set_location_assignment PIN_L7 -to SDRAM_DQ[23]
set_location_assignment PIN_M7 -to SDRAM_DQ[22]
set_location_assignment PIN_M4 -to SDRAM_DQ[21]
set_location_assignment PIN_N4 -to SDRAM_DQ[20]
set_location_assignment PIN_N3 -to SDRAM_DQ[19]
set_location_assignment PIN_P2 -to SDRAM_DQ[18]
set_location_assignment PIN_L8 -to SDRAM_DQ[17]
set_location_assignment PIN_M8 -to SDRAM_DQ[16]
set_location_assignment PIN_AC2 -to SDRAM_DQ[15]
set_location_assignment PIN_AB3 -to SDRAM_DQ[14]
set_location_assignment PIN_AC1 -to SDRAM_DQ[13]
set_location_assignment PIN_AB2 -to SDRAM_DQ[12]
set_location_assignment PIN_AA3 -to SDRAM_DQ[11]
set_location_assignment PIN_AB1 -to SDRAM_DQ[10]
set_location_assignment PIN_Y4 -to SDRAM_DQ[9]
set_location_assignment PIN_Y3 -to SDRAM_DQ[8]
set_location_assignment PIN_U3 -to SDRAM_DQ[7]
set_location_assignment PIN_V1 -to SDRAM_DQ[6]
set_location_assignment PIN_V2 -to SDRAM_DQ[5]
set_location_assignment PIN_V3 -to SDRAM_DQ[4]
set_location_assignment PIN_W1 -to SDRAM_DQ[3]
set_location_assignment PIN_V4 -to SDRAM_DQ[2]
set_location_assignment PIN_W2 -to SDRAM_DQ[1]
set_location_assignment PIN_W3 -to SDRAM_DQ[0]
set_location_assignment PIN_N8 -to SDRAM_DQM[3]
set_location_assignment PIN_K8 -to SDRAM_DQM[2]
set_location_assignment PIN_W4 -to SDRAM_DQM[1]
set_location_assignment PIN_U2 -to SDRAM_DQM[0]
set_location_assignment PIN_U6 -to SDRAM_RASn
set_location_assignment PIN_V6 -to SDRAM_WEn
set_location_assignment PIN_G12 -to UART_RX
set_location_assignment PIN_G9 -to UART_TX
set_global_assignment -name QIP_FILE qsys/synthesis/qsys.qip
set_global_assignment -name QIP_FILE altpll0.qip
set_global_assignment -name BDF_FILE DE2_115_uClinux.bdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top