add memory minitest

Author: mmicko

minitests/memory/.gitignore

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+*.pnl
+*.bit
+*.log
+*_tdroute.v

minitests/memory/memory.v

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+module top(input clk,input p1, input p2);
+
+genvar i;
+generate for (i = 0; i < 64; i = i + 1)
+begin: part1
+	(* keep *)
+	EG_PHY_BRAM bram_i(.clka(clk));
+end
+endgenerate
+
+genvar j;
+generate for (j = 0; j < 16; j = j + 1)
+begin: part2
+	(* keep *)
+	EG_PHY_BRAM32K  bram32_j(.clka(clk));
+end
+endgenerate
+
+endmodule

minitests/memory/run.tcl

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+import_device eagle_s20.db -package BG256
+read_verilog memory.v
+optimize_rtl
+optimize_gate
+legalize_phy_inst
+place
+route
+write_pnl memory.pnl
+bitgen -bit "memory.bit" -version 0X00 -g ucode:000000000000000000000000 -info -log_file memory.log