75 MHz

Author: jean-m-cyr

DE10_NANO_SOC_GHRD.qsf

@@ -403,13 +403,10 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS 8
 set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
 set_global_assignment -name VERILOG_FILE DE10_NANO_SOC_GHRD.v
 set_global_assignment -name SDC_FILE DE10_NANO_SOC_GHRD.sdc
-set_global_assignment -name VERILOG_FILE ip/intr_capturer/intr_capturer.v
 set_global_assignment -name VERILOG_FILE ip/edge_detect/altera_edge_detector.v
 set_global_assignment -name VERILOG_FILE ip/debounce/debounce.v
 set_global_assignment -name QIP_FILE soc_system/synthesis/soc_system.qip
 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
 
-set_global_assignment -name VERILOG_FILE miner_ip/permutation.v
-set_global_assignment -name VERILOG_FILE miner_ip/sha3_256_miner.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

hps_isw_handoff/soc_system_hps_0/id

@@ -1,3 +1,3 @@
 Do not change the content of this file
-MD5 : d53a809f407df8110d573e44da1c892a
-CRC32 : 0xFE9504BC
+MD5 : 05f129a584ff7fc8ea0c2375bf10f748
+CRC32 : 0x04642965

soc_system.qsys

@@ -818,7 +818,7 @@
   <parameter name="width" value="8" />
  </module>
  <module name="miner_0" kind="miner" version="1.1" enabled="1">
-  <parameter name="MINER_CLK_MHZ" value="78 MHz" />
+  <parameter name="MINER_CLK_MHZ" value="75 MHz" />
   <parameter name="MINER_MAJ_VER" value="1" />
   <parameter name="MINER_MIN_VER" value="1" />
   <parameter name="STAGES" value="8" />

soc_system.sopcinfo

@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="soc_system" kind="soc_system" version="1.0" fabric="QSYS">
  <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
- <!-- 2020.08.04.19:37:28 -->
+ <!-- 2020.08.05.18:04:59 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1596584236</value>
+  <value>1596665087</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
@@ -76411,7 +76411,7 @@ the requested settings for a module instance. -->
   </assignment>
   <parameter name="MINER_CLK_MHZ">
    <type>java.lang.String</type>
-   <value>78 MHz</value>
+   <value>75 MHz</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>