update compliance running environment

Author: Talha-Ahmed-1

Makefile

@@ -34,4 +34,4 @@ clean:
 
 
 compliance:
-	./run_compliance.sh $(TEST) $(ISA)
+	./run_compliance.sh $(ISA) $(TEST)

riscv-target/nucleusrv/device/rv32i/Makefile.include

@@ -10,7 +10,7 @@ RUN_TARGET=\
     > $(*).stdout; \
     `grep '^[a-f0-9]\+$$' $(*).stdout > $(*).signature.output`;
 
-RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_PREFIX   ?= riscv64-unknown-elf-
 RISCV_GCC      ?= $(RISCV_PREFIX)gcc
 RISCV_OBJCOPY  ?= $(RISCV_PREFIX)objcopy
 RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump

run_compliance.sh

@@ -3,8 +3,20 @@
 export NUCLEUSRV=$PWD
 FILE=$NUCLEUSRV/test_run_dir/Top_Test/VTop
 
-TEST=$1
+if [ -f $FILE ]; then
+        echo "$FILE exists."
+else 
+        echo "$FILE does not exist."
+        echo "Running sbt testOnly TopTest"
+        sbt "testOnly nucleusrv.components.TopTest"
+fi
+
+ISA=$1
+TEST=$2
+
 cd $NUCLEUSRV/riscv-arch-test
-make clean TARGETDIR=$NUCLEUSRV/riscv-target RISCV_PREFIX=riscv32-unknown-elf-  RISCV_TARGET=nucleusrv RISCV_DEVICE=rv32i RISCV_ISA=rv32im RISCV_TEST=$TEST TARGET_SIM=$NUCLEUSRV/test_run_dir/Top_Test/VTop
-make TARGETDIR=$NUCLEUSRV/riscv-target RISCV_PREFIX=riscv32-unknown-elf- RISCV_TARGET=nucleusrv RISCV_DEVICE=rv32i RISCV_ISA=rv32imc RISCV_TEST=$TEST TARGET_SIM=$NUCLEUSRV/test_run_dir/Top_Test/VTop | tee Test_result.txt
+
+make clean TARGETDIR=$NUCLEUSRV/riscv-target RISCV_PREFIX=riscv64-unknown-elf-  RISCV_TARGET=nucleusrv RISCV_DEVICE=rv32i RISCV_ISA=$ISA RISCV_TEST=$TEST TARGET_SIM=$NUCLEUSRV/test_run_dir/Top_Test/VTop
+make TARGETDIR=$NUCLEUSRV/riscv-target RISCV_PREFIX=riscv64-unknown-elf- RISCV_TARGET=nucleusrv RISCV_DEVICE=rv32i RISCV_ISA=$ISA RISCV_TEST=$TEST TARGET_SIM=$NUCLEUSRV/test_run_dir/Top_Test/VTop | tee Test_result.txt
+
 cd ../

src/main/scala/components/Core.scala

@@ -257,7 +257,7 @@ class Core(M:Boolean = false) extends Module {
     wb_data := MEM.io.readData
     wb_addr := mem_reg_wra
   }.elsewhen(mem_reg_ctl_memToReg === 2.U) {
-      wb_data := mem_reg_pc
+      wb_data := mem_reg_pc+4.U
       wb_addr := mem_reg_wra
     }
     .otherwise {
@@ -273,11 +273,4 @@ class Core(M:Boolean = false) extends Module {
   ID.ctl_writeEnable := mem_reg_ctl_regWrite
   io.pin := wb_data
 
-  /*******************************
-   * Log, in format of Spike-ISS *
-   *******************************/
-
-   printf("PC: %x, INST: %x, REG_NO: %d, REG_VAL: %x\n", ex_reg_pc, ex_reg_ins,
-      Mux(mem_reg_ctl_regWrite, mem_reg_wra, 0.U),
-      Mux(mem_reg_ctl_regWrite, wb_data, 0.U))
 }

src/test/scala/components/TopTest.scala

@@ -31,7 +31,7 @@ class TopTest extends FreeSpec with ChiselScalatestTester {
       // test(new Top(new WBRequest(), new WBResponse(), Module(new WishboneAdapter()), Module(new WishboneAdapter()), programFile)).withAnnotation(Seq(VerilatorBackendAnnotation)){ c =>
         test(new Top(programFile, dataFile)).withAnnotations(Seq(VerilatorBackendAnnotation)){ c =>
           c.clock.setTimeout(0)
-          c.clock.step(20)
+          c.clock.step(10000)
       }
   }
   // printf("logs enclosed\n")