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x86asm: Add vm* and iret[wlq] insns
The no-operand vm* instructions can be interpreted as having a funny modrm byte, but unlike no-operand OPC_MODRM it's also the r/m field which selects the insn, not (only) the reg field (aka group), so we need another insn type.
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i386-asm.c

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@@ -40,6 +40,8 @@
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#define OPC_ARITH 0x30 /* arithmetic opcodes */
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#define OPC_FARITH 0x40 /* FPU arithmetic opcodes */
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#define OPC_TEST 0x50 /* test opcodes */
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#define OPC_0F01 0x60 /* 0x0f01XX (group 7, XX is 2nd opcode,
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no operands and unstructured mod/rm) */
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#define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i))
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#define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */
@@ -1072,6 +1074,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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}
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if (OPCT_IS(pa->instr_type, OPC_TEST))
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v += test_bits[opcode - pa->sym];
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else if (OPCT_IS(pa->instr_type, OPC_0F01))
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v |= 0x0f0100;
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op1 = v >> 16;
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if (op1)
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g(op1);

tests/asmtest.S

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@@ -632,10 +632,19 @@ int $0x10
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leave
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int3
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iret
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iretw
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iretl
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#ifdef __x86_64__
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iretq
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#endif
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rsm
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hlt
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wait
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nop
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vmcall
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vmlaunch
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vmresume
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vmxoff
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/* XXX: handle prefixes */
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#if 0

x86_64-asm.h

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@@ -30,13 +30,21 @@
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DEF_ASM_OP0(int3, 0xcc)
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DEF_ASM_OP0(into, 0xce)
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DEF_ASM_OP0(iret, 0xcf)
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DEF_ASM_OP0(iretw, 0x66cf)
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DEF_ASM_OP0(iretl, 0xcf)
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DEF_ASM_OP0(iretq, 0x48cf)
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DEF_ASM_OP0(rsm, 0x0faa)
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DEF_ASM_OP0(hlt, 0xf4)
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DEF_ASM_OP0(wait, 0x9b)
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DEF_ASM_OP0(nop, 0x90)
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DEF_ASM_OP0(pause, 0xf390)
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DEF_ASM_OP0(xlat, 0xd7)
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DEF_ASM_OP0L(vmcall, 0xc1, 0, OPC_0F01)
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DEF_ASM_OP0L(vmlaunch, 0xc2, 0, OPC_0F01)
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DEF_ASM_OP0L(vmresume, 0xc3, 0, OPC_0F01)
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DEF_ASM_OP0L(vmxoff, 0xc4, 0, OPC_0F01)
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/* strings */
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ALT(DEF_ASM_OP0L(cmpsb, 0xa6, 0, OPC_BWLX))
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ALT(DEF_ASM_OP0L(scmpb, 0xa6, 0, OPC_BWLX))

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