Setting program counter via lua scripting breaks under certain conditions

[utz82]

Running the following code on Channel F

halt br halt

and setting the program counter with the following sequence

emu.pause()
manager:machine().devices[":maincpu"].state["PC0"].value = n
emu.unpause()

fails approx. 50% of the time, setting PC0 to an arbitrary value instead.

Adding a "nop" to the halting loop fixes the issue. See here for more context.

[ajrhacker]

This bug is specific to the F8 core, but other CPU cores have been known to have similar flaws. The basic problem is that debugger_instruction_hook is called after the instruction prefetch and incrementing of PC0, and adjusting PC0 at this point has no effect on the opcode that was just latched.

Several of MAME's CPU cores that prefetch their instructions (e.g. 6502) work around this by forcing an instantaneous prefetch when the program counter is meddled with. Another logical fix might be to jam NOP into the instruction register (as various CPUs are documented to do internally when their normal fetch sequence is disrupted by a program transfer), but the wasted cycle this causes may be undesirable.

[utz82]

Thanks for the info, the trick with jamming NOP seems quite useful. I don't mind a few extra cycles for my use-case. How exactly do I do that though? Alternatively, is there a way to force a prefetch from LUA (without enabling the debugger)?