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Issues list

[SystemVerilog] Create style guide torture test
#3 opened Jul 3, 2019 by imphil
1
Power and other implementation considerations
#10 opened Oct 18, 2019 by GregAC
5
[security] Provide RTL coding style guidance for security critical applications
#14 opened Jan 2, 2020 by msfschaffner
@asb @GregAC
@eunchan @imphil @vogelpi @cdgori @sjgitty @msfschaffner
3
Recommendations around xprop in simulations
#31 opened Mar 24, 2020 by GregAC
11
Scope of this style guide and questions
#41 opened Aug 20, 2020 by hirooih
3
Use of SystemVerilog Interfaces
#52 opened May 4, 2021 by MikeOpenHWGroup
12
[sv] How to format module instantiations that fit in a single line?
#53 opened May 19, 2021 by imphil
5
Linting file for spyglass question Further information is requested
#56 opened Oct 8, 2021 by rahulraveendran15-coder
5
Parameter naming convention inconsistencies
#63 opened Oct 18, 2022 by colluca
Continuous assignment from argumentless functions
#67 opened Aug 2, 2023 by sifferman
2
ProTip! Updated in the last three days: updated:>2025-03-20.