@@ -433,6 +433,9 @@ architecture top of afc_ref_fofb_ctrl_gen is
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-- FOFB CC
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constant c_NUM_FOFC_CC_CORES : natural := 2 ;
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+ -- SYS ID
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+ constant c_NUM_SYS_ID_CORES : natural := 1 ;
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+
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constant c_BPMS : integer := 1 ;
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constant c_FAI_DW : integer := 16 ;
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constant c_DMUX : integer := 2 ;
@@ -478,6 +481,15 @@ architecture top of afc_ref_fofb_ctrl_gen is
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signal acq_dcc_fmc_packet : t_fofb_cc_packet;
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signal acq_dcc_fmc_valid : std_logic := '0' ;
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+ -- ---------------------------------------------------------------------------
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+ -- FOFB system identification signals
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+ -- ---------------------------------------------------------------------------
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+
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+ signal bpm_pos_flat_x : t_bpm_pos_arr(c_MAX_NUM_P2P_BPM_POS/ 2 - 1 downto 0 );
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+ signal bpm_pos_flat_x_rcvd : std_logic_vector (c_MAX_NUM_P2P_BPM_POS/ 2 - 1 downto 0 );
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+ signal bpm_pos_flat_y : t_bpm_pos_arr(c_MAX_NUM_P2P_BPM_POS/ 2 - 1 downto 0 );
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+ signal bpm_pos_flat_y_rcvd : std_logic_vector (c_MAX_NUM_P2P_BPM_POS/ 2 - 1 downto 0 );
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+
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-- ---------------------------------------------------------------------------
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-- RTM signals
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-- ---------------------------------------------------------------------------
@@ -684,13 +696,14 @@ architecture top of afc_ref_fofb_ctrl_gen is
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constant c_ACQ_FIFO_SIZE : natural := 256 ;
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- -- Number of acquisition cores. Same as the number of DCC
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- constant c_ACQ_NUM_CORES : natural := c_NUM_FOFC_CC_CORES + c_RTM_LAMP_NUM_CORES;
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+ -- Number of acquisition cores
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+ constant c_ACQ_NUM_CORES : natural := c_NUM_FOFC_CC_CORES + c_RTM_LAMP_NUM_CORES + c_NUM_SYS_ID_CORES ;
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-- Acquisition core IDs
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constant c_ACQ_CORE_RTM_LAMP_ID : natural := 0 ;
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constant c_ACQ_CORE_CC_FMC_OR_RTM_ID : natural := 1 ;
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constant c_ACQ_CORE_CC_P2P_ID : natural := 2 ;
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+ constant c_ACQ_CORE_SYS_ID_ID : natural := 3 ;
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-- Type of DDR3 core interface
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constant c_DDR_INTERFACE_TYPE : string := " AXIS" ;
@@ -767,6 +780,7 @@ architecture top of afc_ref_fofb_ctrl_gen is
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constant c_TRIG_MUX_RTM_LAMP_ID : natural := c_ACQ_CORE_RTM_LAMP_ID;
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constant c_TRIG_MUX_CC_FMC_ID : natural := c_ACQ_CORE_CC_FMC_OR_RTM_ID;
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constant c_TRIG_MUX_CC_P2P_ID : natural := c_ACQ_CORE_CC_P2P_ID;
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+ constant c_TRIG_MUX_SYS_ID_ID : natural := c_ACQ_CORE_SYS_ID_ID;
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constant c_TRIG_MUX_NUM_CORES : natural := c_ACQ_NUM_CORES;
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@@ -1804,11 +1818,10 @@ begin
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bpm_pos_index_i => fofb_proc_bpm_pos_index,
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bpm_pos_valid_i => fofb_proc_bpm_pos_valid,
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bpm_pos_flat_clear_i => or fofb_sp_valid_arr,
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- -- TODO: connect on acq channel
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- bpm_pos_flat_x_o => open ,
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- bpm_pos_flat_x_rcvd_o => open ,
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- bpm_pos_flat_y_o => open ,
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- bpm_pos_flat_y_rcvd_o => open ,
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+ bpm_pos_flat_x_o => bpm_pos_flat_x,
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+ bpm_pos_flat_x_rcvd_o => bpm_pos_flat_x_rcvd,
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+ bpm_pos_flat_y_o => bpm_pos_flat_y,
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+ bpm_pos_flat_y_rcvd_o => bpm_pos_flat_y_rcvd,
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wb_slv_i => user_wb_out(c_FOFB_SYS_ID_ID),
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wb_slv_o => user_wb_in(c_FOFB_SYS_ID_ID)
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);
@@ -2133,6 +2146,9 @@ begin
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fs_clk_array(c_ACQ_CORE_RTM_LAMP_ID) <= clk_sys;
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fs_rst_n_array(c_ACQ_CORE_RTM_LAMP_ID) <= clk_sys_rstn;
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+ fs_clk_array(c_ACQ_CORE_SYS_ID_ID) <= clk_sys;
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+ fs_rst_n_array(c_ACQ_CORE_SYS_ID_ID) <= clk_sys_rstn;
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+
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gen_acq_clks : for i in 0 to c_ACQ_NUM_CORES- 1 generate
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fs_ce_array(i) <= '1' ;
@@ -2200,6 +2216,26 @@ begin
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acq_chan_array(c_ACQ_CORE_CC_P2P_ID, c_ACQ_DCC_ID).dvalid <= fofb_fod_dat_val(c_FOFB_CC_P2P_ID)(0 );
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acq_chan_array(c_ACQ_CORE_CC_P2P_ID, c_ACQ_DCC_ID).trig <= trig_pulse_rcv(c_TRIG_MUX_CC_P2P_ID, c_ACQ_DCC_ID).pulse;
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+ -- ------------------
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+ -- ACQ Core 4
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+ -- ------------------
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+
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+ -- SYS ID
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+ acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_ID).val(to_integer (c_FACQ_CHANNELS(c_ACQ_SYS_ID_ID).width )- 1 downto 0 ) <=
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+ std_logic_vector (bpm_pos_flat_x(7 )) & std_logic_vector (bpm_pos_flat_x(6 )) & std_logic_vector (bpm_pos_flat_x(5 )) & std_logic_vector (bpm_pos_flat_x(4 )) & -- BPM x positions (767 downto 512, 8x32)
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+ std_logic_vector (bpm_pos_flat_x(3 )) & std_logic_vector (bpm_pos_flat_x(2 )) & std_logic_vector (bpm_pos_flat_x(1 )) & std_logic_vector (bpm_pos_flat_x(0 )) &
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+ std_logic_vector (bpm_pos_flat_y(7 )) & std_logic_vector (bpm_pos_flat_y(6 )) & std_logic_vector (bpm_pos_flat_y(5 )) & std_logic_vector (bpm_pos_flat_y(4 )) & -- BPM y positions (511 downto 256, 8x32)
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+ std_logic_vector (bpm_pos_flat_y(3 )) & std_logic_vector (bpm_pos_flat_y(2 )) & std_logic_vector (bpm_pos_flat_y(1 )) & std_logic_vector (bpm_pos_flat_y(0 )) &
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+ -- TODO: These bits should be filled with channels 11-8, but they aren't instantiated yet
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+ std_logic_vector (to_unsigned (0 , 64 )) & -- FOFB setpoints (255 downto 64, 12x16)
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+ std_logic_vector (fofb_sp_arr(7 )) & std_logic_vector (fofb_sp_arr(6 )) & std_logic_vector (fofb_sp_arr(5 )) & std_logic_vector (fofb_sp_arr(4 )) &
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+ std_logic_vector (fofb_sp_arr(3 )) & std_logic_vector (fofb_sp_arr(2 )) & std_logic_vector (fofb_sp_arr(1 )) & std_logic_vector (fofb_sp_arr(0 )) &
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+ bpm_pos_flat_x_rcvd & bpm_pos_flat_y_rcvd & -- [DEBUG] Flatenizers' 'received' flag (64 downto 49, 2x8)
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+ f_fofb_cc_packet_to_slv(acq_dcc_fmc_packet)(def_PacketTimeframeCntr16MSB downto def_PacketTimeframeCntr16LSB) & -- [DEBUG] Timeframe counter (49 downto 33, 1x16)
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+ std_logic_vector (to_unsigned (0 , 32 ));
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+ acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_ID).dvalid <= or fofb_sp_valid_arr;
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+ acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_ID).trig <= trig_pulse_rcv(c_TRIG_MUX_SYS_ID_ID, c_ACQ_SYS_ID_ID).pulse;
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+
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-- --------------------------------------------------------------------
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-- Trigger --
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-- --------------------------------------------------------------------
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