diff --git a/hdl/ip_cores/dsp-cores b/hdl/ip_cores/dsp-cores index 5be219c3..4b49382b 160000 --- a/hdl/ip_cores/dsp-cores +++ b/hdl/ip_cores/dsp-cores @@ -1 +1 @@ -Subproject commit 5be219c3081a2318f11debd84e77be8c893b9cbe +Subproject commit 4b49382baaf52ce062a87a214dbcfd20e9361a06 diff --git a/hdl/ip_cores/general-cores b/hdl/ip_cores/general-cores index 4dc79c87..20ade77c 160000 --- a/hdl/ip_cores/general-cores +++ b/hdl/ip_cores/general-cores @@ -1 +1 @@ -Subproject commit 4dc79c876bd41cd150eecef7f331ddd889275a90 +Subproject commit 20ade77c41bcb981276a3980858fc5574f12460f diff --git a/hdl/modules/bpm_cores_pkg.vhd b/hdl/modules/bpm_cores_pkg.vhd index e51c9faa..3671f89b 100644 --- a/hdl/modules/bpm_cores_pkg.vhd +++ b/hdl/modules/bpm_cores_pkg.vhd @@ -228,7 +228,8 @@ package bpm_cores_pkg is g_fofb_cordic_stages : positive := 15; g_fofb_cordic_iter_per_clk : positive := 3; g_fofb_cordic_ratio : positive := 4; - g_k_width : natural := 24; + g_k_width : natural := 25; + g_offset_width : natural := 32; g_IQ_width : natural := 32); port ( adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0); @@ -243,6 +244,8 @@ package bpm_cores_pkg is ksum_i : in std_logic_vector(g_k_width-1 downto 0); kx_i : in std_logic_vector(g_k_width-1 downto 0); ky_i : in std_logic_vector(g_k_width-1 downto 0); + offset_x_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0'); + offset_y_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0'); mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0); mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0); mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0); @@ -642,7 +645,10 @@ package bpm_cores_pkg is g_fofb_cordic_ratio : positive := 4; -- width of K constants - g_k_width : natural := 24; + g_k_width : natural := 25; + + -- width of offset constants + g_offset_width : natural := 32; --width for IQ output g_IQ_width : natural := 32; @@ -884,7 +890,10 @@ package bpm_cores_pkg is g_monit_decim_width : natural := 32; -- width of K constants - g_k_width : natural := 24; + g_k_width : natural := 25; + + -- width of offset constants + g_offset_width : natural := 32; --width for IQ output g_IQ_width : natural := 32; @@ -1143,15 +1152,30 @@ package bpm_cores_pkg is intlk_trans_bigger_x_o : out std_logic; intlk_trans_bigger_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted intlk_trans_bigger_ltc_x_o : out std_logic; intlk_trans_bigger_ltc_y_o : out std_logic; + intlk_trans_bigger_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_bigger_ltc_o : out std_logic; + -- conditional to intlk_trans_en_i intlk_trans_bigger_o : out std_logic; + intlk_trans_smaller_x_o : out std_logic; + intlk_trans_smaller_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted - intlk_trans_ltc_o : out std_logic; + intlk_trans_smaller_ltc_x_o : out std_logic; + intlk_trans_smaller_ltc_y_o : out std_logic; + + intlk_trans_smaller_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_smaller_ltc_o : out std_logic; -- conditional to intlk_trans_en_i - intlk_trans_o : out std_logic; + intlk_trans_smaller_o : out std_logic; intlk_ang_bigger_x_o : out std_logic; intlk_ang_bigger_y_o : out std_logic; @@ -1159,12 +1183,25 @@ package bpm_cores_pkg is intlk_ang_bigger_ltc_x_o : out std_logic; intlk_ang_bigger_ltc_y_o : out std_logic; + intlk_ang_bigger_any_o : out std_logic; + + -- only cleared when intlk_ang_clr_i is asserted + intlk_ang_bigger_ltc_o : out std_logic; + -- conditional to intlk_ang_en_i intlk_ang_bigger_o : out std_logic; + intlk_ang_smaller_x_o : out std_logic; + intlk_ang_smaller_y_o : out std_logic; + + intlk_ang_smaller_ltc_x_o : out std_logic; + intlk_ang_smaller_ltc_y_o : out std_logic; + + intlk_ang_smaller_any_o : out std_logic; + -- only cleared when intlk_ang_clr_i is asserted - intlk_ang_ltc_o : out std_logic; + intlk_ang_smaller_ltc_o : out std_logic; -- conditional to intlk_ang_en_i - intlk_ang_o : out std_logic; + intlk_ang_smaller_o : out std_logic; -- only cleared when intlk_clr_i is asserted intlk_ltc_o : out std_logic; @@ -1246,15 +1283,30 @@ package bpm_cores_pkg is intlk_trans_bigger_x_o : out std_logic; intlk_trans_bigger_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted intlk_trans_bigger_ltc_x_o : out std_logic; intlk_trans_bigger_ltc_y_o : out std_logic; + intlk_trans_bigger_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_bigger_ltc_o : out std_logic; + -- conditional to intlk_trans_en_i intlk_trans_bigger_o : out std_logic; + intlk_trans_smaller_x_o : out std_logic; + intlk_trans_smaller_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted - intlk_trans_ltc_o : out std_logic; + intlk_trans_smaller_ltc_x_o : out std_logic; + intlk_trans_smaller_ltc_y_o : out std_logic; + + intlk_trans_smaller_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_smaller_ltc_o : out std_logic; -- conditional to intlk_trans_en_i - intlk_trans_o : out std_logic; + intlk_trans_smaller_o : out std_logic; intlk_ang_bigger_x_o : out std_logic; intlk_ang_bigger_y_o : out std_logic; @@ -1262,12 +1314,25 @@ package bpm_cores_pkg is intlk_ang_bigger_ltc_x_o : out std_logic; intlk_ang_bigger_ltc_y_o : out std_logic; + intlk_ang_bigger_any_o : out std_logic; + + -- only cleared when intlk_ang_clr_i is asserted + intlk_ang_bigger_ltc_o : out std_logic; + -- conditional to intlk_ang_en_i intlk_ang_bigger_o : out std_logic; + intlk_ang_smaller_x_o : out std_logic; + intlk_ang_smaller_y_o : out std_logic; + + intlk_ang_smaller_ltc_x_o : out std_logic; + intlk_ang_smaller_ltc_y_o : out std_logic; + + intlk_ang_smaller_any_o : out std_logic; + -- only cleared when intlk_ang_clr_i is asserted - intlk_ang_ltc_o : out std_logic; + intlk_ang_smaller_ltc_o : out std_logic; -- conditional to intlk_ang_en_i - intlk_ang_o : out std_logic; + intlk_ang_smaller_o : out std_logic; -- only cleared when intlk_clr_i is asserted intlk_ltc_o : out std_logic; diff --git a/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd b/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd index 7666caae..7faf7179 100644 --- a/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd +++ b/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd @@ -96,7 +96,8 @@ package machine_pkg is -- them, so we gain in latency. constant c_pos_calc_fofb_cordic_ratio : positive := 1; - constant c_pos_calc_k_width : natural := 24; + constant c_pos_calc_k_width : natural := 25; + constant c_pos_calc_offset_width : natural := 32; constant c_pos_calc_IQ_width : natural := c_pos_calc_mixed_width; constant c_pos_calc_k_sum : natural := 85e5; diff --git a/hdl/modules/machine/sirius_bo_250M/machine_pkg.vhd b/hdl/modules/machine/sirius_bo_250M/machine_pkg.vhd index d8d6d77c..dc391027 100644 --- a/hdl/modules/machine/sirius_bo_250M/machine_pkg.vhd +++ b/hdl/modules/machine/sirius_bo_250M/machine_pkg.vhd @@ -86,7 +86,8 @@ package machine_pkg is constant c_pos_calc_fofb_cordic_iter_per_clk : positive := 3; constant c_pos_calc_fofb_cordic_ratio : positive := 8; - constant c_pos_calc_k_width : natural := 24; + constant c_pos_calc_k_width : natural := 25; + constant c_pos_calc_offset_width : natural := 32; constant c_pos_calc_IQ_width : natural := c_pos_calc_mixed_width; constant c_pos_calc_k_sum : natural := 85e5; diff --git a/hdl/modules/machine/sirius_sr_130M/machine_pkg.vhd b/hdl/modules/machine/sirius_sr_130M/machine_pkg.vhd index 79fb96c7..c29cce8a 100644 --- a/hdl/modules/machine/sirius_sr_130M/machine_pkg.vhd +++ b/hdl/modules/machine/sirius_sr_130M/machine_pkg.vhd @@ -69,7 +69,8 @@ package machine_pkg is constant c_pos_calc_fofb_cordic_iter_per_clk : positive := 3; constant c_pos_calc_fofb_cordic_ratio : positive := 4; - constant c_pos_calc_k_width : natural := 24; + constant c_pos_calc_k_width : natural := 25; + constant c_pos_calc_offset_width : natural := 32; constant c_pos_calc_IQ_width : natural := c_pos_calc_mixed_width; constant c_pos_calc_k_sum : natural := 85e5; diff --git a/hdl/modules/machine/sirius_sr_250M/machine_pkg.vhd b/hdl/modules/machine/sirius_sr_250M/machine_pkg.vhd index 3b22df3c..e472365a 100644 --- a/hdl/modules/machine/sirius_sr_250M/machine_pkg.vhd +++ b/hdl/modules/machine/sirius_sr_250M/machine_pkg.vhd @@ -86,7 +86,8 @@ package machine_pkg is constant c_pos_calc_fofb_cordic_iter_per_clk : positive := 3; constant c_pos_calc_fofb_cordic_ratio : positive := 8; - constant c_pos_calc_k_width : natural := 24; + constant c_pos_calc_k_width : natural := 25; + constant c_pos_calc_offset_width : natural := 32; constant c_pos_calc_IQ_width : natural := c_pos_calc_mixed_width; constant c_pos_calc_k_sum : natural := 85e5; diff --git a/hdl/modules/position_calc/position_calc.vhd b/hdl/modules/position_calc/position_calc.vhd index 0f65ffb8..3100716f 100644 --- a/hdl/modules/position_calc/position_calc.vhd +++ b/hdl/modules/position_calc/position_calc.vhd @@ -99,7 +99,10 @@ entity position_calc is g_fofb_cordic_ratio : positive := 4; -- width of K constants - g_k_width : natural := 24; + g_k_width : natural := 25; + + -- width of offset constants + g_offset_width : natural := 32; --width for IQ output g_IQ_width : natural := 32 @@ -121,6 +124,9 @@ entity position_calc is kx_i : in std_logic_vector(g_k_width-1 downto 0); ky_i : in std_logic_vector(g_k_width-1 downto 0); + offset_x_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0'); + offset_y_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0'); + mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0); mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0); mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0); @@ -388,6 +394,9 @@ architecture rtl of position_calc is signal fofb_x_pre, fofb_y_pre, fofb_q_pre, fofb_sum_pre : std_logic_vector(g_fofb_decim_width-1 downto 0) := (others => '0'); + signal fofb_pos_x_int, fofb_pos_y_int, fofb_pos_q_int, fofb_pos_sum_int : + std_logic_vector(g_fofb_decim_width-1 downto 0) := (others => '0'); + signal tbt_x_pre, tbt_y_pre, tbt_q_pre, tbt_sum_pre : std_logic_vector(g_tbt_decim_width-1 downto 0) := (others => '0'); @@ -782,10 +791,16 @@ begin end generate gen_ddc; + -- x, y, and q are fixed point with: + -- sign bit = MSB + -- word length = g_width + -- integer length = g_k_width + 1 + -- fractional length = g_width - (integer length) cmp_fofb_ds : delta_sigma generic map ( g_width => g_fofb_decim_width, - g_k_width => g_k_width) + g_k_width => g_k_width, + g_offset_width => g_offset_width) port map ( a_i => fofb_mag(0), b_i => fofb_mag(1), @@ -794,15 +809,17 @@ begin kx_i => kx_i, ky_i => ky_i, ksum_i => ksum_i, + offset_x_i => offset_x_i, + offset_y_i => offset_y_i, clk_i => clk_i, ce_i => ce_fofb_cordic(0), valid_i => valid_fofb_cordic(0), valid_o => valid_fofb_ds, rst_i => rst_i, - x_o => fofb_pos_x_o, - y_o => fofb_pos_y_o, - q_o => fofb_pos_q_o, - sum_o => fofb_pos_sum_o); + x_o => fofb_pos_x_int, + y_o => fofb_pos_y_int, + q_o => fofb_pos_q_int, + sum_o => fofb_pos_sum_int); -- desync counters. Use only one of the channels as a sample tbt_tag_desync_cnt_o <= tbt_tag_desync_cnt(0); @@ -890,10 +907,15 @@ begin fofb_pos_valid_o <= valid_fofb_ds; fofb_pos_ce_o <= ce_fofb_cordic(0); + fofb_pos_x_o <= std_logic_vector(shift_right(signed(fofb_pos_x_int), g_fofb_decim_width-g_k_width)); + fofb_pos_y_o <= std_logic_vector(shift_right(signed(fofb_pos_y_int), g_fofb_decim_width-g_k_width)); + fofb_pos_q_o <= std_logic_vector(shift_right(signed(fofb_pos_q_int), g_fofb_decim_width-g_k_width)); + fofb_pos_sum_o <= fofb_pos_sum_int; + + -- Removed to speed synthesis during test tbt_pos_valid_o <= '0'; tbt_pos_ce_o <= '0'; - -- Removed to speed synthesis during test tbt_pos_x_o <= (others => '0'); tbt_pos_y_o <= (others => '0'); tbt_pos_q_o <= (others => '0'); diff --git a/hdl/modules/wb_orbit_intlk/orbit_intlk.vhd b/hdl/modules/wb_orbit_intlk/orbit_intlk.vhd index c5cf6a66..c1ffde2d 100644 --- a/hdl/modules/wb_orbit_intlk/orbit_intlk.vhd +++ b/hdl/modules/wb_orbit_intlk/orbit_intlk.vhd @@ -59,12 +59,16 @@ port intlk_trans_clr_i : in std_logic; intlk_trans_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); intlk_trans_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_trans_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_trans_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); -- Angular interlock on/off intlk_ang_en_i : in std_logic; -- Angular interlock clear intlk_ang_clr_i : in std_logic; intlk_ang_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); intlk_ang_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_ang_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_ang_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); ----------------------------- -- Downstream ADC and position signals @@ -110,14 +114,34 @@ port intlk_trans_bigger_x_o : out std_logic; intlk_trans_bigger_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted intlk_trans_bigger_ltc_x_o : out std_logic; intlk_trans_bigger_ltc_y_o : out std_logic; + intlk_trans_bigger_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_bigger_ltc_o : out std_logic; + -- conditional to intlk_trans_en_i intlk_trans_bigger_o : out std_logic; + intlk_trans_smaller_x_o : out std_logic; + intlk_trans_smaller_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted - intlk_trans_ltc_o : out std_logic; + intlk_trans_smaller_ltc_x_o : out std_logic; + intlk_trans_smaller_ltc_y_o : out std_logic; + + intlk_trans_smaller_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_smaller_ltc_o : out std_logic; -- conditional to intlk_trans_en_i + intlk_trans_smaller_o : out std_logic; + + -- only cleared when intlk_clr_i is asserted + intlk_trans_ltc_o : out std_logic; + -- conditional to intlk_en_i intlk_trans_o : out std_logic; intlk_ang_bigger_x_o : out std_logic; @@ -126,11 +150,29 @@ port intlk_ang_bigger_ltc_x_o : out std_logic; intlk_ang_bigger_ltc_y_o : out std_logic; + intlk_ang_bigger_any_o : out std_logic; + + -- only cleared when intlk_ang_clr_i is asserted + intlk_ang_bigger_ltc_o : out std_logic; + -- conditional to intlk_ang_en_i intlk_ang_bigger_o : out std_logic; + intlk_ang_smaller_x_o : out std_logic; + intlk_ang_smaller_y_o : out std_logic; + + intlk_ang_smaller_ltc_x_o : out std_logic; + intlk_ang_smaller_ltc_y_o : out std_logic; + + intlk_ang_smaller_any_o : out std_logic; + -- only cleared when intlk_ang_clr_i is asserted - intlk_ang_ltc_o : out std_logic; + intlk_ang_smaller_ltc_o : out std_logic; -- conditional to intlk_ang_en_i + intlk_ang_smaller_o : out std_logic; + + -- only cleared when intlk_clr_i is asserted + intlk_ang_ltc_o : out std_logic; + -- conditional to intlk_en_i intlk_ang_o : out std_logic; -- only cleared when intlk_clr_i is asserted @@ -157,10 +199,19 @@ architecture rtl of orbit_intlk is signal decim_pos_sum_array : t_decim_data_array(c_NUM_BPMS-1 downto 0); signal decim_pos_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0); - signal intlk_trans_ltc : std_logic; - signal intlk_trans : std_logic; - signal intlk_ang_ltc : std_logic; - signal intlk_ang : std_logic; + signal intlk_trans_bigger_ltc : std_logic; + signal intlk_trans_bigger : std_logic; + signal intlk_trans_smaller_ltc : std_logic; + signal intlk_trans_smaller : std_logic; + signal intlk_trans_ltc : std_logic; + signal intlk_trans : std_logic; + + signal intlk_ang_bigger_ltc : std_logic; + signal intlk_ang_bigger : std_logic; + signal intlk_ang_smaller_ltc : std_logic; + signal intlk_ang_smaller : std_logic; + signal intlk_ang_ltc : std_logic; + signal intlk_ang : std_logic; signal intlk_all : std_logic; signal intlk_ltc : std_logic; @@ -172,7 +223,6 @@ architecture rtl of orbit_intlk is signal intlk_sum_bigger : t_bit_array(c_NUM_BPMS-1 downto 0); signal intlk_sum_bigger_valid : t_bit_array(c_NUM_BPMS-1 downto 0); signal intlk_sum_bigger_reg : t_bit_array(c_NUM_BPMS-1 downto 0); - signal intlk_sum_bigger_valid_reg : t_bit_array(c_NUM_BPMS-1 downto 0); signal intlk_sum_bigger_or : t_bit_array(c_NUM_BPMS downto 0); signal intlk_sum_bigger_any : std_logic; signal intlk_sum_bigger_en : std_logic; @@ -336,8 +386,11 @@ begin p_sum_thold_bigger_reg : process(ref_clk_i) begin if rising_edge(ref_clk_i) then - intlk_sum_bigger_reg(i) <= intlk_sum_bigger(i); - intlk_sum_bigger_valid_reg(i) <= intlk_sum_bigger_valid(i); + if ref_rst_n_i = '0' then + intlk_sum_bigger_reg(i) <= '0'; + elsif intlk_sum_bigger_valid(i) = '1' then + intlk_sum_bigger_reg(i) <= intlk_sum_bigger(i); + end if; end if; end process; @@ -346,8 +399,7 @@ begin intlk_sum_bigger_or(0) <= '0'; -- ORing all trans_bigger gen_intlk_sum_bigger : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate - intlk_sum_bigger_or(i+1) <= intlk_sum_bigger_or(i) or (intlk_sum_bigger_reg(i) and - intlk_sum_bigger_valid_reg(i)); + intlk_sum_bigger_or(i+1) <= intlk_sum_bigger_or(i) or intlk_sum_bigger_reg(i); end generate; p_reg_enable : process(ref_clk_i) @@ -397,6 +449,8 @@ begin intlk_trans_clr_i => intlk_trans_clr_i, intlk_trans_max_x_i => intlk_trans_max_x_i, intlk_trans_max_y_i => intlk_trans_max_y_i, + intlk_trans_min_x_i => intlk_trans_min_x_i, + intlk_trans_min_y_i => intlk_trans_min_y_i, ----------------------------- -- Downstream ADC and position signals @@ -441,15 +495,36 @@ begin intlk_trans_bigger_ltc_x_o => intlk_trans_bigger_ltc_x_o, intlk_trans_bigger_ltc_y_o => intlk_trans_bigger_ltc_y_o, - intlk_trans_bigger_o => intlk_trans_bigger_o, + intlk_trans_bigger_any_o => intlk_trans_bigger_any_o, + + intlk_trans_bigger_ltc_o => intlk_trans_bigger_ltc, + intlk_trans_bigger_o => intlk_trans_bigger, + + intlk_trans_smaller_x_o => intlk_trans_smaller_x_o, + intlk_trans_smaller_y_o => intlk_trans_smaller_y_o, + + intlk_trans_smaller_ltc_x_o => intlk_trans_smaller_ltc_x_o, + intlk_trans_smaller_ltc_y_o => intlk_trans_smaller_ltc_y_o, + + intlk_trans_smaller_any_o => intlk_trans_smaller_any_o, - intlk_trans_ltc_o => intlk_trans_ltc, - intlk_trans_o => intlk_trans + intlk_trans_smaller_ltc_o => intlk_trans_smaller_ltc, + intlk_trans_smaller_o => intlk_trans_smaller ); + intlk_trans_ltc <= intlk_trans_bigger_ltc or intlk_trans_smaller_ltc; + intlk_trans <= intlk_trans_bigger or intlk_trans_smaller; + + -- Outputs + intlk_trans_ltc_o <= intlk_trans_ltc; intlk_trans_o <= intlk_trans; + intlk_trans_bigger_ltc_o <= intlk_trans_bigger_ltc; + intlk_trans_bigger_o <= intlk_trans_bigger; + intlk_trans_smaller_ltc_o <= intlk_trans_smaller_ltc; + intlk_trans_smaller_o <= intlk_trans_smaller; + ----------------------------- -- Angular interlock ----------------------------- @@ -480,6 +555,8 @@ begin intlk_ang_clr_i => intlk_ang_clr_i, intlk_ang_max_x_i => intlk_ang_max_x_i, intlk_ang_max_y_i => intlk_ang_max_y_i, + intlk_ang_min_x_i => intlk_ang_min_x_i, + intlk_ang_min_y_i => intlk_ang_min_y_i, ----------------------------- -- Downstream ADC and position signals @@ -524,15 +601,36 @@ begin intlk_ang_bigger_ltc_x_o => intlk_ang_bigger_ltc_x_o, intlk_ang_bigger_ltc_y_o => intlk_ang_bigger_ltc_y_o, - intlk_ang_bigger_o => intlk_ang_bigger_o, + intlk_ang_bigger_any_o => intlk_ang_bigger_any_o, + + intlk_ang_bigger_ltc_o => intlk_ang_bigger_ltc, + intlk_ang_bigger_o => intlk_ang_bigger, + + intlk_ang_smaller_x_o => intlk_ang_smaller_x_o, + intlk_ang_smaller_y_o => intlk_ang_smaller_y_o, - intlk_ang_ltc_o => intlk_ang_ltc, - intlk_ang_o => intlk_ang + intlk_ang_smaller_ltc_x_o => intlk_ang_smaller_ltc_x_o, + intlk_ang_smaller_ltc_y_o => intlk_ang_smaller_ltc_y_o, + + intlk_ang_smaller_any_o => intlk_ang_smaller_any_o, + + intlk_ang_smaller_ltc_o => intlk_ang_smaller_ltc, + intlk_ang_smaller_o => intlk_ang_smaller ); + intlk_ang_ltc <= intlk_ang_bigger_ltc or intlk_ang_smaller_ltc; + intlk_ang <= intlk_ang_bigger or intlk_ang_smaller; + + -- Outputs + intlk_ang_ltc_o <= intlk_ang_ltc; intlk_ang_o <= intlk_ang; + intlk_ang_bigger_ltc_o <= intlk_ang_bigger_ltc; + intlk_ang_bigger_o <= intlk_ang_bigger; + intlk_ang_smaller_ltc_o <= intlk_ang_smaller_ltc; + intlk_ang_smaller_o <= intlk_ang_smaller; + ------------------------------------------------------------------------- -- General interlock detector. Only for X and Y. ------------------------------------------------------------------------- @@ -558,7 +656,7 @@ begin if intlk_clr_i = '1' or intlk_en_i = '0' then intlk <= '0'; elsif intlk_en_i = '1' then - intlk <= intlk_ltc; + intlk <= intlk_all; end if; end if; end if; diff --git a/hdl/modules/wb_orbit_intlk/orbit_intlk_ang.vhd b/hdl/modules/wb_orbit_intlk/orbit_intlk_ang.vhd index 69c75a92..fe695311 100644 --- a/hdl/modules/wb_orbit_intlk/orbit_intlk_ang.vhd +++ b/hdl/modules/wb_orbit_intlk/orbit_intlk_ang.vhd @@ -53,6 +53,8 @@ port intlk_ang_clr_i : in std_logic; intlk_ang_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); intlk_ang_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_ang_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_ang_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); ----------------------------- -- Downstream ADC and position signals @@ -97,12 +99,25 @@ port intlk_ang_bigger_ltc_x_o : out std_logic; intlk_ang_bigger_ltc_y_o : out std_logic; + intlk_ang_bigger_any_o : out std_logic; + + -- only cleared when intlk_ang_clr_i is asserted + intlk_ang_bigger_ltc_o : out std_logic; + -- conditional to intlk_ang_en_i intlk_ang_bigger_o : out std_logic; + intlk_ang_smaller_x_o : out std_logic; + intlk_ang_smaller_y_o : out std_logic; + + intlk_ang_smaller_ltc_x_o : out std_logic; + intlk_ang_smaller_ltc_y_o : out std_logic; + + intlk_ang_smaller_any_o : out std_logic; + -- only cleared when intlk_ang_clr_i is asserted - intlk_ang_ltc_o : out std_logic; + intlk_ang_smaller_ltc_o : out std_logic; -- conditional to intlk_ang_en_i - intlk_ang_o : out std_logic + intlk_ang_smaller_o : out std_logic ); end orbit_intlk_ang; @@ -142,8 +157,11 @@ architecture rtl of orbit_intlk_ang is signal decim_pos_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0); -- interlock limits - signal intlk_ang_max : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0); - signal intlk_ang_max_n : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0); + signal intlk_ang_max : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0); + signal intlk_ang_max_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal intlk_ang_max_n : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0); + signal intlk_ang_min : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0); + signal intlk_ang_min_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0); -- valid AND signal adc_valid_and : t_bit_array(c_NUM_BPMS downto 0); @@ -157,21 +175,40 @@ architecture rtl of orbit_intlk_ang is signal ang_sum_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal ang_sum_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal ang : t_decim_data_array(c_NUM_CHANNELS-1 downto 0); - signal ang_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal ang_n : t_decim_data_array(c_NUM_CHANNELS-1 downto 0); + signal ang_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal ang_bigger : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_bigger_comb : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal ang_bigger_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal ang_bigger_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal ang_bigger_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0); - signal ang_intlk_ltc_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); - signal ang_intlk_bigger_or : t_bit_array(c_NUM_CHANNELS downto 0); - signal ang_intlk_bigger : std_logic; - signal ang_intlk_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); - signal ang_intlk_ltc : std_logic; - signal ang_intlk_any : std_logic; - signal ang_intlk : std_logic; + signal ang_smaller : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_smaller_comb : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_smaller_n : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_smaller_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_smaller_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_smaller_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0); + + signal ang_intlk_det_bigger_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_intlk_bigger_ltc_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_intlk_bigger_or : t_bit_array(c_NUM_CHANNELS downto 0); + signal ang_intlk_bigger_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_intlk_bigger_ltc_or : t_bit_array(c_NUM_CHANNELS downto 0); + signal ang_intlk_bigger_ltc : std_logic; + signal ang_intlk_bigger_any : std_logic; + signal ang_intlk_bigger : std_logic; + + signal ang_intlk_det_smaller_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_intlk_smaller_ltc_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_intlk_smaller_or : t_bit_array(c_NUM_CHANNELS downto 0); + signal ang_intlk_smaller_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal ang_intlk_smaller_ltc_or : t_bit_array(c_NUM_CHANNELS downto 0); + signal ang_intlk_smaller_ltc : std_logic; + signal ang_intlk_smaller_any : std_logic; + signal ang_intlk_smaller : std_logic; begin @@ -220,9 +257,11 @@ begin -- Interlock limits -- X limits intlk_ang_max(0) <= intlk_ang_max_x_i; + intlk_ang_min(0) <= intlk_ang_min_x_i; -- Y limits intlk_ang_max(1) <= intlk_ang_max_y_i; + intlk_ang_min(1) <= intlk_ang_min_y_i; ---------------------------------- -- Calculate angular @@ -247,11 +286,11 @@ begin ------------------------------------------------------------------------- -- Angular interlock detector. Only for X and Y. -- Calculation is a simple (us = upstream, ds = downstream): - -- x_ang = abs(x_us - x_ds) / distance_between_bpms OR - -- x_ang * distance_between_bpms = abs(x_us - x_ds) + -- x_ang = x_us - x_ds / distance_between_bpms OR + -- x_ang * distance_between_bpms = x_us - x_ds -- - -- y_ang = abs(y_us - y_ds) / distance_between_bpms OR - -- y_ang * distance_between_bpms = abs(y_us - y_ds) + -- y_ang = y_us - y_ds / distance_between_bpms OR + -- y_ang * distance_between_bpms = y_us - y_ds ------------------------------------------------------------------------- gen_ang_intlk : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate @@ -275,32 +314,28 @@ begin -- gc_big_adder2 outputs are unregistered. So register them. p_ang_reg : process(fs_clk_i) - begin - if rising_edge(fs_clk_i) then - ang_sum_reg(i) <= ang_sum(i); - ang_sum_valid_reg(i) <= ang_sum_valid(i); - end if; - end process; - - -- Absolute sum value - p_ang_divide : process(fs_clk_i) begin if rising_edge(fs_clk_i) then if fs_rst_n_i = '0' then - ang(i) <= (others => '0'); - ang_valid(i) <= '0'; + ang_sum_valid_reg(i) <= '0'; else - ang(i) <= std_logic_vector(abs(signed(ang_sum_reg(i)))); - ang_valid(i) <= ang_sum_valid_reg(i); + if ang_sum_valid(i) = '1' then + ang_sum_reg(i) <= ang_sum(i); + end if; + + ang_sum_valid_reg(i) <= ang_sum_valid(i); end if; end if; end process; + ang(i) <= ang_sum_reg(i); + ang_valid(i) <= ang_sum_valid_reg(i); + ---------------------------------- - -- Detect position >= Threshold + -- Detect position > Threshold ---------------------------------- -- Compare with threshold. Use the simple identity that: - -- A >= B is the same as A + (-B) and we check if MSB Carry + -- A > B is the same as A + (-B) and we check if MSB Carry -- is 1 cmp_ang_thold_bigger : gc_big_adder2 generic map ( @@ -313,43 +348,126 @@ begin a_i => ang(i), b_i => intlk_ang_max_n(i), c_i => '1', - c2_o => ang_bigger(i), + c2_o => ang_bigger_comb(i), c2x2_valid_o => ang_bigger_valid(i) ); intlk_ang_max_n(i) <= not intlk_ang_max(i); + -- comparison of different sign operands fails with the above method. + -- Just compare the sign bits, for these cases. + ang_high_bit(i) <= ang(i)(ang(i)'high); + intlk_ang_max_high_bit(i) <= intlk_ang_max(i)(intlk_ang_max(i)'high); + + ang_bigger(i) <= ang_bigger_comb(i) when + (ang_high_bit(i) xnor intlk_ang_max_high_bit(i)) = '1' else + intlk_ang_max_high_bit(i); + -- gc_big_adder2 outputs are unregistered. So register them. p_ang_thold_bigger_reg : process(fs_clk_i) begin if rising_edge(fs_clk_i) then - ang_bigger_reg(i) <= ang_bigger(i); - ang_bigger_valid_reg(i) <= ang_bigger_valid(i); + if fs_rst_n_i = '0' then + ang_bigger_valid_reg(i) <= '0'; + else + if ang_bigger_valid(i) = '1' then + ang_bigger_reg(i) <= ang_bigger(i); + end if; + + ang_bigger_valid_reg(i) <= ang_bigger_valid(i); + end if; + end if; + end process; + + ---------------------------------- + -- Detect position < Threshold + ---------------------------------- + -- Compare with threshold. Use the simple identity that: + -- A < B is the same as -A > -B = -A + B > 0 and we check + -- if MSB Carry is 1 + cmp_ang_thold_smaller : gc_big_adder2 + generic map ( + g_data_bits => c_DECIM_WIDTH + ) + port map ( + clk_i => fs_clk_i, + stall_i => '0', + valid_i => ang_valid(i), + a_i => ang_n(i), + b_i => intlk_ang_min(i), + c_i => '1', + c2_o => ang_smaller_comb(i), + c2x2_valid_o => ang_smaller_valid(i) + ); + + ang_n(i) <= not ang(i); + + -- comparison of different sign operands fails with the above method. + -- Just compare the sign bits, for these cases. + intlk_ang_min_high_bit(i) <= intlk_ang_min(i)(intlk_ang_min(i)'high); + + ang_smaller(i) <= ang_smaller_comb(i) when + (ang_high_bit(i) xnor intlk_ang_min_high_bit(i)) = '1' else + ang_high_bit(i); + + -- gc_big_adder2 outputs are unregistered. So register them. + p_ang_thold_smaller_reg : process(fs_clk_i) + begin + if rising_edge(fs_clk_i) then + if fs_rst_n_i = '0' then + ang_smaller_valid_reg(i) <= '0'; + else + if ang_smaller_valid(i) = '1' then + ang_smaller_reg(i) <= ang_smaller(i); + end if; + + ang_smaller_valid_reg(i) <= ang_smaller_valid(i); + end if; end if; end process; + ---------------------------------- + -- Latch interlocks + ---------------------------------- + + ang_intlk_det_bigger_all(i) <= ang_bigger_reg(i) and ang_bigger_valid_reg(i); + ang_intlk_det_smaller_all(i) <= ang_smaller_reg(i) and ang_smaller_valid_reg(i); + -- latch all interlocks p_latch : process(fs_clk_i) begin if rising_edge(fs_clk_i) then if fs_rst_n_i = '0' then - ang_intlk_ltc_all(i) <= '0'; + ang_intlk_bigger_ltc_all(i) <= '0'; + ang_intlk_smaller_ltc_all(i) <= '0'; else - -- latch up angle interlock status + -- latch up anglation interlock status -- only clear on "clear" signal if intlk_ang_clr_i = '1' then - ang_intlk_ltc_all(i) <= '0'; - elsif ang_bigger_reg(i) = '1' and - ang_bigger_valid_reg(i) = '1' and + ang_intlk_bigger_ltc_all(i) <= '0'; + elsif ang_intlk_det_bigger_all(i) = '1' and + intlk_ang_en_i = '1' then + ang_intlk_bigger_ltc_all(i) <= '1'; + end if; + + if intlk_ang_clr_i = '1' then + ang_intlk_smaller_ltc_all(i) <= '0'; + elsif ang_intlk_det_smaller_all(i) = '1' and intlk_ang_en_i = '1' then - ang_intlk_ltc_all(i) <= '1'; + ang_intlk_smaller_ltc_all(i) <= '1'; end if; -- register anglation interlock when active if intlk_ang_clr_i = '1' or intlk_ang_en_i = '0' then - ang_intlk_all(i) <= '0'; + ang_intlk_bigger_all(i) <= '0'; + else + ang_intlk_bigger_all(i) <= ang_intlk_det_bigger_all(i); + end if; + + if intlk_ang_clr_i = '1' or intlk_ang_en_i = '0' then + ang_intlk_smaller_all(i) <= '0'; else - ang_intlk_all(i) <= ang_intlk_ltc_all(i); + ang_intlk_smaller_all(i) <= ang_intlk_det_smaller_all(i); end if; end if; end if; @@ -357,56 +475,62 @@ begin end generate; - intlk_ang_bigger_ltc_x_o <= ang_intlk_ltc_all(c_CHAN_X_IDX); - intlk_ang_bigger_ltc_y_o <= ang_intlk_ltc_all(c_CHAN_Y_IDX); + intlk_ang_bigger_ltc_x_o <= ang_intlk_bigger_ltc_all(c_CHAN_X_IDX); + intlk_ang_bigger_ltc_y_o <= ang_intlk_bigger_ltc_all(c_CHAN_Y_IDX); - intlk_ang_bigger_x_o <= ang_intlk_all(c_CHAN_X_IDX); - intlk_ang_bigger_y_o <= ang_intlk_all(c_CHAN_Y_IDX); + intlk_ang_bigger_x_o <= ang_intlk_bigger_all(c_CHAN_X_IDX); + intlk_ang_bigger_y_o <= ang_intlk_bigger_all(c_CHAN_Y_IDX); + + intlk_ang_smaller_ltc_x_o <= ang_intlk_smaller_ltc_all(c_CHAN_X_IDX); + intlk_ang_smaller_ltc_y_o <= ang_intlk_smaller_ltc_all(c_CHAN_Y_IDX); + + intlk_ang_smaller_x_o <= ang_intlk_smaller_all(c_CHAN_X_IDX); + intlk_ang_smaller_y_o <= ang_intlk_smaller_all(c_CHAN_Y_IDX); ---------------------------------- -- Angular interlock merging ---------------------------------- + + ---------------------------------- + -- Bigger + ---------------------------------- ang_intlk_bigger_or(0) <= '0'; -- ORing all ang_bigger gen_ang_intlk_bigger : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate - ang_intlk_bigger_or(i+1) <= ang_intlk_bigger_or(i) or ang_intlk_all(i); + ang_intlk_bigger_or(i+1) <= ang_intlk_bigger_or(i) or ang_intlk_bigger_all(i); end generate; ang_intlk_bigger <= ang_intlk_bigger_or(c_INTLK_GEN_UPTO_CHANNEL+1); intlk_ang_bigger_o <= ang_intlk_bigger; + ang_intlk_bigger_ltc_or(0) <= '0'; + -- ORing all ang_bigger_ltc + gen_ang_intlk_bigger_ltc : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate + ang_intlk_bigger_ltc_or(i+1) <= ang_intlk_bigger_ltc_or(i) or ang_intlk_bigger_ltc_all(i); + end generate; + + ang_intlk_bigger_ltc <= ang_intlk_bigger_ltc_or(c_INTLK_GEN_UPTO_CHANNEL+1); + intlk_ang_bigger_ltc_o <= ang_intlk_bigger_ltc; + ---------------------------------- - -- Angular interlock status reg + -- Smaller ---------------------------------- + ang_intlk_smaller_or(0) <= '0'; + -- ORing all ang_smaller + gen_ang_intlk_smaller : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate + ang_intlk_smaller_or(i+1) <= ang_intlk_smaller_or(i) or ang_intlk_smaller_all(i); + end generate; - ang_intlk_any <= ang_intlk_bigger; - - p_ang_out : process(fs_clk_i) - begin - if rising_edge(fs_clk_i) then - if fs_rst_n_i = '0' then - ang_intlk_ltc <= '0'; - ang_intlk <= '0'; - else - -- latch up angular interlock status - -- only clear on "clear" signal - if intlk_ang_clr_i = '1' then - ang_intlk_ltc <= '0'; - elsif ang_intlk_any = '1' then - ang_intlk_ltc <= '1'; - end if; + ang_intlk_smaller <= ang_intlk_smaller_or(c_INTLK_GEN_UPTO_CHANNEL+1); + intlk_ang_smaller_o <= ang_intlk_smaller; - -- register angular interlock when active - if intlk_ang_clr_i = '1' or intlk_ang_en_i = '0' then - ang_intlk <= '0'; - else - ang_intlk <= ang_intlk_ltc; - end if; - end if; - end if; - end process; + ang_intlk_smaller_ltc_or(0) <= '0'; + -- ORing all ang_smaller_ltc + gen_ang_intlk_smaller_ltc : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate + ang_intlk_smaller_ltc_or(i+1) <= ang_intlk_smaller_ltc_or(i) or ang_intlk_smaller_ltc_all(i); + end generate; - intlk_ang_ltc_o <= ang_intlk_ltc; - intlk_ang_o <= ang_intlk; + ang_intlk_smaller_ltc <= ang_intlk_smaller_ltc_or(c_INTLK_GEN_UPTO_CHANNEL+1); + intlk_ang_smaller_ltc_o <= ang_intlk_smaller_ltc; end rtl; diff --git a/hdl/modules/wb_orbit_intlk/orbit_intlk_cdc_fifo.vhd b/hdl/modules/wb_orbit_intlk/orbit_intlk_cdc_fifo.vhd old mode 100755 new mode 100644 diff --git a/hdl/modules/wb_orbit_intlk/orbit_intlk_pkg.vhd b/hdl/modules/wb_orbit_intlk/orbit_intlk_pkg.vhd index c5a228c2..17d10f3d 100644 --- a/hdl/modules/wb_orbit_intlk/orbit_intlk_pkg.vhd +++ b/hdl/modules/wb_orbit_intlk/orbit_intlk_pkg.vhd @@ -69,12 +69,16 @@ package orbit_intlk_pkg is intlk_trans_clr_i : in std_logic; intlk_trans_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); intlk_trans_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_trans_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_trans_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); -- Angular interlock on/off intlk_ang_en_i : in std_logic; -- Angular interlock clear intlk_ang_clr_i : in std_logic; intlk_ang_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); intlk_ang_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_ang_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_ang_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); ----------------------------- -- Downstream ADC and position signals @@ -120,14 +124,34 @@ package orbit_intlk_pkg is intlk_trans_bigger_x_o : out std_logic; intlk_trans_bigger_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted intlk_trans_bigger_ltc_x_o : out std_logic; intlk_trans_bigger_ltc_y_o : out std_logic; + intlk_trans_bigger_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_bigger_ltc_o : out std_logic; + -- conditional to intlk_trans_en_i intlk_trans_bigger_o : out std_logic; + intlk_trans_smaller_x_o : out std_logic; + intlk_trans_smaller_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted - intlk_trans_ltc_o : out std_logic; + intlk_trans_smaller_ltc_x_o : out std_logic; + intlk_trans_smaller_ltc_y_o : out std_logic; + + intlk_trans_smaller_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_smaller_ltc_o : out std_logic; -- conditional to intlk_trans_en_i + intlk_trans_smaller_o : out std_logic; + + -- only cleared when intlk_clr_i is asserted + intlk_trans_ltc_o : out std_logic; + -- conditional to intlk_en_i intlk_trans_o : out std_logic; intlk_ang_bigger_x_o : out std_logic; @@ -136,11 +160,29 @@ package orbit_intlk_pkg is intlk_ang_bigger_ltc_x_o : out std_logic; intlk_ang_bigger_ltc_y_o : out std_logic; + intlk_ang_bigger_any_o : out std_logic; + + -- only cleared when intlk_ang_clr_i is asserted + intlk_ang_bigger_ltc_o : out std_logic; + -- conditional to intlk_ang_en_i intlk_ang_bigger_o : out std_logic; + intlk_ang_smaller_x_o : out std_logic; + intlk_ang_smaller_y_o : out std_logic; + + intlk_ang_smaller_ltc_x_o : out std_logic; + intlk_ang_smaller_ltc_y_o : out std_logic; + + intlk_ang_smaller_any_o : out std_logic; + -- only cleared when intlk_ang_clr_i is asserted - intlk_ang_ltc_o : out std_logic; + intlk_ang_smaller_ltc_o : out std_logic; -- conditional to intlk_ang_en_i + intlk_ang_smaller_o : out std_logic; + + -- only cleared when intlk_clr_i is asserted + intlk_ang_ltc_o : out std_logic; + -- conditional to intlk_en_i intlk_ang_o : out std_logic; -- only cleared when intlk_clr_i is asserted @@ -177,6 +219,8 @@ package orbit_intlk_pkg is intlk_trans_clr_i : in std_logic; intlk_trans_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); intlk_trans_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_trans_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_trans_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); ----------------------------- -- Downstream ADC and position signals @@ -221,12 +265,25 @@ package orbit_intlk_pkg is intlk_trans_bigger_ltc_x_o : out std_logic; intlk_trans_bigger_ltc_y_o : out std_logic; + intlk_trans_bigger_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_bigger_ltc_o : out std_logic; + -- conditional to intlk_trans_en_i intlk_trans_bigger_o : out std_logic; + intlk_trans_smaller_x_o : out std_logic; + intlk_trans_smaller_y_o : out std_logic; + + intlk_trans_smaller_ltc_x_o : out std_logic; + intlk_trans_smaller_ltc_y_o : out std_logic; + + intlk_trans_smaller_any_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted - intlk_trans_ltc_o : out std_logic; + intlk_trans_smaller_ltc_o : out std_logic; -- conditional to intlk_trans_en_i - intlk_trans_o : out std_logic + intlk_trans_smaller_o : out std_logic ); end component; @@ -257,6 +314,8 @@ package orbit_intlk_pkg is intlk_ang_clr_i : in std_logic; intlk_ang_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); intlk_ang_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_ang_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_ang_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); ----------------------------- -- Downstream ADC and position signals @@ -301,12 +360,25 @@ package orbit_intlk_pkg is intlk_ang_bigger_ltc_x_o : out std_logic; intlk_ang_bigger_ltc_y_o : out std_logic; + intlk_ang_bigger_any_o : out std_logic; + + -- only cleared when intlk_ang_clr_i is asserted + intlk_ang_bigger_ltc_o : out std_logic; + -- conditional to intlk_ang_en_i intlk_ang_bigger_o : out std_logic; + intlk_ang_smaller_x_o : out std_logic; + intlk_ang_smaller_y_o : out std_logic; + + intlk_ang_smaller_ltc_x_o : out std_logic; + intlk_ang_smaller_ltc_y_o : out std_logic; + + intlk_ang_smaller_any_o : out std_logic; + -- only cleared when intlk_ang_clr_i is asserted - intlk_ang_ltc_o : out std_logic; + intlk_ang_smaller_ltc_o : out std_logic; -- conditional to intlk_ang_en_i - intlk_ang_o : out std_logic + intlk_ang_smaller_o : out std_logic ); end component; diff --git a/hdl/modules/wb_orbit_intlk/orbit_intlk_trans.vhd b/hdl/modules/wb_orbit_intlk/orbit_intlk_trans.vhd index a8750e6b..c121bf8f 100644 --- a/hdl/modules/wb_orbit_intlk/orbit_intlk_trans.vhd +++ b/hdl/modules/wb_orbit_intlk/orbit_intlk_trans.vhd @@ -53,6 +53,8 @@ port intlk_trans_clr_i : in std_logic; intlk_trans_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); intlk_trans_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_trans_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); + intlk_trans_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0); ----------------------------- -- Downstream ADC and position signals @@ -97,12 +99,25 @@ port intlk_trans_bigger_ltc_x_o : out std_logic; intlk_trans_bigger_ltc_y_o : out std_logic; + intlk_trans_bigger_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_bigger_ltc_o : out std_logic; + -- conditional to intlk_trans_en_i intlk_trans_bigger_o : out std_logic; + intlk_trans_smaller_x_o : out std_logic; + intlk_trans_smaller_y_o : out std_logic; + + intlk_trans_smaller_ltc_x_o : out std_logic; + intlk_trans_smaller_ltc_y_o : out std_logic; + + intlk_trans_smaller_any_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted - intlk_trans_ltc_o : out std_logic; + intlk_trans_smaller_ltc_o : out std_logic; -- conditional to intlk_trans_en_i - intlk_trans_o : out std_logic + intlk_trans_smaller_o : out std_logic ); end orbit_intlk_trans; @@ -141,8 +156,11 @@ architecture rtl of orbit_intlk_trans is signal decim_pos_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0); -- interlock limits - signal intlk_trans_max : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0); - signal intlk_trans_max_n : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0); + signal intlk_trans_max : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0); + signal intlk_trans_max_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal intlk_trans_max_n : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0); + signal intlk_trans_min : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0); + signal intlk_trans_min_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0); -- valid AND signal adc_valid_and : t_bit_array(c_NUM_BPMS downto 0); @@ -156,21 +174,39 @@ architecture rtl of orbit_intlk_trans is signal trans_sum_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal trans_sum_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal trans : t_decim_data_array(c_NUM_CHANNELS-1 downto 0); - signal trans_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal trans_n : t_decim_data_array(c_NUM_CHANNELS-1 downto 0); + signal trans_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal trans_bigger : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_bigger_comb : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal trans_bigger_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal trans_bigger_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0); signal trans_bigger_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0); - signal trans_intlk_ltc_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); - signal trans_intlk_bigger_or : t_bit_array(c_NUM_CHANNELS downto 0); - signal trans_intlk_bigger : std_logic; - signal trans_intlk_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); - signal trans_intlk_ltc : std_logic; - signal trans_intlk_any : std_logic; - signal trans_intlk : std_logic; + signal trans_smaller : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_smaller_comb : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_smaller_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_smaller_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_smaller_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0); + + signal trans_intlk_det_bigger_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_intlk_bigger_ltc_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_intlk_bigger_or : t_bit_array(c_NUM_CHANNELS downto 0); + signal trans_intlk_bigger_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_intlk_bigger_ltc_or : t_bit_array(c_NUM_CHANNELS downto 0); + signal trans_intlk_bigger_ltc : std_logic; + signal trans_intlk_bigger_any : std_logic; + signal trans_intlk_bigger : std_logic; + + signal trans_intlk_det_smaller_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_intlk_smaller_ltc_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_intlk_smaller_or : t_bit_array(c_NUM_CHANNELS downto 0); + signal trans_intlk_smaller_all : t_bit_array(c_NUM_CHANNELS-1 downto 0); + signal trans_intlk_smaller_ltc_or : t_bit_array(c_NUM_CHANNELS downto 0); + signal trans_intlk_smaller_ltc : std_logic; + signal trans_intlk_smaller_any : std_logic; + signal trans_intlk_smaller : std_logic; begin @@ -209,9 +245,11 @@ begin -- Interlock limits -- X limits intlk_trans_max(0) <= intlk_trans_max_x_i; + intlk_trans_min(0) <= intlk_trans_min_x_i; -- Y limits intlk_trans_max(1) <= intlk_trans_max_y_i; + intlk_trans_min(1) <= intlk_trans_min_y_i; ---------------------------------- -- Calculate translation @@ -262,30 +300,39 @@ begin p_trans_reg : process(fs_clk_i) begin if rising_edge(fs_clk_i) then - trans_sum_reg(i) <= trans_sum(i); - trans_sum_valid_reg(i) <= trans_sum_valid(i); + if fs_rst_n_i = '0' then + trans_sum_valid_reg(i) <= '0'; + else + if trans_sum_valid(i) = '1' then + trans_sum_reg(i) <= trans_sum(i); + end if; + + trans_sum_valid_reg(i) <= trans_sum_valid(i); + end if; end if; end process; - -- Divide by 2 + -- Divide by 2 and take absolute value for comparison p_trans_divide : process(fs_clk_i) begin if rising_edge(fs_clk_i) then if fs_rst_n_i = '0' then - trans(i) <= (others => '0'); trans_valid(i) <= '0'; else - trans(i) <= std_logic_vector(shift_right(signed(trans_sum_reg(i)), 1)); + if trans_sum_valid_reg(i) = '1' then + trans(i) <= std_logic_vector(shift_right(signed(trans_sum_reg(i)), 1)); + end if; + trans_valid(i) <= trans_sum_valid_reg(i); end if; end if; end process; ---------------------------------- - -- Detect position >= Threshold + -- Detect position > Threshold ---------------------------------- -- Compare with threshold. Use the simple identity that: - -- A >= B is the same as A + (-B) and we check if MSB Carry + -- A > B is the same as A + (-B) and we check if MSB Carry -- is 1 cmp_trans_thold_bigger : gc_big_adder2 generic map ( @@ -298,43 +345,126 @@ begin a_i => trans(i), b_i => intlk_trans_max_n(i), c_i => '1', - c2_o => trans_bigger(i), + c2_o => trans_bigger_comb(i), c2x2_valid_o => trans_bigger_valid(i) ); intlk_trans_max_n(i) <= not intlk_trans_max(i); + -- comparison of different sign operands fails with the above method. + -- Just compare the sign bits, for these cases. + trans_high_bit(i) <= trans(i)(trans(i)'high); + intlk_trans_max_high_bit(i) <= intlk_trans_max(i)(intlk_trans_max(i)'high); + + trans_bigger(i) <= trans_bigger_comb(i) when + (trans_high_bit(i) xnor intlk_trans_max_high_bit(i)) = '1' else + intlk_trans_max_high_bit(i); + -- gc_big_adder2 outputs are unregistered. So register them. p_trans_thold_bigger_reg : process(fs_clk_i) begin if rising_edge(fs_clk_i) then - trans_bigger_reg(i) <= trans_bigger(i); - trans_bigger_valid_reg(i) <= trans_bigger_valid(i); + if fs_rst_n_i = '0' then + trans_bigger_valid_reg(i) <= '0'; + else + if trans_bigger_valid(i) = '1' then + trans_bigger_reg(i) <= trans_bigger(i); + end if; + + trans_bigger_valid_reg(i) <= trans_bigger_valid(i); + end if; end if; end process; + ---------------------------------- + -- Detect position < Threshold + ---------------------------------- + -- Compare with threshold. Use the simple identity that: + -- A < B is the same as -A > -B = -A + B > 0 and we check + -- if MSB Carry is 1 + cmp_trans_thold_smaller : gc_big_adder2 + generic map ( + g_data_bits => c_DECIM_WIDTH + ) + port map ( + clk_i => fs_clk_i, + stall_i => '0', + valid_i => trans_valid(i), + a_i => trans_n(i), + b_i => intlk_trans_min(i), + c_i => '1', + c2_o => trans_smaller_comb(i), + c2x2_valid_o => trans_smaller_valid(i) + ); + + trans_n(i) <= not trans(i); + + -- comparison of different sign operands fails with the above method. + -- Just compare the sign bits, for these cases. + intlk_trans_min_high_bit(i) <= intlk_trans_min(i)(intlk_trans_min(i)'high); + + trans_smaller(i) <= trans_smaller_comb(i) when + (trans_high_bit(i) xnor intlk_trans_min_high_bit(i)) = '1' else + trans_high_bit(i); + + -- gc_big_adder2 outputs are unregistered. So register them. + p_trans_thold_smaller_reg : process(fs_clk_i) + begin + if rising_edge(fs_clk_i) then + if fs_rst_n_i = '0' then + trans_smaller_valid_reg(i) <= '0'; + else + if trans_smaller_valid(i) = '1' then + trans_smaller_reg(i) <= trans_smaller(i); + end if; + + trans_smaller_valid_reg(i) <= trans_smaller_valid(i); + end if; + end if; + end process; + + ---------------------------------- + -- Latch interlocks + ---------------------------------- + + trans_intlk_det_bigger_all(i) <= trans_bigger_reg(i) and trans_bigger_valid_reg(i); + trans_intlk_det_smaller_all(i) <= trans_smaller_reg(i) and trans_smaller_valid_reg(i); + -- latch all interlocks p_latch : process(fs_clk_i) begin if rising_edge(fs_clk_i) then if fs_rst_n_i = '0' then - trans_intlk_ltc_all(i) <= '0'; + trans_intlk_bigger_ltc_all(i) <= '0'; + trans_intlk_smaller_ltc_all(i) <= '0'; else -- latch up translation interlock status -- only clear on "clear" signal if intlk_trans_clr_i = '1' then - trans_intlk_ltc_all(i) <= '0'; - elsif trans_bigger_reg(i) = '1' and - trans_bigger_valid_reg(i) = '1' and + trans_intlk_bigger_ltc_all(i) <= '0'; + elsif trans_intlk_det_bigger_all(i) = '1' and + intlk_trans_en_i = '1' then + trans_intlk_bigger_ltc_all(i) <= '1'; + end if; + + if intlk_trans_clr_i = '1' then + trans_intlk_smaller_ltc_all(i) <= '0'; + elsif trans_intlk_det_smaller_all(i) = '1' and intlk_trans_en_i = '1' then - trans_intlk_ltc_all(i) <= '1'; + trans_intlk_smaller_ltc_all(i) <= '1'; end if; -- register translation interlock when active if intlk_trans_clr_i = '1' or intlk_trans_en_i = '0' then - trans_intlk_all(i) <= '0'; + trans_intlk_bigger_all(i) <= '0'; else - trans_intlk_all(i) <= trans_intlk_ltc_all(i); + trans_intlk_bigger_all(i) <= trans_intlk_det_bigger_all(i); + end if; + + if intlk_trans_clr_i = '1' or intlk_trans_en_i = '0' then + trans_intlk_smaller_all(i) <= '0'; + else + trans_intlk_smaller_all(i) <= trans_intlk_det_smaller_all(i); end if; end if; end if; @@ -342,56 +472,62 @@ begin end generate; - intlk_trans_bigger_ltc_x_o <= trans_intlk_ltc_all(c_CHAN_X_IDX); - intlk_trans_bigger_ltc_y_o <= trans_intlk_ltc_all(c_CHAN_Y_IDX); + intlk_trans_bigger_ltc_x_o <= trans_intlk_bigger_ltc_all(c_CHAN_X_IDX); + intlk_trans_bigger_ltc_y_o <= trans_intlk_bigger_ltc_all(c_CHAN_Y_IDX); + + intlk_trans_bigger_x_o <= trans_intlk_bigger_all(c_CHAN_X_IDX); + intlk_trans_bigger_y_o <= trans_intlk_bigger_all(c_CHAN_Y_IDX); - intlk_trans_bigger_x_o <= trans_intlk_all(c_CHAN_X_IDX); - intlk_trans_bigger_y_o <= trans_intlk_all(c_CHAN_Y_IDX); + intlk_trans_smaller_ltc_x_o <= trans_intlk_smaller_ltc_all(c_CHAN_X_IDX); + intlk_trans_smaller_ltc_y_o <= trans_intlk_smaller_ltc_all(c_CHAN_Y_IDX); + + intlk_trans_smaller_x_o <= trans_intlk_smaller_all(c_CHAN_X_IDX); + intlk_trans_smaller_y_o <= trans_intlk_smaller_all(c_CHAN_Y_IDX); ---------------------------------- -- Translation interlock merging ---------------------------------- + + ---------------------------------- + -- Bigger + ---------------------------------- trans_intlk_bigger_or(0) <= '0'; -- ORing all trans_bigger gen_trans_intlk_bigger : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate - trans_intlk_bigger_or(i+1) <= trans_intlk_bigger_or(i) or trans_intlk_all(i); + trans_intlk_bigger_or(i+1) <= trans_intlk_bigger_or(i) or trans_intlk_bigger_all(i); end generate; trans_intlk_bigger <= trans_intlk_bigger_or(c_INTLK_GEN_UPTO_CHANNEL+1); intlk_trans_bigger_o <= trans_intlk_bigger; + trans_intlk_bigger_ltc_or(0) <= '0'; + -- ORing all trans_bigger_ltc + gen_trans_intlk_bigger_ltc : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate + trans_intlk_bigger_ltc_or(i+1) <= trans_intlk_bigger_ltc_or(i) or trans_intlk_bigger_ltc_all(i); + end generate; + + trans_intlk_bigger_ltc <= trans_intlk_bigger_ltc_or(c_INTLK_GEN_UPTO_CHANNEL+1); + intlk_trans_bigger_ltc_o <= trans_intlk_bigger_ltc; + ---------------------------------- - -- Translation interlock status reg + -- Smaller ---------------------------------- + trans_intlk_smaller_or(0) <= '0'; + -- ORing all trans_smaller + gen_trans_intlk_smaller : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate + trans_intlk_smaller_or(i+1) <= trans_intlk_smaller_or(i) or trans_intlk_smaller_all(i); + end generate; - trans_intlk_any <= trans_intlk_bigger; - - p_trans_out : process(fs_clk_i) - begin - if rising_edge(fs_clk_i) then - if fs_rst_n_i = '0' then - trans_intlk_ltc <= '0'; - trans_intlk <= '0'; - else - -- latch up translation interlock status - -- only clear on "clear" signal - if intlk_trans_clr_i = '1' then - trans_intlk_ltc <= '0'; - elsif trans_intlk_any = '1' then - trans_intlk_ltc <= '1'; - end if; + trans_intlk_smaller <= trans_intlk_smaller_or(c_INTLK_GEN_UPTO_CHANNEL+1); + intlk_trans_smaller_o <= trans_intlk_smaller; - -- register translation interlock when active - if intlk_trans_clr_i = '1' or intlk_trans_en_i = '0' then - trans_intlk <= '0'; - else - trans_intlk <= trans_intlk_ltc; - end if; - end if; - end if; - end process; + trans_intlk_smaller_ltc_or(0) <= '0'; + -- ORing all trans_smaller_ltc + gen_trans_intlk_smaller_ltc : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate + trans_intlk_smaller_ltc_or(i+1) <= trans_intlk_smaller_ltc_or(i) or trans_intlk_smaller_ltc_all(i); + end generate; - intlk_trans_ltc_o <= trans_intlk_ltc; - intlk_trans_o <= trans_intlk; + trans_intlk_smaller_ltc <= trans_intlk_smaller_ltc_or(c_INTLK_GEN_UPTO_CHANNEL+1); + intlk_trans_smaller_ltc_o <= trans_intlk_smaller_ltc; end rtl; diff --git a/hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd b/hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd index 435b2319..ca9b302f 100644 --- a/hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd +++ b/hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd @@ -108,15 +108,30 @@ port intlk_trans_bigger_x_o : out std_logic; intlk_trans_bigger_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted intlk_trans_bigger_ltc_x_o : out std_logic; intlk_trans_bigger_ltc_y_o : out std_logic; + intlk_trans_bigger_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_bigger_ltc_o : out std_logic; + -- conditional to intlk_trans_en_i intlk_trans_bigger_o : out std_logic; + intlk_trans_smaller_x_o : out std_logic; + intlk_trans_smaller_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted - intlk_trans_ltc_o : out std_logic; + intlk_trans_smaller_ltc_x_o : out std_logic; + intlk_trans_smaller_ltc_y_o : out std_logic; + + intlk_trans_smaller_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_smaller_ltc_o : out std_logic; -- conditional to intlk_trans_en_i - intlk_trans_o : out std_logic; + intlk_trans_smaller_o : out std_logic; intlk_ang_bigger_x_o : out std_logic; intlk_ang_bigger_y_o : out std_logic; @@ -124,12 +139,25 @@ port intlk_ang_bigger_ltc_x_o : out std_logic; intlk_ang_bigger_ltc_y_o : out std_logic; + intlk_ang_bigger_any_o : out std_logic; + + -- only cleared when intlk_ang_clr_i is asserted + intlk_ang_bigger_ltc_o : out std_logic; + -- conditional to intlk_ang_en_i intlk_ang_bigger_o : out std_logic; + intlk_ang_smaller_x_o : out std_logic; + intlk_ang_smaller_y_o : out std_logic; + + intlk_ang_smaller_ltc_x_o : out std_logic; + intlk_ang_smaller_ltc_y_o : out std_logic; + + intlk_ang_smaller_any_o : out std_logic; + -- only cleared when intlk_ang_clr_i is asserted - intlk_ang_ltc_o : out std_logic; + intlk_ang_smaller_ltc_o : out std_logic; -- conditional to intlk_ang_en_i - intlk_ang_o : out std_logic; + intlk_ang_smaller_o : out std_logic; -- only cleared when intlk_clr_i is asserted intlk_ltc_o : out std_logic; @@ -143,7 +171,7 @@ architecture rtl of wb_orbit_intlk is --------------------------------------------------------- -- Constants -- --------------------------------------------------------- - constant c_PERIPH_ADDR_SIZE : natural := 3+2; + constant c_PERIPH_ADDR_SIZE : natural := 4+2; constant c_INTLK_LMT_WIDTH : natural := 32; @@ -172,33 +200,55 @@ architecture rtl of wb_orbit_intlk is signal intlk_trans_clr_reg : std_logic; signal intlk_trans_max_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0); signal intlk_trans_max_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0); + signal intlk_trans_min_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0); + signal intlk_trans_min_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0); signal intlk_ang_en_reg : std_logic; signal intlk_ang_clr_reg : std_logic; signal intlk_ang_max_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0); signal intlk_ang_max_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0); + signal intlk_ang_min_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0); + signal intlk_ang_min_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0); signal intlk_trans_bigger_x : std_logic; signal intlk_trans_bigger_y : std_logic; signal intlk_trans_bigger_ltc_x : std_logic; signal intlk_trans_bigger_ltc_y : std_logic; + signal intlk_trans_bigger_any : std_logic; + signal intlk_trans_bigger_ltc : std_logic; signal intlk_trans_bigger : std_logic; - signal intlk_trans_ltc : std_logic; - signal intlk_trans : std_logic; + + signal intlk_trans_smaller_x : std_logic; + signal intlk_trans_smaller_y : std_logic; + signal intlk_trans_smaller_ltc_x : std_logic; + signal intlk_trans_smaller_ltc_y : std_logic; + signal intlk_trans_smaller_any : std_logic; + signal intlk_trans_smaller_ltc : std_logic; + signal intlk_trans_smaller : std_logic; + signal intlk_ang_bigger_x : std_logic; signal intlk_ang_bigger_y : std_logic; signal intlk_ang_bigger_ltc_x : std_logic; signal intlk_ang_bigger_ltc_y : std_logic; + signal intlk_ang_bigger_any : std_logic; + signal intlk_ang_bigger_ltc : std_logic; signal intlk_ang_bigger : std_logic; - signal intlk_ang_ltc : std_logic; - signal intlk_ang : std_logic; - signal intlk_ltc : std_logic; - signal intlk : std_logic; + + signal intlk_ang_smaller_x : std_logic; + signal intlk_ang_smaller_y : std_logic; + signal intlk_ang_smaller_ltc_x : std_logic; + signal intlk_ang_smaller_ltc_y : std_logic; + signal intlk_ang_smaller_any : std_logic; + signal intlk_ang_smaller_ltc : std_logic; + signal intlk_ang_smaller : std_logic; + + signal intlk : std_logic; + signal intlk_ltc : std_logic; component wb_orbit_intlk_regs port ( rst_n_i : in std_logic; clk_sys_i : in std_logic; - wb_adr_i : in std_logic_vector(2 downto 0); + wb_adr_i : in std_logic_vector(3 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; @@ -254,7 +304,7 @@ begin port map ( rst_n_i => rst_n_i, clk_sys_i => clk_i, - wb_adr_i => wb_slv_adp_out.adr(2 downto 0), + wb_adr_i => wb_slv_adp_out.adr(3 downto 0), wb_dat_i => wb_slv_adp_out.dat, wb_dat_o => wb_slv_adp_in.dat, wb_cyc_i => wb_slv_adp_out.cyc, @@ -278,29 +328,49 @@ begin intlk_trans_clr_reg <= regs_out.ctrl_trans_clr_o; intlk_trans_max_x_reg <= regs_out.trans_max_x_o; intlk_trans_max_y_reg <= regs_out.trans_max_y_o; + intlk_trans_min_x_reg <= regs_out.trans_min_x_o; + intlk_trans_min_y_reg <= regs_out.trans_min_y_o; intlk_ang_en_reg <= regs_out.ctrl_ang_en_o; intlk_ang_clr_reg <= regs_out.ctrl_ang_clr_o; intlk_ang_max_x_reg <= regs_out.ang_max_x_o; intlk_ang_max_y_reg <= regs_out.ang_max_y_o; + intlk_ang_min_x_reg <= regs_out.ang_min_x_o; + intlk_ang_min_y_reg <= regs_out.ang_min_y_o; regs_in.sts_trans_bigger_x_i <= intlk_trans_bigger_x; regs_in.sts_trans_bigger_y_i <= intlk_trans_bigger_y; regs_in.sts_trans_bigger_ltc_x_i <= intlk_trans_bigger_ltc_x; regs_in.sts_trans_bigger_ltc_y_i <= intlk_trans_bigger_ltc_y; - regs_in.sts_trans_bigger_any_i <= intlk_trans_bigger; - regs_in.sts_trans_bigger_i <= intlk_trans; - regs_in.sts_trans_bigger_ltc_i <= intlk_trans_ltc; + regs_in.sts_trans_bigger_any_i <= intlk_trans_bigger_any; + regs_in.sts_trans_bigger_ltc_i <= intlk_trans_bigger_ltc; + regs_in.sts_trans_bigger_i <= intlk_trans_bigger; + + regs_in.sts_trans_smaller_x_i <= intlk_trans_smaller_x; + regs_in.sts_trans_smaller_y_i <= intlk_trans_smaller_y; + regs_in.sts_trans_smaller_ltc_x_i <= intlk_trans_smaller_ltc_x; + regs_in.sts_trans_smaller_ltc_y_i <= intlk_trans_smaller_ltc_y; + regs_in.sts_trans_smaller_any_i <= intlk_trans_smaller_any; + regs_in.sts_trans_smaller_ltc_i <= intlk_trans_smaller_ltc; + regs_in.sts_trans_smaller_i <= intlk_trans_smaller; regs_in.sts_ang_bigger_x_i <= intlk_ang_bigger_x; regs_in.sts_ang_bigger_y_i <= intlk_ang_bigger_y; regs_in.sts_ang_bigger_ltc_x_i <= intlk_ang_bigger_ltc_x; regs_in.sts_ang_bigger_ltc_y_i <= intlk_ang_bigger_ltc_y; - regs_in.sts_ang_bigger_any_i <= intlk_ang_bigger; - regs_in.sts_ang_bigger_i <= intlk_ang; - regs_in.sts_ang_bigger_ltc_i <= intlk_ang_ltc; + regs_in.sts_ang_bigger_any_i <= intlk_ang_bigger_any; + regs_in.sts_ang_bigger_ltc_i <= intlk_ang_bigger_ltc; + regs_in.sts_ang_bigger_i <= intlk_ang_bigger; - regs_in.sts_intlk_bigger_i <= intlk; - regs_in.sts_intlk_bigger_ltc_i <= intlk_ltc; + regs_in.sts_ang_smaller_x_i <= intlk_ang_smaller_x; + regs_in.sts_ang_smaller_y_i <= intlk_ang_smaller_y; + regs_in.sts_ang_smaller_ltc_x_i <= intlk_ang_smaller_ltc_x; + regs_in.sts_ang_smaller_ltc_y_i <= intlk_ang_smaller_ltc_y; + regs_in.sts_ang_smaller_any_i <= intlk_ang_smaller_any; + regs_in.sts_ang_smaller_ltc_i <= intlk_ang_smaller_ltc; + regs_in.sts_ang_smaller_i <= intlk_ang_smaller; + + regs_in.sts_intlk_i <= intlk; + regs_in.sts_intlk_ltc_i <= intlk_ltc; -- Unused wishbone signals wb_slv_adp_in.err <= '0'; @@ -338,12 +408,16 @@ begin intlk_trans_clr_i => intlk_trans_clr_reg, intlk_trans_max_x_i => intlk_trans_max_x_reg, intlk_trans_max_y_i => intlk_trans_max_y_reg, + intlk_trans_min_x_i => intlk_trans_min_x_reg, + intlk_trans_min_y_i => intlk_trans_min_y_reg, -- Angular interlock on/off intlk_ang_en_i => intlk_ang_en_reg, -- Angular interlock clear intlk_ang_clr_i => intlk_ang_clr_reg, intlk_ang_max_x_i => intlk_ang_max_x_reg, intlk_ang_max_y_i => intlk_ang_max_y_reg, + intlk_ang_min_x_i => intlk_ang_min_x_reg, + intlk_ang_min_y_i => intlk_ang_min_y_reg, ----------------------------- -- Downstream ADC and position signals @@ -391,10 +465,21 @@ begin intlk_trans_bigger_ltc_x_o => intlk_trans_bigger_ltc_x, intlk_trans_bigger_ltc_y_o => intlk_trans_bigger_ltc_y, + intlk_trans_bigger_any_o => intlk_trans_bigger_any, + + intlk_trans_bigger_ltc_o => intlk_trans_bigger_ltc, intlk_trans_bigger_o => intlk_trans_bigger, - intlk_trans_ltc_o => intlk_trans_ltc, - intlk_trans_o => intlk_trans, + intlk_trans_smaller_x_o => intlk_trans_smaller_x, + intlk_trans_smaller_y_o => intlk_trans_smaller_y, + + intlk_trans_smaller_ltc_x_o => intlk_trans_smaller_ltc_x, + intlk_trans_smaller_ltc_y_o => intlk_trans_smaller_ltc_y, + + intlk_trans_smaller_any_o => intlk_trans_smaller_any, + + intlk_trans_smaller_ltc_o => intlk_trans_smaller_ltc, + intlk_trans_smaller_o => intlk_trans_smaller, intlk_ang_bigger_x_o => intlk_ang_bigger_x, intlk_ang_bigger_y_o => intlk_ang_bigger_y, @@ -402,10 +487,21 @@ begin intlk_ang_bigger_ltc_x_o => intlk_ang_bigger_ltc_x, intlk_ang_bigger_ltc_y_o => intlk_ang_bigger_ltc_y, + intlk_ang_bigger_any_o => intlk_ang_bigger_any, + + intlk_ang_bigger_ltc_o => intlk_ang_bigger_ltc, intlk_ang_bigger_o => intlk_ang_bigger, - intlk_ang_ltc_o => intlk_ang_ltc, - intlk_ang_o => intlk_ang, + intlk_ang_smaller_x_o => intlk_ang_smaller_x, + intlk_ang_smaller_y_o => intlk_ang_smaller_y, + + intlk_ang_smaller_ltc_x_o => intlk_ang_smaller_ltc_x, + intlk_ang_smaller_ltc_y_o => intlk_ang_smaller_ltc_y, + + intlk_ang_smaller_any_o => intlk_ang_smaller_any, + + intlk_ang_smaller_ltc_o => intlk_ang_smaller_ltc, + intlk_ang_smaller_o => intlk_ang_smaller, intlk_ltc_o => intlk_ltc, intlk_o => intlk @@ -418,10 +514,21 @@ begin intlk_trans_bigger_ltc_x_o <= intlk_trans_bigger_ltc_x; intlk_trans_bigger_ltc_y_o <= intlk_trans_bigger_ltc_y; + intlk_trans_bigger_any_o <= intlk_trans_bigger_any; + + intlk_trans_bigger_ltc_o <= intlk_trans_bigger_ltc; intlk_trans_bigger_o <= intlk_trans_bigger; - intlk_trans_ltc_o <= intlk_trans_ltc; - intlk_trans_o <= intlk_trans; + intlk_trans_smaller_x_o <= intlk_trans_smaller_x; + intlk_trans_smaller_y_o <= intlk_trans_smaller_y; + + intlk_trans_smaller_ltc_x_o <= intlk_trans_smaller_ltc_x; + intlk_trans_smaller_ltc_y_o <= intlk_trans_smaller_ltc_y; + + intlk_trans_smaller_any_o <= intlk_trans_smaller_any; + + intlk_trans_smaller_ltc_o <= intlk_trans_smaller_ltc; + intlk_trans_smaller_o <= intlk_trans_smaller; intlk_ang_bigger_x_o <= intlk_ang_bigger_x; intlk_ang_bigger_y_o <= intlk_ang_bigger_y; @@ -429,10 +536,21 @@ begin intlk_ang_bigger_ltc_x_o <= intlk_ang_bigger_ltc_x; intlk_ang_bigger_ltc_y_o <= intlk_ang_bigger_ltc_y; + intlk_ang_bigger_any_o <= intlk_ang_bigger_any; + + intlk_ang_bigger_ltc_o <= intlk_ang_bigger_ltc; intlk_ang_bigger_o <= intlk_ang_bigger; - intlk_ang_ltc_o <= intlk_ang_ltc; - intlk_ang_o <= intlk_ang; + intlk_ang_smaller_x_o <= intlk_ang_smaller_x; + intlk_ang_smaller_y_o <= intlk_ang_smaller_y; + + intlk_ang_smaller_ltc_x_o <= intlk_ang_smaller_ltc_x; + intlk_ang_smaller_ltc_y_o <= intlk_ang_smaller_ltc_y; + + intlk_ang_smaller_any_o <= intlk_ang_smaller_any; + + intlk_ang_smaller_ltc_o <= intlk_ang_smaller_ltc; + intlk_ang_smaller_o <= intlk_ang_smaller; intlk_ltc_o <= intlk_ltc; intlk_o <= intlk; diff --git a/hdl/modules/wb_orbit_intlk/wbgen/doc/orbit_intlk_regs_wb.html b/hdl/modules/wb_orbit_intlk/wbgen/doc/orbit_intlk_regs_wb.html index 7768215c..05371315 100644 --- a/hdl/modules/wb_orbit_intlk/wbgen/doc/orbit_intlk_regs_wb.html +++ b/hdl/modules/wb_orbit_intlk/wbgen/doc/orbit_intlk_regs_wb.html @@ -37,10 +37,14 @@

Contents:

3.1. General Control Signals
3.2. General Status Signals
3.3. Minimum sum threshold
-3.4. Translation X threshold
-3.5. Translation Y threshold
-3.6. Angular X threshold
-3.7. Angular Y threshold
+3.4. Maximum translation X threshold
+3.5. Maximum translation Y threshold
+3.6. Maximum angular X threshold
+3.7. Maximum angular Y threshold
+3.8. Minimum translation X threshold
+3.9. Minimum translation Y threshold
+3.10. Minimum angular X threshold
+3.11. Minimum angular Y threshold

1. Memory map summary

@@ -119,7 +123,7 @@

1. Memory map summary

REG + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-Translation X threshold +Maximum translation X threshold orbit_intlk_trans_max_x @@ -136,7 +140,7 @@

1. Memory map summary

REG 		-Translation Y threshold +Maximum translation Y threshold orbit_intlk_trans_max_y @@ -153,7 +157,7 @@

1. Memory map summary

REG 		-Angular X threshold +Maximum angular X threshold orbit_intlk_ang_max_x @@ -170,7 +174,7 @@

1. Memory map summary

REG 		-Angular Y threshold +Maximum angular Y threshold orbit_intlk_ang_max_y @@ -179,16 +183,84 @@

1. Memory map summary

ANG_MAX_Y
+0x7 + +REG + +Minimum translation X threshold + +orbit_intlk_trans_min_x + +TRANS_MIN_X +
+0x8 + +REG + +Minimum translation Y threshold + +orbit_intlk_trans_min_y + +TRANS_MIN_Y +
+0x9 + +REG + +Minimum angular X threshold + +orbit_intlk_ang_min_x + +ANG_MIN_X +
+0xa + +REG + +Minimum angular Y threshold + +orbit_intlk_ang_min_y + +ANG_MIN_Y +

2. HDL symbol

@@ -667,13 +739,13 @@

2. HDL symbol

@@ -687,10 +759,10 @@

2. HDL symbol

@@ -704,10 +776,10 @@

2. HDL symbol

@@ -718,13 +790,13 @@

2. HDL symbol

@@ -738,10 +810,10 @@

2. HDL symbol

@@ -755,10 +827,10 @@

2. HDL symbol

@@ -769,13 +841,13 @@

2. HDL symbol

@@ -789,10 +861,10 @@

2. HDL symbol

@@ -806,10 +878,10 @@

2. HDL symbol

@@ -820,13 +892,30 @@

2. HDL symbol

+ + + + + + + @@ -840,10 +929,27 @@

2. HDL symbol

+ + + + + + + @@ -857,10 +963,10 @@

2. HDL symbol

@@ -891,7 +997,7 @@

2. HDL symbol

-
-→ +⇒ -rst_n_i +wb_adr_i[3:0] @@ -202,10 +274,10 @@

2. HDL symbol

-→ +⇒ -clk_sys_i +wb_dat_i[31:0] @@ -219,10 +291,10 @@

2. HDL symbol

-⇒ +⇐ -wb_adr_i[2:0] +wb_dat_o[31:0] @@ -236,10 +308,10 @@

2. HDL symbol

-⇒ +→ -wb_dat_i[31:0] +wb_cyc_i @@ -253,10 +325,10 @@

2. HDL symbol

-⇐ +⇒ -wb_dat_o[31:0] +wb_sel_i[3:0] @@ -273,7 +345,7 @@

2. HDL symbol

→ 		-wb_cyc_i +wb_stb_i @@ -287,10 +359,10 @@

2. HDL symbol

-⇒ +→ -wb_sel_i[3:0] +wb_we_i @@ -304,10 +376,10 @@

2. HDL symbol

-→ +← -wb_stb_i +wb_ack_o @@ -321,10 +393,10 @@

2. HDL symbol

-→ +← -wb_we_i +wb_err_o @@ -341,7 +413,7 @@

2. HDL symbol

← 		-wb_ack_o +wb_rty_o   @@ -619,7 +691,7 @@

2. HDL symbol

 -orbit_intlk_sts_intlk_bigger_i +orbit_intlk_sts_intlk_i ← @@ -636,7 +708,7 @@

2. HDL symbol

 -orbit_intlk_sts_intlk_bigger_ltc_i +orbit_intlk_sts_intlk_ltc_i ← @@ -653,10 +725,10 @@

2. HDL symbol

 -orbit_intlk_sts_reserved_i[15:0] +orbit_intlk_sts_trans_smaller_x_i -⇐ +←
-  + - +orbit_intlk_sts_trans_smaller_y_i - +←
-Minimum sum threshold: +orbit_intlk_sts_trans_smaller_ltc_x_i - +←
-orbit_intlk_min_sum_o[31:0] +orbit_intlk_sts_trans_smaller_ltc_y_i -⇒ +←
-  + - +orbit_intlk_sts_trans_smaller_any_i - +←
-Translation X threshold: +orbit_intlk_sts_trans_smaller_i - +←
-orbit_intlk_trans_max_x_o[31:0] +orbit_intlk_sts_trans_smaller_ltc_i -⇒ +←
-  + - +orbit_intlk_sts_ang_smaller_x_i - +←
-Translation Y threshold: +orbit_intlk_sts_ang_smaller_y_i - +←
-orbit_intlk_trans_max_y_o[31:0] +orbit_intlk_sts_ang_smaller_ltc_x_i -⇒ +←
-  + - +orbit_intlk_sts_ang_smaller_ltc_y_i +← +
+ + + + + +orbit_intlk_sts_ang_smaller_any_i + +←
-Angular X threshold: +orbit_intlk_sts_ang_smaller_i +← +
+ + + + + +orbit_intlk_sts_ang_smaller_ltc_i + +←
-orbit_intlk_ang_max_x_o[31:0] +orbit_intlk_sts_reserved_i[1:0] -⇒ +⇐
-Angular Y threshold: +Minimum sum threshold: @@ -908,101 +1014,1701 @@

2. HDL symbol

 -orbit_intlk_ang_max_y_o[31:0] +orbit_intlk_min_sum_o[31:0] ⇒
- -

3. Register description

- -

3.1. General Control Signals

- - - - - - - - - - - - - - -
-HW prefix: - -orbit_intlk_ctrl + +
-HW address: + + -0x0 + + 
-C prefix: + + -CTRL + +
-C offset: + + -0x0 + +
-

-General Controls -

- - - - - - + + - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-31 + + -30 + +Maximum translation X threshold: -29 + + -28 +
+ -27 + + -26 + + -25 + +orbit_intlk_trans_max_x_o[31:0] -24 + +⇒
-- - -RESERVED[23:17] - + + - + +  + + + +
+ + + + + + +Maximum translation Y threshold: + + +
+ + + + + + +orbit_intlk_trans_max_y_o[31:0] + +⇒ +
+ + + + +  + + + + +
+ + + + + + +Maximum angular X threshold: + + +
+ + + + + + +orbit_intlk_ang_max_x_o[31:0] + +⇒ +
+ + + + +  + + + + +
+ + + + + + +Maximum angular Y threshold: + + +
+ + + + + + +orbit_intlk_ang_max_y_o[31:0] + +⇒ +
+ + + + +  + + + + +
+ + + + + + +Minimum translation X threshold: + + +
+ + + + + + +orbit_intlk_trans_min_x_o[31:0] + +⇒ +
+ + + + +  + + + + +
+ + + + + + +Minimum translation Y threshold: + + +
+ + + + + + +orbit_intlk_trans_min_y_o[31:0] + +⇒ +
+ + + + +  + + + + +
+ + + + + + +Minimum angular X threshold: + + +
+ + + + + + +orbit_intlk_ang_min_x_o[31:0] + +⇒ +
+ + + + +  + + + + +
+ + + + + + +Minimum angular Y threshold: + + +
+ + + + + + +orbit_intlk_ang_min_y_o[31:0] + +⇒ +
+ +

3. Register description

+ +

3.1. General Control Signals

+ + + + + + + + + + + + + + + + + +
+HW prefix: + +orbit_intlk_ctrl +
+HW address: + +0x0 +
+C prefix: + +CTRL +
+C offset: + +0x0 +
+

+General Controls +

+ + + + + + + + + + + + + + + + + + + + + +
+31 + +30 + +29 + +28 + +27 + +26 + +25 + +24 +
+- + +RESERVED[23:17] + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + +
+23 + +22 + +21 + +20 + +19 + +18 + +17 + +16 +
+RESERVED[16:9] + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + +
+15 + +14 + +13 + +12 + +11 + +10 + +9 + +8 +
+RESERVED[8:1] + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + +
+7 + +6 + +5 + +4 + +3 + +2 + +1 + +0 +
+RESERVED[0:0] + +ANG_CLR + +ANG_EN + +TRANS_CLR + +TRANS_EN + +MIN_SUM_EN + +CLR + +EN +
+ + +

3.2. General Status Signals

+ + + + + + + + + + + + + + + + + +
+HW prefix: + +orbit_intlk_sts +
+HW address: + +0x1 +
+C prefix: + +STS +
+C offset: + +0x4 +
+

+General Status +

+ + + + + + + + + + + + + + + + + + + + + +
+31 + +30 + +29 + +28 + +27 + +26 + +25 + +24 +
+RESERVED[1:0] + +ANG_SMALLER_LTC + +ANG_SMALLER + +ANG_SMALLER_ANY + +ANG_SMALLER_LTC_Y + +ANG_SMALLER_LTC_X + +ANG_SMALLER_Y + + +
+ + + + + + + + + + + + + + + + + + + + + +
+23 + +22 + +21 + +20 + +19 + +18 + +17 + +16 +
+ANG_SMALLER_X + +TRANS_SMALLER_LTC + +TRANS_SMALLER + +TRANS_SMALLER_ANY + +TRANS_SMALLER_LTC_Y + +TRANS_SMALLER_LTC_X + +TRANS_SMALLER_Y + +TRANS_SMALLER_X +
+ + + + + + + + + + + + + + + + + + + + + +
+15 + +14 + +13 + +12 + +11 + +10 + +9 + +8 +
+INTLK_LTC + +INTLK + +ANG_BIGGER_LTC + +ANG_BIGGER + +ANG_BIGGER_ANY + +ANG_BIGGER_LTC_Y + +ANG_BIGGER_LTC_X + +ANG_BIGGER_Y +
+ + + + + + + + + + + + + + + + + + + + + +
+7 + +6 + +5 + +4 + +3 + +2 + +1 + +0 +
+ANG_BIGGER_X + +TRANS_BIGGER_LTC + +TRANS_BIGGER + +TRANS_BIGGER_ANY + +TRANS_BIGGER_LTC_Y + +TRANS_BIGGER_LTC_X + +TRANS_BIGGER_Y + +TRANS_BIGGER_X +
+ + +

3.3. Minimum sum threshold

+ + + + + + + + + + + + + + + + + +
+HW prefix: + +orbit_intlk_min_sum +
+HW address: + +0x2 +
+C prefix: + +MIN_SUM +
+C offset: + +0x8 +
+

+Minimum sum threshold to enable interlock +

+ + + + + + + + + + + + + + + + + + + + + +
+31 + +30 + +29 + +28 + +27 + +26 + +25 + +24 +
+MIN_SUM[31:24] + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + +
+23 + +22 + +21 + +20 + +19 + +18 + +17 + +16 +
+MIN_SUM[23:16] + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + +
+15 + +14 + +13 + +12 + +11 + +10 + +9 + +8 +
+MIN_SUM[15:8] + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + +
+7 + +6 + +5 + +4 + +3 + +2 + +1 + +0 +
+MIN_SUM[7:0] + + + + + + + + + + + + + + +
+ + +

3.4. Maximum translation X threshold

+ + + + + + + + + + + + + + + + + +
+HW prefix: + +orbit_intlk_trans_max_x +
+HW address: + +0x3 +
+C prefix: + +TRANS_MAX_X +
+C offset: + +0xc +
+

+Maximum translation X threshold to trip interlock +

+ + + + + + + + + + + + + + + + + + + + + +
+31 + +30 + +29 + +28 + +27 + +26 + +25 + +24 +
+TRANS_MAX_X[31:24] + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + +
+23 + +22 + +21 + +20 + +19 + +18 + +17 + +16 +
+TRANS_MAX_X[23:16] + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + +
+15 + +14 + +13 + +12 + +11 + +10 + +9 + +8 +
+TRANS_MAX_X[15:8] + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + +
+7 + +6 + +5 + +4 + +3 + +2 + +1 + +0 +
+TRANS_MAX_X[7:0] + + + + + + + + + + + + + + +
+ + +

3.5. Maximum translation Y threshold

+ + + + + + + + + + + + + + + + + +
+HW prefix: + +orbit_intlk_trans_max_y +
+HW address: + +0x4 +
+C prefix: + +TRANS_MAX_Y +
+C offset: + +0x10 +
+

+Maximum translation Y threshold to trip interlock +

+ + + + + + + + + + + + + + + + + + + - - - - - - - - +
+31 + +30 + +29 + +28 + +27 + +26 + +25 + +24 +
+TRANS_MAX_Y[31:24] + + + + + + + + + + + @@ -1039,7 +2745,7 @@

3.1. General Control Signals

-RESERVED[16:9] +TRANS_MAX_Y[23:16] @@ -1093,7 +2799,7 @@

3.1. General Control Signals

-RESERVED[8:1] +TRANS_MAX_Y[15:8] @@ -1146,75 +2852,47 @@

3.1. General Control Signals
-RESERVED[0:0] - -ANG_CLR + +TRANS_MAX_Y[7:0] -ANG_EN + + -TRANS_CLR + + -TRANS_EN + + -MIN_SUM_EN + + -CLR + + -EN + + + +
- -

3.2. General Status Signals

+ +

3.6. Maximum angular X threshold

@@ -1222,7 +2900,7 @@

3.2. General Status Signals

HW address: @@ -1230,7 +2908,7 @@

3.2. General Status Signals

C prefix: @@ -1238,12 +2916,12 @@

3.2. General Status Signals

C offset:
HW prefix: -orbit_intlk_sts +orbit_intlk_ang_max_x
-0x1 +0x5
-STS +ANG_MAX_X
-0x4 +0x14

-General Status +Maximum angular X threshold to trip interlock

@@ -1274,7 +2952,7 @@

3.2. General Status Signals

- - - - - - - -
-RESERVED[15:8] +ANG_MAX_X[31:24] @@ -1328,7 +3006,7 @@

3.2. General Status Signals

-RESERVED[7:0] +ANG_MAX_X[23:16] @@ -1381,29 +3059,29 @@

3.2. General Status Signals
-INTLK_BIGGER_LTC + +ANG_MAX_X[15:8] -INTLK_BIGGER + + -ANG_BIGGER_LTC + + -ANG_BIGGER + + -ANG_BIGGER_ANY + + -ANG_BIGGER_LTC_Y + + -ANG_BIGGER_LTC_X + + -ANG_BIGGER_Y + +
@@ -1435,111 +3113,47 @@

3.2. General Status Signals

- -ANG_BIGGER_X + +ANG_MAX_X[7:0] - -TRANS_BIGGER_LTC + + - -TRANS_BIGGER + + - -TRANS_BIGGER_ANY + + - -TRANS_BIGGER_LTC_Y + + - -TRANS_BIGGER_LTC_X + + - -TRANS_BIGGER_Y + + - -TRANS_BIGGER_X + + - -

3.3. Minimum sum threshold

+ +

3.7. Maximum angular Y threshold

@@ -1547,7 +3161,7 @@

3.3. Minimum sum threshold

HW address: @@ -1555,7 +3169,7 @@

3.3. Minimum sum threshold

C prefix: @@ -1563,12 +3177,12 @@

3.3. Minimum sum threshold

C offset:
HW prefix: -orbit_intlk_min_sum +orbit_intlk_ang_max_y
-0x2 +0x6
-MIN_SUM +ANG_MAX_Y
-0x8 +0x18

-Minimum sum threshold to enable interlock +Maximum angular Y threshold to trip interlock

@@ -1599,7 +3213,7 @@

3.3. Minimum sum threshold

-MIN_SUM[31:24] +ANG_MAX_Y[31:24] @@ -1653,7 +3267,7 @@

3.3. Minimum sum threshold

-MIN_SUM[23:16] +ANG_MAX_Y[23:16] @@ -1707,7 +3321,7 @@

3.3. Minimum sum threshold

-MIN_SUM[15:8] +ANG_MAX_Y[15:8] @@ -1761,7 +3375,7 @@

3.3. Minimum sum threshold

-MIN_SUM[7:0] +ANG_MAX_Y[7:0] @@ -1788,19 +3402,19 @@

3.3. Minimum sum threshold

- -

3.4. Translation X threshold

+ +

3.8. Minimum translation X threshold

@@ -1808,7 +3422,7 @@

3.4. Translation X threshold

HW address: @@ -1816,7 +3430,7 @@

3.4. Translation X threshold

C prefix: @@ -1824,12 +3438,12 @@

3.4. Translation X threshold

C offset:
HW prefix: -orbit_intlk_trans_max_x +orbit_intlk_trans_min_x
-0x3 +0x7
-TRANS_MAX_X +TRANS_MIN_X
-0xc +0x1c

-Translation X threshold to trip interlock +Minimum translation X threshold to trip interlock

@@ -1860,7 +3474,7 @@

3.4. Translation X threshold

-TRANS_MAX_X[31:24] +TRANS_MIN_X[31:24] @@ -1914,7 +3528,7 @@

3.4. Translation X threshold

-TRANS_MAX_X[23:16] +TRANS_MIN_X[23:16] @@ -1968,7 +3582,7 @@

3.4. Translation X threshold

-TRANS_MAX_X[15:8] +TRANS_MIN_X[15:8] @@ -2022,7 +3636,7 @@

3.4. Translation X threshold

-TRANS_MAX_X[7:0] +TRANS_MIN_X[7:0] @@ -2049,19 +3663,19 @@

3.4. Translation X threshold

- -

3.5. Translation Y threshold

+ +

3.9. Minimum translation Y threshold

@@ -2069,7 +3683,7 @@

3.5. Translation Y threshold

HW address: @@ -2077,7 +3691,7 @@

3.5. Translation Y threshold

C prefix: @@ -2085,12 +3699,12 @@

3.5. Translation Y threshold

C offset:
HW prefix: -orbit_intlk_trans_max_y +orbit_intlk_trans_min_y
-0x4 +0x8
-TRANS_MAX_Y +TRANS_MIN_Y
-0x10 +0x20

-Translation Y threshold to trip interlock +Minimum translation Y threshold to trip interlock

@@ -2121,7 +3735,7 @@

3.5. Translation Y threshold

-TRANS_MAX_Y[31:24] +TRANS_MIN_Y[31:24] @@ -2175,7 +3789,7 @@

3.5. Translation Y threshold

-TRANS_MAX_Y[23:16] +TRANS_MIN_Y[23:16] @@ -2229,7 +3843,7 @@

3.5. Translation Y threshold

-TRANS_MAX_Y[15:8] +TRANS_MIN_Y[15:8] @@ -2283,7 +3897,7 @@

3.5. Translation Y threshold

-TRANS_MAX_Y[7:0] +TRANS_MIN_Y[7:0] @@ -2310,19 +3924,19 @@

3.5. Translation Y threshold

- -

3.6. Angular X threshold

+ +

3.10. Minimum angular X threshold

@@ -2330,7 +3944,7 @@

3.6. Angular X threshold

HW address: @@ -2338,7 +3952,7 @@

3.6. Angular X threshold

C prefix: @@ -2346,12 +3960,12 @@

3.6. Angular X threshold

C offset:
HW prefix: -orbit_intlk_ang_max_x +orbit_intlk_ang_min_x
-0x5 +0x9
-ANG_MAX_X +ANG_MIN_X
-0x14 +0x24

-Angular X threshold to trip interlock +Minimum angular X threshold to trip interlock

@@ -2382,7 +3996,7 @@

3.6. Angular X threshold

-ANG_MAX_X[31:24] +ANG_MIN_X[31:24] @@ -2436,7 +4050,7 @@

3.6. Angular X threshold

-ANG_MAX_X[23:16] +ANG_MIN_X[23:16] @@ -2490,7 +4104,7 @@

3.6. Angular X threshold

-ANG_MAX_X[15:8] +ANG_MIN_X[15:8] @@ -2544,7 +4158,7 @@

3.6. Angular X threshold

-ANG_MAX_X[7:0] +ANG_MIN_X[7:0] @@ -2571,19 +4185,19 @@

3.6. Angular X threshold

- -

3.7. Angular Y threshold

+ +

3.11. Minimum angular Y threshold

@@ -2591,7 +4205,7 @@

3.7. Angular Y threshold

HW address: @@ -2599,7 +4213,7 @@

3.7. Angular Y threshold

C prefix: @@ -2607,12 +4221,12 @@

3.7. Angular Y threshold

C offset:
HW prefix: -orbit_intlk_ang_max_y +orbit_intlk_ang_min_y
-0x6 +0xa
-ANG_MAX_Y +ANG_MIN_Y
-0x18 +0x28

-Angular Y threshold to trip interlock +Minimum angular Y threshold to trip interlock

@@ -2643,7 +4257,7 @@

3.7. Angular Y threshold

-ANG_MAX_Y[31:24] +ANG_MIN_Y[31:24] @@ -2697,7 +4311,7 @@

3.7. Angular Y threshold

-ANG_MAX_Y[23:16] +ANG_MIN_Y[23:16] @@ -2751,7 +4365,7 @@

3.7. Angular Y threshold

-ANG_MAX_Y[15:8] +ANG_MIN_Y[15:8] @@ -2805,7 +4419,7 @@

3.7. Angular Y threshold

-ANG_MAX_Y[7:0] +ANG_MIN_Y[7:0] @@ -2832,9 +4446,9 @@

3.7. Angular Y threshold

diff --git a/hdl/modules/wb_orbit_intlk/wbgen/orbit_intlk_regs.h b/hdl/modules/wb_orbit_intlk/wbgen/orbit_intlk_regs.h index 7f2f1e73..b1a327c8 100644 --- a/hdl/modules/wb_orbit_intlk/wbgen/orbit_intlk_regs.h +++ b/hdl/modules/wb_orbit_intlk/wbgen/orbit_intlk_regs.h @@ -3,7 +3,7 @@ * File : orbit_intlk_regs.h * Author : auto-generated by wbgen2 from wb_orbit_intlk_regs.wb - * Created : Thu Jun 18 16:34:13 2020 + * Created : Fri Aug 21 17:24:04 2020 * Standard : ANSI C THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_orbit_intlk_regs.wb @@ -14,7 +14,11 @@ #ifndef __WBGEN2_REGDEFS_WB_ORBIT_INTLK_REGS_WB #define __WBGEN2_REGDEFS_WB_ORBIT_INTLK_REGS_WB +#ifdef __KERNEL__ +#include +#else #include +#endif #if defined( __GNUC__) #define PACKED __attribute__ ((packed)) @@ -104,39 +108,97 @@ /* definitions for field: Angular Bigger Latched in reg: General Status Signals */ #define ORBIT_INTLK_STS_ANG_BIGGER_LTC WBGEN2_GEN_MASK(13, 1) -/* definitions for field: Interlock Bigger in reg: General Status Signals */ -#define ORBIT_INTLK_STS_INTLK_BIGGER WBGEN2_GEN_MASK(14, 1) +/* definitions for field: Interlock Trip in reg: General Status Signals */ +#define ORBIT_INTLK_STS_INTLK WBGEN2_GEN_MASK(14, 1) + +/* definitions for field: Interlock Trip Latched in reg: General Status Signals */ +#define ORBIT_INTLK_STS_INTLK_LTC WBGEN2_GEN_MASK(15, 1) + +/* definitions for field: Translation Smaller X in reg: General Status Signals */ +#define ORBIT_INTLK_STS_TRANS_SMALLER_X WBGEN2_GEN_MASK(16, 1) + +/* definitions for field: Translation Smaller Y in reg: General Status Signals */ +#define ORBIT_INTLK_STS_TRANS_SMALLER_Y WBGEN2_GEN_MASK(17, 1) + +/* definitions for field: Translation Smaller Latched X in reg: General Status Signals */ +#define ORBIT_INTLK_STS_TRANS_SMALLER_LTC_X WBGEN2_GEN_MASK(18, 1) + +/* definitions for field: Translation Smaller Latched Y in reg: General Status Signals */ +#define ORBIT_INTLK_STS_TRANS_SMALLER_LTC_Y WBGEN2_GEN_MASK(19, 1) + +/* definitions for field: Translation Smaller Any (X/Y) in reg: General Status Signals */ +#define ORBIT_INTLK_STS_TRANS_SMALLER_ANY WBGEN2_GEN_MASK(20, 1) + +/* definitions for field: Translation Smaller in reg: General Status Signals */ +#define ORBIT_INTLK_STS_TRANS_SMALLER WBGEN2_GEN_MASK(21, 1) + +/* definitions for field: Translation Smaller Latched in reg: General Status Signals */ +#define ORBIT_INTLK_STS_TRANS_SMALLER_LTC WBGEN2_GEN_MASK(22, 1) -/* definitions for field: Interlock Bigger Latched in reg: General Status Signals */ -#define ORBIT_INTLK_STS_INTLK_BIGGER_LTC WBGEN2_GEN_MASK(15, 1) +/* definitions for field: Angular Smaller X in reg: General Status Signals */ +#define ORBIT_INTLK_STS_ANG_SMALLER_X WBGEN2_GEN_MASK(23, 1) + +/* definitions for field: Angular Smaller Y in reg: General Status Signals */ +#define ORBIT_INTLK_STS_ANG_SMALLER_Y WBGEN2_GEN_MASK(24, 1) + +/* definitions for field: Angular Smaller Latched X in reg: General Status Signals */ +#define ORBIT_INTLK_STS_ANG_SMALLER_LTC_X WBGEN2_GEN_MASK(25, 1) + +/* definitions for field: Angular Smaller Latched Y in reg: General Status Signals */ +#define ORBIT_INTLK_STS_ANG_SMALLER_LTC_Y WBGEN2_GEN_MASK(26, 1) + +/* definitions for field: Angular Smaller Any (X/Y) in reg: General Status Signals */ +#define ORBIT_INTLK_STS_ANG_SMALLER_ANY WBGEN2_GEN_MASK(27, 1) + +/* definitions for field: Angular Smaller in reg: General Status Signals */ +#define ORBIT_INTLK_STS_ANG_SMALLER WBGEN2_GEN_MASK(28, 1) + +/* definitions for field: Angular Smaller Latched in reg: General Status Signals */ +#define ORBIT_INTLK_STS_ANG_SMALLER_LTC WBGEN2_GEN_MASK(29, 1) /* definitions for field: Reserved in reg: General Status Signals */ -#define ORBIT_INTLK_STS_RESERVED_MASK WBGEN2_GEN_MASK(16, 16) -#define ORBIT_INTLK_STS_RESERVED_SHIFT 16 -#define ORBIT_INTLK_STS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16) -#define ORBIT_INTLK_STS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16) +#define ORBIT_INTLK_STS_RESERVED_MASK WBGEN2_GEN_MASK(30, 2) +#define ORBIT_INTLK_STS_RESERVED_SHIFT 30 +#define ORBIT_INTLK_STS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 30, 2) +#define ORBIT_INTLK_STS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 30, 2) /* definitions for register: Minimum sum threshold */ -/* definitions for register: Translation X threshold */ +/* definitions for register: Maximum translation X threshold */ + +/* definitions for register: Maximum translation Y threshold */ + +/* definitions for register: Maximum angular X threshold */ + +/* definitions for register: Maximum angular Y threshold */ + +/* definitions for register: Minimum translation X threshold */ -/* definitions for register: Translation Y threshold */ +/* definitions for register: Minimum translation Y threshold */ -/* definitions for register: Angular X threshold */ +/* definitions for register: Minimum angular X threshold */ -/* definitions for register: Angular Y threshold */ +/* definitions for register: Minimum angular Y threshold */ /* [0x0]: REG General Control Signals */ #define ORBIT_INTLK_REG_CTRL 0x00000000 /* [0x4]: REG General Status Signals */ #define ORBIT_INTLK_REG_STS 0x00000004 /* [0x8]: REG Minimum sum threshold */ #define ORBIT_INTLK_REG_MIN_SUM 0x00000008 -/* [0xc]: REG Translation X threshold */ +/* [0xc]: REG Maximum translation X threshold */ #define ORBIT_INTLK_REG_TRANS_MAX_X 0x0000000c -/* [0x10]: REG Translation Y threshold */ +/* [0x10]: REG Maximum translation Y threshold */ #define ORBIT_INTLK_REG_TRANS_MAX_Y 0x00000010 -/* [0x14]: REG Angular X threshold */ +/* [0x14]: REG Maximum angular X threshold */ #define ORBIT_INTLK_REG_ANG_MAX_X 0x00000014 -/* [0x18]: REG Angular Y threshold */ +/* [0x18]: REG Maximum angular Y threshold */ #define ORBIT_INTLK_REG_ANG_MAX_Y 0x00000018 +/* [0x1c]: REG Minimum translation X threshold */ +#define ORBIT_INTLK_REG_TRANS_MIN_X 0x0000001c +/* [0x20]: REG Minimum translation Y threshold */ +#define ORBIT_INTLK_REG_TRANS_MIN_Y 0x00000020 +/* [0x24]: REG Minimum angular X threshold */ +#define ORBIT_INTLK_REG_ANG_MIN_X 0x00000024 +/* [0x28]: REG Minimum angular Y threshold */ +#define ORBIT_INTLK_REG_ANG_MIN_Y 0x00000028 #endif diff --git a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.vhd b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.vhd index 9e92a42c..9b5f260f 100644 --- a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.vhd +++ b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.vhd @@ -3,7 +3,7 @@ --------------------------------------------------------------------------------------- -- File : wb_orbit_intlk_regs.vhd -- Author : auto-generated by wbgen2 from wb_orbit_intlk_regs.wb --- Created : Thu Jun 18 16:34:13 2020 +-- Created : Fri Aug 21 17:24:04 2020 -- Standard : VHDL'87 --------------------------------------------------------------------------------------- -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_orbit_intlk_regs.wb @@ -21,7 +21,7 @@ entity wb_orbit_intlk_regs is port ( rst_n_i : in std_logic; clk_sys_i : in std_logic; - wb_adr_i : in std_logic_vector(2 downto 0); + wb_adr_i : in std_logic_vector(3 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; @@ -29,6 +29,8 @@ entity wb_orbit_intlk_regs is wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; + wb_err_o : out std_logic; + wb_rty_o : out std_logic; wb_stall_o : out std_logic; fs_clk_i : in std_logic; regs_i : in t_orbit_intlk_in_registers; @@ -78,11 +80,35 @@ signal orbit_intlk_ang_max_y_swb_delay : std_logic ; signal orbit_intlk_ang_max_y_swb_s0 : std_logic ; signal orbit_intlk_ang_max_y_swb_s1 : std_logic ; signal orbit_intlk_ang_max_y_swb_s2 : std_logic ; +signal orbit_intlk_trans_min_x_int : std_logic_vector(31 downto 0); +signal orbit_intlk_trans_min_x_swb : std_logic ; +signal orbit_intlk_trans_min_x_swb_delay : std_logic ; +signal orbit_intlk_trans_min_x_swb_s0 : std_logic ; +signal orbit_intlk_trans_min_x_swb_s1 : std_logic ; +signal orbit_intlk_trans_min_x_swb_s2 : std_logic ; +signal orbit_intlk_trans_min_y_int : std_logic_vector(31 downto 0); +signal orbit_intlk_trans_min_y_swb : std_logic ; +signal orbit_intlk_trans_min_y_swb_delay : std_logic ; +signal orbit_intlk_trans_min_y_swb_s0 : std_logic ; +signal orbit_intlk_trans_min_y_swb_s1 : std_logic ; +signal orbit_intlk_trans_min_y_swb_s2 : std_logic ; +signal orbit_intlk_ang_min_x_int : std_logic_vector(31 downto 0); +signal orbit_intlk_ang_min_x_swb : std_logic ; +signal orbit_intlk_ang_min_x_swb_delay : std_logic ; +signal orbit_intlk_ang_min_x_swb_s0 : std_logic ; +signal orbit_intlk_ang_min_x_swb_s1 : std_logic ; +signal orbit_intlk_ang_min_x_swb_s2 : std_logic ; +signal orbit_intlk_ang_min_y_int : std_logic_vector(31 downto 0); +signal orbit_intlk_ang_min_y_swb : std_logic ; +signal orbit_intlk_ang_min_y_swb_delay : std_logic ; +signal orbit_intlk_ang_min_y_swb_s0 : std_logic ; +signal orbit_intlk_ang_min_y_swb_s1 : std_logic ; +signal orbit_intlk_ang_min_y_swb_s2 : std_logic ; signal ack_sreg : std_logic_vector(9 downto 0); signal rddata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0); signal bwsel_reg : std_logic_vector(3 downto 0); -signal rwaddr_reg : std_logic_vector(2 downto 0); +signal rwaddr_reg : std_logic_vector(3 downto 0); signal ack_in_progress : std_logic ; signal wr_int : std_logic ; signal rd_int : std_logic ; @@ -90,13 +116,8 @@ signal allones : std_logic_vector(31 downto 0); signal allzeros : std_logic_vector(31 downto 0); begin --- Some internal signals assignments. For (foreseen) compatibility with other bus standards. +-- Some internal signals assignments wrdata_reg <= wb_dat_i; - bwsel_reg <= wb_sel_i; - rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i)); - wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i); - allones <= (others => '1'); - allzeros <= (others => '0'); -- -- Main register bank access process. process (clk_sys_i, rst_n_i) @@ -127,6 +148,18 @@ begin orbit_intlk_ang_max_y_int <= "00000000000000000000000000000000"; orbit_intlk_ang_max_y_swb <= '0'; orbit_intlk_ang_max_y_swb_delay <= '0'; + orbit_intlk_trans_min_x_int <= "00000000000000000000000000000000"; + orbit_intlk_trans_min_x_swb <= '0'; + orbit_intlk_trans_min_x_swb_delay <= '0'; + orbit_intlk_trans_min_y_int <= "00000000000000000000000000000000"; + orbit_intlk_trans_min_y_swb <= '0'; + orbit_intlk_trans_min_y_swb_delay <= '0'; + orbit_intlk_ang_min_x_int <= "00000000000000000000000000000000"; + orbit_intlk_ang_min_x_swb <= '0'; + orbit_intlk_ang_min_x_swb_delay <= '0'; + orbit_intlk_ang_min_y_int <= "00000000000000000000000000000000"; + orbit_intlk_ang_min_y_swb <= '0'; + orbit_intlk_ang_min_y_swb_delay <= '0'; elsif rising_edge(clk_sys_i) then -- advance the ACK generator shift register ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); @@ -148,11 +181,19 @@ begin orbit_intlk_ang_max_x_swb_delay <= '0'; orbit_intlk_ang_max_y_swb <= orbit_intlk_ang_max_y_swb_delay; orbit_intlk_ang_max_y_swb_delay <= '0'; + orbit_intlk_trans_min_x_swb <= orbit_intlk_trans_min_x_swb_delay; + orbit_intlk_trans_min_x_swb_delay <= '0'; + orbit_intlk_trans_min_y_swb <= orbit_intlk_trans_min_y_swb_delay; + orbit_intlk_trans_min_y_swb_delay <= '0'; + orbit_intlk_ang_min_x_swb <= orbit_intlk_ang_min_x_swb_delay; + orbit_intlk_ang_min_x_swb_delay <= '0'; + orbit_intlk_ang_min_y_swb <= orbit_intlk_ang_min_y_swb_delay; + orbit_intlk_ang_min_y_swb_delay <= '0'; end if; else if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then - case rwaddr_reg(2 downto 0) is - when "000" => + case rwaddr_reg(3 downto 0) is + when "0000" => if (wb_we_i = '1') then orbit_intlk_ctrl_en_int <= wrdata_reg(0); orbit_intlk_ctrl_clr_int <= wrdata_reg(1); @@ -173,7 +214,7 @@ begin rddata_reg(31) <= 'X'; ack_sreg(2) <= '1'; ack_in_progress <= '1'; - when "001" => + when "0001" => if (wb_we_i = '1') then end if; rddata_reg(0) <= regs_i.sts_trans_bigger_x_i; @@ -190,12 +231,26 @@ begin rddata_reg(11) <= regs_i.sts_ang_bigger_any_i; rddata_reg(12) <= regs_i.sts_ang_bigger_i; rddata_reg(13) <= regs_i.sts_ang_bigger_ltc_i; - rddata_reg(14) <= regs_i.sts_intlk_bigger_i; - rddata_reg(15) <= regs_i.sts_intlk_bigger_ltc_i; - rddata_reg(31 downto 16) <= regs_i.sts_reserved_i; + rddata_reg(14) <= regs_i.sts_intlk_i; + rddata_reg(15) <= regs_i.sts_intlk_ltc_i; + rddata_reg(16) <= regs_i.sts_trans_smaller_x_i; + rddata_reg(17) <= regs_i.sts_trans_smaller_y_i; + rddata_reg(18) <= regs_i.sts_trans_smaller_ltc_x_i; + rddata_reg(19) <= regs_i.sts_trans_smaller_ltc_y_i; + rddata_reg(20) <= regs_i.sts_trans_smaller_any_i; + rddata_reg(21) <= regs_i.sts_trans_smaller_i; + rddata_reg(22) <= regs_i.sts_trans_smaller_ltc_i; + rddata_reg(23) <= regs_i.sts_ang_smaller_x_i; + rddata_reg(24) <= regs_i.sts_ang_smaller_y_i; + rddata_reg(25) <= regs_i.sts_ang_smaller_ltc_x_i; + rddata_reg(26) <= regs_i.sts_ang_smaller_ltc_y_i; + rddata_reg(27) <= regs_i.sts_ang_smaller_any_i; + rddata_reg(28) <= regs_i.sts_ang_smaller_i; + rddata_reg(29) <= regs_i.sts_ang_smaller_ltc_i; + rddata_reg(31 downto 30) <= regs_i.sts_reserved_i; ack_sreg(0) <= '1'; ack_in_progress <= '1'; - when "010" => + when "0010" => if (wb_we_i = '1') then orbit_intlk_min_sum_int <= wrdata_reg(31 downto 0); orbit_intlk_min_sum_swb <= '1'; @@ -204,7 +259,7 @@ begin rddata_reg(31 downto 0) <= orbit_intlk_min_sum_int; ack_sreg(3) <= '1'; ack_in_progress <= '1'; - when "011" => + when "0011" => if (wb_we_i = '1') then orbit_intlk_trans_max_x_int <= wrdata_reg(31 downto 0); orbit_intlk_trans_max_x_swb <= '1'; @@ -213,7 +268,7 @@ begin rddata_reg(31 downto 0) <= orbit_intlk_trans_max_x_int; ack_sreg(3) <= '1'; ack_in_progress <= '1'; - when "100" => + when "0100" => if (wb_we_i = '1') then orbit_intlk_trans_max_y_int <= wrdata_reg(31 downto 0); orbit_intlk_trans_max_y_swb <= '1'; @@ -222,7 +277,7 @@ begin rddata_reg(31 downto 0) <= orbit_intlk_trans_max_y_int; ack_sreg(3) <= '1'; ack_in_progress <= '1'; - when "101" => + when "0101" => if (wb_we_i = '1') then orbit_intlk_ang_max_x_int <= wrdata_reg(31 downto 0); orbit_intlk_ang_max_x_swb <= '1'; @@ -231,7 +286,7 @@ begin rddata_reg(31 downto 0) <= orbit_intlk_ang_max_x_int; ack_sreg(3) <= '1'; ack_in_progress <= '1'; - when "110" => + when "0110" => if (wb_we_i = '1') then orbit_intlk_ang_max_y_int <= wrdata_reg(31 downto 0); orbit_intlk_ang_max_y_swb <= '1'; @@ -240,6 +295,42 @@ begin rddata_reg(31 downto 0) <= orbit_intlk_ang_max_y_int; ack_sreg(3) <= '1'; ack_in_progress <= '1'; + when "0111" => + if (wb_we_i = '1') then + orbit_intlk_trans_min_x_int <= wrdata_reg(31 downto 0); + orbit_intlk_trans_min_x_swb <= '1'; + orbit_intlk_trans_min_x_swb_delay <= '1'; + end if; + rddata_reg(31 downto 0) <= orbit_intlk_trans_min_x_int; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1000" => + if (wb_we_i = '1') then + orbit_intlk_trans_min_y_int <= wrdata_reg(31 downto 0); + orbit_intlk_trans_min_y_swb <= '1'; + orbit_intlk_trans_min_y_swb_delay <= '1'; + end if; + rddata_reg(31 downto 0) <= orbit_intlk_trans_min_y_int; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1001" => + if (wb_we_i = '1') then + orbit_intlk_ang_min_x_int <= wrdata_reg(31 downto 0); + orbit_intlk_ang_min_x_swb <= '1'; + orbit_intlk_ang_min_x_swb_delay <= '1'; + end if; + rddata_reg(31 downto 0) <= orbit_intlk_ang_min_x_int; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1010" => + if (wb_we_i = '1') then + orbit_intlk_ang_min_y_int <= wrdata_reg(31 downto 0); + orbit_intlk_ang_min_y_swb <= '1'; + orbit_intlk_ang_min_y_swb_delay <= '1'; + end if; + rddata_reg(31 downto 0) <= orbit_intlk_ang_min_y_int; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; when others => -- prevent the slave from hanging the bus on invalid address ack_in_progress <= '1'; @@ -315,8 +406,22 @@ begin -- Angular Bigger Any (X/Y) -- Angular Bigger -- Angular Bigger Latched --- Interlock Bigger --- Interlock Bigger Latched +-- Interlock Trip +-- Interlock Trip Latched +-- Translation Smaller X +-- Translation Smaller Y +-- Translation Smaller Latched X +-- Translation Smaller Latched Y +-- Translation Smaller Any (X/Y) +-- Translation Smaller +-- Translation Smaller Latched +-- Angular Smaller X +-- Angular Smaller Y +-- Angular Smaller Latched X +-- Angular Smaller Latched Y +-- Angular Smaller Any (X/Y) +-- Angular Smaller +-- Angular Smaller Latched -- Reserved -- Minimum Sum Threshold -- asynchronous std_logic_vector register : Minimum Sum Threshold (type RW/RO, fs_clk_i <-> clk_sys_i) @@ -418,8 +523,90 @@ begin end process; +-- Minimum X Threshold +-- asynchronous std_logic_vector register : Minimum X Threshold (type RW/RO, fs_clk_i <-> clk_sys_i) + process (fs_clk_i, rst_n_i) + begin + if (rst_n_i = '0') then + orbit_intlk_trans_min_x_swb_s0 <= '0'; + orbit_intlk_trans_min_x_swb_s1 <= '0'; + orbit_intlk_trans_min_x_swb_s2 <= '0'; + regs_o.trans_min_x_o <= "00000000000000000000000000000000"; + elsif rising_edge(fs_clk_i) then + orbit_intlk_trans_min_x_swb_s0 <= orbit_intlk_trans_min_x_swb; + orbit_intlk_trans_min_x_swb_s1 <= orbit_intlk_trans_min_x_swb_s0; + orbit_intlk_trans_min_x_swb_s2 <= orbit_intlk_trans_min_x_swb_s1; + if ((orbit_intlk_trans_min_x_swb_s2 = '0') and (orbit_intlk_trans_min_x_swb_s1 = '1')) then + regs_o.trans_min_x_o <= orbit_intlk_trans_min_x_int; + end if; + end if; + end process; + + +-- Minimum Y Threshold +-- asynchronous std_logic_vector register : Minimum Y Threshold (type RW/RO, fs_clk_i <-> clk_sys_i) + process (fs_clk_i, rst_n_i) + begin + if (rst_n_i = '0') then + orbit_intlk_trans_min_y_swb_s0 <= '0'; + orbit_intlk_trans_min_y_swb_s1 <= '0'; + orbit_intlk_trans_min_y_swb_s2 <= '0'; + regs_o.trans_min_y_o <= "00000000000000000000000000000000"; + elsif rising_edge(fs_clk_i) then + orbit_intlk_trans_min_y_swb_s0 <= orbit_intlk_trans_min_y_swb; + orbit_intlk_trans_min_y_swb_s1 <= orbit_intlk_trans_min_y_swb_s0; + orbit_intlk_trans_min_y_swb_s2 <= orbit_intlk_trans_min_y_swb_s1; + if ((orbit_intlk_trans_min_y_swb_s2 = '0') and (orbit_intlk_trans_min_y_swb_s1 = '1')) then + regs_o.trans_min_y_o <= orbit_intlk_trans_min_y_int; + end if; + end if; + end process; + + +-- Minimum X Threshold +-- asynchronous std_logic_vector register : Minimum X Threshold (type RW/RO, fs_clk_i <-> clk_sys_i) + process (fs_clk_i, rst_n_i) + begin + if (rst_n_i = '0') then + orbit_intlk_ang_min_x_swb_s0 <= '0'; + orbit_intlk_ang_min_x_swb_s1 <= '0'; + orbit_intlk_ang_min_x_swb_s2 <= '0'; + regs_o.ang_min_x_o <= "00000000000000000000000000000000"; + elsif rising_edge(fs_clk_i) then + orbit_intlk_ang_min_x_swb_s0 <= orbit_intlk_ang_min_x_swb; + orbit_intlk_ang_min_x_swb_s1 <= orbit_intlk_ang_min_x_swb_s0; + orbit_intlk_ang_min_x_swb_s2 <= orbit_intlk_ang_min_x_swb_s1; + if ((orbit_intlk_ang_min_x_swb_s2 = '0') and (orbit_intlk_ang_min_x_swb_s1 = '1')) then + regs_o.ang_min_x_o <= orbit_intlk_ang_min_x_int; + end if; + end if; + end process; + + +-- Minimum Y Threshold +-- asynchronous std_logic_vector register : Minimum Y Threshold (type RW/RO, fs_clk_i <-> clk_sys_i) + process (fs_clk_i, rst_n_i) + begin + if (rst_n_i = '0') then + orbit_intlk_ang_min_y_swb_s0 <= '0'; + orbit_intlk_ang_min_y_swb_s1 <= '0'; + orbit_intlk_ang_min_y_swb_s2 <= '0'; + regs_o.ang_min_y_o <= "00000000000000000000000000000000"; + elsif rising_edge(fs_clk_i) then + orbit_intlk_ang_min_y_swb_s0 <= orbit_intlk_ang_min_y_swb; + orbit_intlk_ang_min_y_swb_s1 <= orbit_intlk_ang_min_y_swb_s0; + orbit_intlk_ang_min_y_swb_s2 <= orbit_intlk_ang_min_y_swb_s1; + if ((orbit_intlk_ang_min_y_swb_s2 = '0') and (orbit_intlk_ang_min_y_swb_s1 = '1')) then + regs_o.ang_min_y_o <= orbit_intlk_ang_min_y_int; + end if; + end if; + end process; + + rwaddr_reg <= wb_adr_i; wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); + wb_err_o <= '0'; + wb_rty_o <= '0'; -- ACK signal generation. Just pass the LSB of ACK counter. wb_ack_o <= ack_sreg(0); end syn; diff --git a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.wb b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.wb index d983adaf..9427a1e5 100644 --- a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.wb +++ b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.wb @@ -217,18 +217,144 @@ peripheral { }; field { - name = "Interlock Bigger"; - description = "Interlock Bigger"; - prefix = "intlk_bigger"; + name = "Interlock Trip"; + description = "Interlock Trip"; + prefix = "intlk"; type = BIT; access_bus = READ_ONLY; access_dev = WRITE_ONLY; }; field { - name = "Interlock Bigger Latched"; - description = "Interlock Bigger Latched"; - prefix = "intlk_bigger_ltc"; + name = "Interlock Trip Latched"; + description = "Interlock Trip Latched"; + prefix = "intlk_ltc"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Translation Smaller X"; + description = "Translation Smaller X"; + prefix = "trans_smaller_x"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Translation Smaller Y"; + description = "Translation Smaller Y"; + prefix = "trans_smaller_y"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Translation Smaller Latched X"; + description = "Translation Smaller Latched X"; + prefix = "trans_smaller_ltc_x"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Translation Smaller Latched Y"; + description = "Translation Smaller Latched Y"; + prefix = "trans_smaller_ltc_y"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Translation Smaller Any (X/Y)"; + description = "Translation Smaller Any (X/Y)"; + prefix = "trans_smaller_any"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Translation Smaller"; + description = "Translation Smaller"; + prefix = "trans_smaller"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Translation Smaller Latched"; + description = "Translation Smaller Latched"; + prefix = "trans_smaller_ltc"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Angular Smaller X"; + description = "Angular Smaller X"; + prefix = "ang_smaller_x"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Angular Smaller Y"; + description = "Angular Smaller Y"; + prefix = "ang_smaller_y"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Angular Smaller Latched X"; + description = "Angular Smaller Latched X"; + prefix = "ang_smaller_ltc_x"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Angular Smaller Latched Y"; + description = "Angular Smaller Latched Y"; + prefix = "ang_smaller_ltc_y"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Angular Smaller Any (X/Y)"; + description = "Angular Smaller Any (X/Y)"; + prefix = "ang_smaller_any"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Angular Smaller"; + description = "Angular Smaller"; + prefix = "ang_smaller"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + + field { + name = "Angular Smaller Latched"; + description = "Angular Smaller Latched"; + prefix = "ang_smaller_ltc"; type = BIT; access_bus = READ_ONLY; access_dev = WRITE_ONLY; @@ -239,7 +365,7 @@ peripheral { description = "Ignore on write, read as 0's"; prefix = "reserved"; type = SLV; - size = 16; + size = 2; access_bus = READ_ONLY; access_dev = WRITE_ONLY; }; @@ -262,13 +388,13 @@ peripheral { }; reg { - name = "Translation X threshold"; - description = "Translation X threshold to trip interlock"; + name = "Maximum translation X threshold"; + description = "Maximum translation X threshold to trip interlock"; prefix = "trans_max_x"; field { name = "Maximum X Threshold"; - description = "Minimum X Threshold"; + description = "Maximum X Threshold"; type = SLV; size = 32; access_bus = READ_WRITE; @@ -278,8 +404,8 @@ peripheral { }; reg { - name = "Translation Y threshold"; - description = "Translation Y threshold to trip interlock"; + name = "Maximum translation Y threshold"; + description = "Maximum translation Y threshold to trip interlock"; prefix = "trans_max_y"; field { @@ -294,8 +420,8 @@ peripheral { }; reg { - name = "Angular X threshold"; - description = "Angular X threshold to trip interlock"; + name = "Maximum angular X threshold"; + description = "Maximum angular X threshold to trip interlock"; prefix = "ang_max_x"; field { @@ -310,8 +436,8 @@ peripheral { }; reg { - name = "Angular Y threshold"; - description = "Angular Y threshold to trip interlock"; + name = "Maximum angular Y threshold"; + description = "Maximum angular Y threshold to trip interlock"; prefix = "ang_max_y"; field { @@ -325,4 +451,68 @@ peripheral { }; }; + reg { + name = "Minimum translation X threshold"; + description = "Minimum translation X threshold to trip interlock"; + prefix = "trans_min_x"; + + field { + name = "Minimum X Threshold"; + description = "Minimum X Threshold"; + type = SLV; + size = 32; + access_bus = READ_WRITE; + access_dev = READ_ONLY; + clock = "fs_clk_i"; + }; + }; + + reg { + name = "Minimum translation Y threshold"; + description = "Minimum translation Y threshold to trip interlock"; + prefix = "trans_min_y"; + + field { + name = "Minimum Y Threshold"; + description = "Minimum Y Threshold"; + type = SLV; + size = 32; + access_bus = READ_WRITE; + access_dev = READ_ONLY; + clock = "fs_clk_i"; + }; + }; + + reg { + name = "Minimum angular X threshold"; + description = "Minimum angular X threshold to trip interlock"; + prefix = "ang_min_x"; + + field { + name = "Minimum X Threshold"; + description = "Minimum X Threshold"; + type = SLV; + size = 32; + access_bus = READ_WRITE; + access_dev = READ_ONLY; + clock = "fs_clk_i"; + }; + }; + + reg { + name = "Minimum angular Y threshold"; + description = "Minimum angular Y threshold to trip interlock"; + prefix = "ang_min_y"; + + field { + name = "Minimum Y Threshold"; + description = "Minimum Y Threshold"; + type = SLV; + size = 32; + access_bus = READ_WRITE; + access_dev = READ_ONLY; + clock = "fs_clk_i"; + }; + }; + }; diff --git a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs_pkg.vhd b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs_pkg.vhd index 0c266e4d..d341cc8f 100644 --- a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs_pkg.vhd +++ b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs_pkg.vhd @@ -3,7 +3,7 @@ --------------------------------------------------------------------------------------- -- File : wb_orbit_intlk_regs_pkg.vhd -- Author : auto-generated by wbgen2 from wb_orbit_intlk_regs.wb --- Created : Thu Jun 18 16:34:13 2020 +-- Created : Fri Aug 21 17:24:04 2020 -- Standard : VHDL'87 --------------------------------------------------------------------------------------- -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_orbit_intlk_regs.wb @@ -35,10 +35,24 @@ package orbit_intlk_wbgen2_pkg is sts_ang_bigger_any_i : std_logic; sts_ang_bigger_i : std_logic; sts_ang_bigger_ltc_i : std_logic; - sts_intlk_bigger_i : std_logic; - sts_intlk_bigger_ltc_i : std_logic; - sts_reserved_i : std_logic_vector(15 downto 0); - end record; + sts_intlk_i : std_logic; + sts_intlk_ltc_i : std_logic; + sts_trans_smaller_x_i : std_logic; + sts_trans_smaller_y_i : std_logic; + sts_trans_smaller_ltc_x_i : std_logic; + sts_trans_smaller_ltc_y_i : std_logic; + sts_trans_smaller_any_i : std_logic; + sts_trans_smaller_i : std_logic; + sts_trans_smaller_ltc_i : std_logic; + sts_ang_smaller_x_i : std_logic; + sts_ang_smaller_y_i : std_logic; + sts_ang_smaller_ltc_x_i : std_logic; + sts_ang_smaller_ltc_y_i : std_logic; + sts_ang_smaller_any_i : std_logic; + sts_ang_smaller_i : std_logic; + sts_ang_smaller_ltc_i : std_logic; + sts_reserved_i : std_logic_vector(1 downto 0); + end record; constant c_orbit_intlk_in_registers_init_value: t_orbit_intlk_in_registers := ( ctrl_reserved_i => (others => '0'), @@ -56,89 +70,151 @@ package orbit_intlk_wbgen2_pkg is sts_ang_bigger_any_i => '0', sts_ang_bigger_i => '0', sts_ang_bigger_ltc_i => '0', - sts_intlk_bigger_i => '0', - sts_intlk_bigger_ltc_i => '0', + sts_intlk_i => '0', + sts_intlk_ltc_i => '0', + sts_trans_smaller_x_i => '0', + sts_trans_smaller_y_i => '0', + sts_trans_smaller_ltc_x_i => '0', + sts_trans_smaller_ltc_y_i => '0', + sts_trans_smaller_any_i => '0', + sts_trans_smaller_i => '0', + sts_trans_smaller_ltc_i => '0', + sts_ang_smaller_x_i => '0', + sts_ang_smaller_y_i => '0', + sts_ang_smaller_ltc_x_i => '0', + sts_ang_smaller_ltc_y_i => '0', + sts_ang_smaller_any_i => '0', + sts_ang_smaller_i => '0', + sts_ang_smaller_ltc_i => '0', sts_reserved_i => (others => '0') + ); + + -- Output registers (WB slave -> user design) + + type t_orbit_intlk_out_registers is record + ctrl_en_o : std_logic; + ctrl_clr_o : std_logic; + ctrl_min_sum_en_o : std_logic; + ctrl_trans_en_o : std_logic; + ctrl_trans_clr_o : std_logic; + ctrl_ang_en_o : std_logic; + ctrl_ang_clr_o : std_logic; + min_sum_o : std_logic_vector(31 downto 0); + trans_max_x_o : std_logic_vector(31 downto 0); + trans_max_y_o : std_logic_vector(31 downto 0); + ang_max_x_o : std_logic_vector(31 downto 0); + ang_max_y_o : std_logic_vector(31 downto 0); + trans_min_x_o : std_logic_vector(31 downto 0); + trans_min_y_o : std_logic_vector(31 downto 0); + ang_min_x_o : std_logic_vector(31 downto 0); + ang_min_y_o : std_logic_vector(31 downto 0); + end record; + + constant c_orbit_intlk_out_registers_init_value: t_orbit_intlk_out_registers := ( + ctrl_en_o => '0', + ctrl_clr_o => '0', + ctrl_min_sum_en_o => '0', + ctrl_trans_en_o => '0', + ctrl_trans_clr_o => '0', + ctrl_ang_en_o => '0', + ctrl_ang_clr_o => '0', + min_sum_o => (others => '0'), + trans_max_x_o => (others => '0'), + trans_max_y_o => (others => '0'), + ang_max_x_o => (others => '0'), + ang_max_y_o => (others => '0'), + trans_min_x_o => (others => '0'), + trans_min_y_o => (others => '0'), + ang_min_x_o => (others => '0'), + ang_min_y_o => (others => '0') + ); + + function "or" (left, right: t_orbit_intlk_in_registers) return t_orbit_intlk_in_registers; + function f_x_to_zero (x:std_logic) return std_logic; + function f_x_to_zero (x:std_logic_vector) return std_logic_vector; + + component wb_orbit_intlk_regs is + port ( + rst_n_i : in std_logic; + clk_sys_i : in std_logic; + wb_adr_i : in std_logic_vector(3 downto 0); + wb_dat_i : in std_logic_vector(31 downto 0); + wb_dat_o : out std_logic_vector(31 downto 0); + wb_cyc_i : in std_logic; + wb_sel_i : in std_logic_vector(3 downto 0); + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_ack_o : out std_logic; + wb_err_o : out std_logic; + wb_rty_o : out std_logic; + wb_stall_o : out std_logic; + fs_clk_i : in std_logic; + regs_i : in t_orbit_intlk_in_registers; + regs_o : out t_orbit_intlk_out_registers ); - - -- Output registers (WB slave -> user design) - - type t_orbit_intlk_out_registers is record - ctrl_en_o : std_logic; - ctrl_clr_o : std_logic; - ctrl_min_sum_en_o : std_logic; - ctrl_trans_en_o : std_logic; - ctrl_trans_clr_o : std_logic; - ctrl_ang_en_o : std_logic; - ctrl_ang_clr_o : std_logic; - min_sum_o : std_logic_vector(31 downto 0); - trans_max_x_o : std_logic_vector(31 downto 0); - trans_max_y_o : std_logic_vector(31 downto 0); - ang_max_x_o : std_logic_vector(31 downto 0); - ang_max_y_o : std_logic_vector(31 downto 0); - end record; - - constant c_orbit_intlk_out_registers_init_value: t_orbit_intlk_out_registers := ( - ctrl_en_o => '0', - ctrl_clr_o => '0', - ctrl_min_sum_en_o => '0', - ctrl_trans_en_o => '0', - ctrl_trans_clr_o => '0', - ctrl_ang_en_o => '0', - ctrl_ang_clr_o => '0', - min_sum_o => (others => '0'), - trans_max_x_o => (others => '0'), - trans_max_y_o => (others => '0'), - ang_max_x_o => (others => '0'), - ang_max_y_o => (others => '0') - ); - function "or" (left, right: t_orbit_intlk_in_registers) return t_orbit_intlk_in_registers; - function f_x_to_zero (x:std_logic) return std_logic; - function f_x_to_zero (x:std_logic_vector) return std_logic_vector; + end component; + end package; package body orbit_intlk_wbgen2_pkg is -function f_x_to_zero (x:std_logic) return std_logic is -begin -if x = '1' then -return '1'; -else -return '0'; -end if; -end function; -function f_x_to_zero (x:std_logic_vector) return std_logic_vector is -variable tmp: std_logic_vector(x'length-1 downto 0); -begin -for i in 0 to x'length-1 loop -if(x(i) = 'X' or x(i) = 'U') then -tmp(i):= '0'; -else -tmp(i):=x(i); -end if; -end loop; -return tmp; -end function; -function "or" (left, right: t_orbit_intlk_in_registers) return t_orbit_intlk_in_registers is -variable tmp: t_orbit_intlk_in_registers; -begin -tmp.ctrl_reserved_i := f_x_to_zero(left.ctrl_reserved_i) or f_x_to_zero(right.ctrl_reserved_i); -tmp.sts_trans_bigger_x_i := f_x_to_zero(left.sts_trans_bigger_x_i) or f_x_to_zero(right.sts_trans_bigger_x_i); -tmp.sts_trans_bigger_y_i := f_x_to_zero(left.sts_trans_bigger_y_i) or f_x_to_zero(right.sts_trans_bigger_y_i); -tmp.sts_trans_bigger_ltc_x_i := f_x_to_zero(left.sts_trans_bigger_ltc_x_i) or f_x_to_zero(right.sts_trans_bigger_ltc_x_i); -tmp.sts_trans_bigger_ltc_y_i := f_x_to_zero(left.sts_trans_bigger_ltc_y_i) or f_x_to_zero(right.sts_trans_bigger_ltc_y_i); -tmp.sts_trans_bigger_any_i := f_x_to_zero(left.sts_trans_bigger_any_i) or f_x_to_zero(right.sts_trans_bigger_any_i); -tmp.sts_trans_bigger_i := f_x_to_zero(left.sts_trans_bigger_i) or f_x_to_zero(right.sts_trans_bigger_i); -tmp.sts_trans_bigger_ltc_i := f_x_to_zero(left.sts_trans_bigger_ltc_i) or f_x_to_zero(right.sts_trans_bigger_ltc_i); -tmp.sts_ang_bigger_x_i := f_x_to_zero(left.sts_ang_bigger_x_i) or f_x_to_zero(right.sts_ang_bigger_x_i); -tmp.sts_ang_bigger_y_i := f_x_to_zero(left.sts_ang_bigger_y_i) or f_x_to_zero(right.sts_ang_bigger_y_i); -tmp.sts_ang_bigger_ltc_x_i := f_x_to_zero(left.sts_ang_bigger_ltc_x_i) or f_x_to_zero(right.sts_ang_bigger_ltc_x_i); -tmp.sts_ang_bigger_ltc_y_i := f_x_to_zero(left.sts_ang_bigger_ltc_y_i) or f_x_to_zero(right.sts_ang_bigger_ltc_y_i); -tmp.sts_ang_bigger_any_i := f_x_to_zero(left.sts_ang_bigger_any_i) or f_x_to_zero(right.sts_ang_bigger_any_i); -tmp.sts_ang_bigger_i := f_x_to_zero(left.sts_ang_bigger_i) or f_x_to_zero(right.sts_ang_bigger_i); -tmp.sts_ang_bigger_ltc_i := f_x_to_zero(left.sts_ang_bigger_ltc_i) or f_x_to_zero(right.sts_ang_bigger_ltc_i); -tmp.sts_intlk_bigger_i := f_x_to_zero(left.sts_intlk_bigger_i) or f_x_to_zero(right.sts_intlk_bigger_i); -tmp.sts_intlk_bigger_ltc_i := f_x_to_zero(left.sts_intlk_bigger_ltc_i) or f_x_to_zero(right.sts_intlk_bigger_ltc_i); -tmp.sts_reserved_i := f_x_to_zero(left.sts_reserved_i) or f_x_to_zero(right.sts_reserved_i); -return tmp; -end function; + function f_x_to_zero (x:std_logic) return std_logic is + begin + if x = '1' then + return '1'; + else + return '0'; + end if; + end function; + + function f_x_to_zero (x:std_logic_vector) return std_logic_vector is + variable tmp: std_logic_vector(x'length-1 downto 0); + begin + for i in 0 to x'length-1 loop + if(x(i) = '1') then + tmp(i):= '1'; + else + tmp(i):= '0'; + end if; + end loop; + return tmp; + end function; + + function "or" (left, right: t_orbit_intlk_in_registers) return t_orbit_intlk_in_registers is + variable tmp: t_orbit_intlk_in_registers; + begin + tmp.ctrl_reserved_i := f_x_to_zero(left.ctrl_reserved_i) or f_x_to_zero(right.ctrl_reserved_i); + tmp.sts_trans_bigger_x_i := f_x_to_zero(left.sts_trans_bigger_x_i) or f_x_to_zero(right.sts_trans_bigger_x_i); + tmp.sts_trans_bigger_y_i := f_x_to_zero(left.sts_trans_bigger_y_i) or f_x_to_zero(right.sts_trans_bigger_y_i); + tmp.sts_trans_bigger_ltc_x_i := f_x_to_zero(left.sts_trans_bigger_ltc_x_i) or f_x_to_zero(right.sts_trans_bigger_ltc_x_i); + tmp.sts_trans_bigger_ltc_y_i := f_x_to_zero(left.sts_trans_bigger_ltc_y_i) or f_x_to_zero(right.sts_trans_bigger_ltc_y_i); + tmp.sts_trans_bigger_any_i := f_x_to_zero(left.sts_trans_bigger_any_i) or f_x_to_zero(right.sts_trans_bigger_any_i); + tmp.sts_trans_bigger_i := f_x_to_zero(left.sts_trans_bigger_i) or f_x_to_zero(right.sts_trans_bigger_i); + tmp.sts_trans_bigger_ltc_i := f_x_to_zero(left.sts_trans_bigger_ltc_i) or f_x_to_zero(right.sts_trans_bigger_ltc_i); + tmp.sts_ang_bigger_x_i := f_x_to_zero(left.sts_ang_bigger_x_i) or f_x_to_zero(right.sts_ang_bigger_x_i); + tmp.sts_ang_bigger_y_i := f_x_to_zero(left.sts_ang_bigger_y_i) or f_x_to_zero(right.sts_ang_bigger_y_i); + tmp.sts_ang_bigger_ltc_x_i := f_x_to_zero(left.sts_ang_bigger_ltc_x_i) or f_x_to_zero(right.sts_ang_bigger_ltc_x_i); + tmp.sts_ang_bigger_ltc_y_i := f_x_to_zero(left.sts_ang_bigger_ltc_y_i) or f_x_to_zero(right.sts_ang_bigger_ltc_y_i); + tmp.sts_ang_bigger_any_i := f_x_to_zero(left.sts_ang_bigger_any_i) or f_x_to_zero(right.sts_ang_bigger_any_i); + tmp.sts_ang_bigger_i := f_x_to_zero(left.sts_ang_bigger_i) or f_x_to_zero(right.sts_ang_bigger_i); + tmp.sts_ang_bigger_ltc_i := f_x_to_zero(left.sts_ang_bigger_ltc_i) or f_x_to_zero(right.sts_ang_bigger_ltc_i); + tmp.sts_intlk_i := f_x_to_zero(left.sts_intlk_i) or f_x_to_zero(right.sts_intlk_i); + tmp.sts_intlk_ltc_i := f_x_to_zero(left.sts_intlk_ltc_i) or f_x_to_zero(right.sts_intlk_ltc_i); + tmp.sts_trans_smaller_x_i := f_x_to_zero(left.sts_trans_smaller_x_i) or f_x_to_zero(right.sts_trans_smaller_x_i); + tmp.sts_trans_smaller_y_i := f_x_to_zero(left.sts_trans_smaller_y_i) or f_x_to_zero(right.sts_trans_smaller_y_i); + tmp.sts_trans_smaller_ltc_x_i := f_x_to_zero(left.sts_trans_smaller_ltc_x_i) or f_x_to_zero(right.sts_trans_smaller_ltc_x_i); + tmp.sts_trans_smaller_ltc_y_i := f_x_to_zero(left.sts_trans_smaller_ltc_y_i) or f_x_to_zero(right.sts_trans_smaller_ltc_y_i); + tmp.sts_trans_smaller_any_i := f_x_to_zero(left.sts_trans_smaller_any_i) or f_x_to_zero(right.sts_trans_smaller_any_i); + tmp.sts_trans_smaller_i := f_x_to_zero(left.sts_trans_smaller_i) or f_x_to_zero(right.sts_trans_smaller_i); + tmp.sts_trans_smaller_ltc_i := f_x_to_zero(left.sts_trans_smaller_ltc_i) or f_x_to_zero(right.sts_trans_smaller_ltc_i); + tmp.sts_ang_smaller_x_i := f_x_to_zero(left.sts_ang_smaller_x_i) or f_x_to_zero(right.sts_ang_smaller_x_i); + tmp.sts_ang_smaller_y_i := f_x_to_zero(left.sts_ang_smaller_y_i) or f_x_to_zero(right.sts_ang_smaller_y_i); + tmp.sts_ang_smaller_ltc_x_i := f_x_to_zero(left.sts_ang_smaller_ltc_x_i) or f_x_to_zero(right.sts_ang_smaller_ltc_x_i); + tmp.sts_ang_smaller_ltc_y_i := f_x_to_zero(left.sts_ang_smaller_ltc_y_i) or f_x_to_zero(right.sts_ang_smaller_ltc_y_i); + tmp.sts_ang_smaller_any_i := f_x_to_zero(left.sts_ang_smaller_any_i) or f_x_to_zero(right.sts_ang_smaller_any_i); + tmp.sts_ang_smaller_i := f_x_to_zero(left.sts_ang_smaller_i) or f_x_to_zero(right.sts_ang_smaller_i); + tmp.sts_ang_smaller_ltc_i := f_x_to_zero(left.sts_ang_smaller_ltc_i) or f_x_to_zero(right.sts_ang_smaller_ltc_i); + tmp.sts_reserved_i := f_x_to_zero(left.sts_reserved_i) or f_x_to_zero(right.sts_reserved_i); + return tmp; + end function; + end package body; diff --git a/hdl/modules/wb_orbit_intlk/xwb_orbit_intlk.vhd b/hdl/modules/wb_orbit_intlk/xwb_orbit_intlk.vhd index fe8e5474..15594ae3 100644 --- a/hdl/modules/wb_orbit_intlk/xwb_orbit_intlk.vhd +++ b/hdl/modules/wb_orbit_intlk/xwb_orbit_intlk.vhd @@ -101,15 +101,30 @@ port intlk_trans_bigger_x_o : out std_logic; intlk_trans_bigger_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted intlk_trans_bigger_ltc_x_o : out std_logic; intlk_trans_bigger_ltc_y_o : out std_logic; + intlk_trans_bigger_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_bigger_ltc_o : out std_logic; + -- conditional to intlk_trans_en_i intlk_trans_bigger_o : out std_logic; + intlk_trans_smaller_x_o : out std_logic; + intlk_trans_smaller_y_o : out std_logic; + -- only cleared when intlk_trans_clr_i is asserted - intlk_trans_ltc_o : out std_logic; + intlk_trans_smaller_ltc_x_o : out std_logic; + intlk_trans_smaller_ltc_y_o : out std_logic; + + intlk_trans_smaller_any_o : out std_logic; + + -- only cleared when intlk_trans_clr_i is asserted + intlk_trans_smaller_ltc_o : out std_logic; -- conditional to intlk_trans_en_i - intlk_trans_o : out std_logic; + intlk_trans_smaller_o : out std_logic; intlk_ang_bigger_x_o : out std_logic; intlk_ang_bigger_y_o : out std_logic; @@ -117,12 +132,25 @@ port intlk_ang_bigger_ltc_x_o : out std_logic; intlk_ang_bigger_ltc_y_o : out std_logic; + intlk_ang_bigger_any_o : out std_logic; + + -- only cleared when intlk_ang_clr_i is asserted + intlk_ang_bigger_ltc_o : out std_logic; + -- conditional to intlk_ang_en_i intlk_ang_bigger_o : out std_logic; + intlk_ang_smaller_x_o : out std_logic; + intlk_ang_smaller_y_o : out std_logic; + + intlk_ang_smaller_ltc_x_o : out std_logic; + intlk_ang_smaller_ltc_y_o : out std_logic; + + intlk_ang_smaller_any_o : out std_logic; + -- only cleared when intlk_ang_clr_i is asserted - intlk_ang_ltc_o : out std_logic; + intlk_ang_smaller_ltc_o : out std_logic; -- conditional to intlk_ang_en_i - intlk_ang_o : out std_logic; + intlk_ang_smaller_o : out std_logic; -- only cleared when intlk_clr_i is asserted intlk_ltc_o : out std_logic; @@ -218,12 +246,21 @@ begin intlk_trans_bigger_ltc_x_o => intlk_trans_bigger_ltc_x_o, intlk_trans_bigger_ltc_y_o => intlk_trans_bigger_ltc_y_o, + intlk_trans_bigger_any_o => intlk_trans_bigger_any_o, + + intlk_trans_bigger_ltc_o => intlk_trans_bigger_ltc_o, intlk_trans_bigger_o => intlk_trans_bigger_o, - -- only cleared when intlk_trans_clr_i is - intlk_trans_ltc_o => intlk_trans_ltc_o, - -- conditional to intlk_trans_en_i - intlk_trans_o => intlk_trans_o, + intlk_trans_smaller_x_o => intlk_trans_smaller_x_o, + intlk_trans_smaller_y_o => intlk_trans_smaller_y_o, + + intlk_trans_smaller_ltc_x_o => intlk_trans_smaller_ltc_x_o, + intlk_trans_smaller_ltc_y_o => intlk_trans_smaller_ltc_y_o, + + intlk_trans_smaller_any_o => intlk_trans_smaller_any_o, + + intlk_trans_smaller_ltc_o => intlk_trans_smaller_ltc_o, + intlk_trans_smaller_o => intlk_trans_smaller_o, intlk_ang_bigger_x_o => intlk_ang_bigger_x_o, intlk_ang_bigger_y_o => intlk_ang_bigger_y_o, @@ -231,16 +268,23 @@ begin intlk_ang_bigger_ltc_x_o => intlk_ang_bigger_ltc_x_o, intlk_ang_bigger_ltc_y_o => intlk_ang_bigger_ltc_y_o, + intlk_ang_bigger_any_o => intlk_ang_bigger_any_o, + + intlk_ang_bigger_ltc_o => intlk_ang_bigger_ltc_o, intlk_ang_bigger_o => intlk_ang_bigger_o, - -- only cleared when intlk_ang_clr_i is as - intlk_ang_ltc_o => intlk_ang_ltc_o, - -- conditional to intlk_ang_en_i - intlk_ang_o => intlk_ang_o, + intlk_ang_smaller_x_o => intlk_ang_smaller_x_o, + intlk_ang_smaller_y_o => intlk_ang_smaller_y_o, + + intlk_ang_smaller_ltc_x_o => intlk_ang_smaller_ltc_x_o, + intlk_ang_smaller_ltc_y_o => intlk_ang_smaller_ltc_y_o, + + intlk_ang_smaller_any_o => intlk_ang_smaller_any_o, + + intlk_ang_smaller_ltc_o => intlk_ang_smaller_ltc_o, + intlk_ang_smaller_o => intlk_ang_smaller_o, - -- only cleared when intlk_clr_i is assert intlk_ltc_o => intlk_ltc_o, - -- conditional to intlk_en_i intlk_o => intlk_o ); diff --git a/hdl/modules/wb_position_calc/Manifest.py b/hdl/modules/wb_position_calc/Manifest.py index d522a14f..81440707 100755 --- a/hdl/modules/wb_position_calc/Manifest.py +++ b/hdl/modules/wb_position_calc/Manifest.py @@ -3,6 +3,5 @@ "position_calc_core_pkg.vhd", "position_calc_cdc_fifo.vhd", "trigger2tag.vhd", - "wbgen/wb_pos_calc_regs_pkg.vhd", - "wbgen/wb_pos_calc_regs.vhd" + "cheby/wb_pos_calc_regs.vhd" ] diff --git a/hdl/modules/wb_position_calc/cheby/build_cheby.sh b/hdl/modules/wb_position_calc/cheby/build_cheby.sh new file mode 100755 index 00000000..29d2118a --- /dev/null +++ b/hdl/modules/wb_position_calc/cheby/build_cheby.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +cheby -i wb_pos_calc_regs.cheby --hdl vhdl --gen-wbgen-hdl wb_pos_calc_regs.vhd --doc html --gen-doc doc/wb_pos_calc_regs_wb.html --gen-c wb_pos_calc_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_pos_calc_regs.vh diff --git a/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html new file mode 100644 index 00000000..193a61e3 --- /dev/null +++ b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html @@ -0,0 +1,6091 @@ + + +wb_pos_calc_regs + + + +

wb_pos_calc_regs

+

Position Calculation Core registers

+

Wishbone slave for Position Calculation Core

+

1. Memory map summary

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HW addressTypeNameHDL prefixC prefix
0x000REGds_tbt_thresds_tbt_thresds_tbt_thres
0x004REGds_fofb_thresds_fofb_thresds_fofb_thres
0x008REGds_monit_thresds_monit_thresds_monit_thres
0x00cREGkxkxkx
0x010REGkykyky
0x014REGksumksumksum
0x018REGdsp_ctnr_tbtdsp_ctnr_tbtdsp_ctnr_tbt
0x01cREGdsp_ctnr_fofbdsp_ctnr_fofbdsp_ctnr_fofb
0x020REGdsp_ctnr1_monitdsp_ctnr1_monitdsp_ctnr1_monit
0x024REGdsp_ctnr2_monitdsp_ctnr2_monitdsp_ctnr2_monit
0x028REGdsp_err_clrdsp_err_clrdsp_err_clr
0x02cREGdds_cfgdds_cfgdds_cfg
0x030REGdds_pinc_ch0dds_pinc_ch0dds_pinc_ch0
0x034REGdds_pinc_ch1dds_pinc_ch1dds_pinc_ch1
0x038REGdds_pinc_ch2dds_pinc_ch2dds_pinc_ch2
0x03cREGdds_pinc_ch3dds_pinc_ch3dds_pinc_ch3
0x040REGdds_poff_ch0dds_poff_ch0dds_poff_ch0
0x044REGdds_poff_ch1dds_poff_ch1dds_poff_ch1
0x048REGdds_poff_ch2dds_poff_ch2dds_poff_ch2
0x04cREGdds_poff_ch3dds_poff_ch3dds_poff_ch3
0x050REGdsp_monit_amp_ch0dsp_monit_amp_ch0dsp_monit_amp_ch0
0x054REGdsp_monit_amp_ch1dsp_monit_amp_ch1dsp_monit_amp_ch1
0x058REGdsp_monit_amp_ch2dsp_monit_amp_ch2dsp_monit_amp_ch2
0x05cREGdsp_monit_amp_ch3dsp_monit_amp_ch3dsp_monit_amp_ch3
0x060REGdsp_monit_pos_xdsp_monit_pos_xdsp_monit_pos_x
0x064REGdsp_monit_pos_ydsp_monit_pos_ydsp_monit_pos_y
0x068REGdsp_monit_pos_qdsp_monit_pos_qdsp_monit_pos_q
0x06cREGdsp_monit_pos_sumdsp_monit_pos_sumdsp_monit_pos_sum
0x070REGdsp_monit_updtdsp_monit_updtdsp_monit_updt
0x074REGdsp_monit1_amp_ch0dsp_monit1_amp_ch0dsp_monit1_amp_ch0
0x078REGdsp_monit1_amp_ch1dsp_monit1_amp_ch1dsp_monit1_amp_ch1
0x07cREGdsp_monit1_amp_ch2dsp_monit1_amp_ch2dsp_monit1_amp_ch2
0x080REGdsp_monit1_amp_ch3dsp_monit1_amp_ch3dsp_monit1_amp_ch3
0x084REGdsp_monit1_pos_xdsp_monit1_pos_xdsp_monit1_pos_x
0x088REGdsp_monit1_pos_ydsp_monit1_pos_ydsp_monit1_pos_y
0x08cREGdsp_monit1_pos_qdsp_monit1_pos_qdsp_monit1_pos_q
0x090REGdsp_monit1_pos_sumdsp_monit1_pos_sumdsp_monit1_pos_sum
0x094REGdsp_monit1_updtdsp_monit1_updtdsp_monit1_updt
0x098-0x0abBLOCKampfifo_monitampfifo_monitampfifo_monit
0x098REGampfifo_monit.ampfifo_monit_r0ampfifo_monit_ampfifo_monit_r0ampfifo_monit.ampfifo_monit_r0
0x09cREGampfifo_monit.ampfifo_monit_r1ampfifo_monit_ampfifo_monit_r1ampfifo_monit.ampfifo_monit_r1
0x0a0REGampfifo_monit.ampfifo_monit_r2ampfifo_monit_ampfifo_monit_r2ampfifo_monit.ampfifo_monit_r2
0x0a4REGampfifo_monit.ampfifo_monit_r3ampfifo_monit_ampfifo_monit_r3ampfifo_monit.ampfifo_monit_r3
0x0a8REGampfifo_monit.ampfifo_monit_csrampfifo_monit_ampfifo_monit_csrampfifo_monit.ampfifo_monit_csr
0x0ac-0x0bfBLOCKposfifo_monitposfifo_monitposfifo_monit
0x0acREGposfifo_monit.posfifo_monit_r0posfifo_monit_posfifo_monit_r0posfifo_monit.posfifo_monit_r0
0x0b0REGposfifo_monit.posfifo_monit_r1posfifo_monit_posfifo_monit_r1posfifo_monit.posfifo_monit_r1
0x0b4REGposfifo_monit.posfifo_monit_r2posfifo_monit_posfifo_monit_r2posfifo_monit.posfifo_monit_r2
0x0b8REGposfifo_monit.posfifo_monit_r3posfifo_monit_posfifo_monit_r3posfifo_monit.posfifo_monit_r3
0x0bcREGposfifo_monit.posfifo_monit_csrposfifo_monit_posfifo_monit_csrposfifo_monit.posfifo_monit_csr
0x0c0-0x0d3BLOCKampfifo_monit1ampfifo_monit1ampfifo_monit1
0x0c0REGampfifo_monit1.ampfifo_monit1_r0ampfifo_monit1_ampfifo_monit1_r0ampfifo_monit1.ampfifo_monit1_r0
0x0c4REGampfifo_monit1.ampfifo_monit1_r1ampfifo_monit1_ampfifo_monit1_r1ampfifo_monit1.ampfifo_monit1_r1
0x0c8REGampfifo_monit1.ampfifo_monit1_r2ampfifo_monit1_ampfifo_monit1_r2ampfifo_monit1.ampfifo_monit1_r2
0x0ccREGampfifo_monit1.ampfifo_monit1_r3ampfifo_monit1_ampfifo_monit1_r3ampfifo_monit1.ampfifo_monit1_r3
0x0d0REGampfifo_monit1.ampfifo_monit1_csrampfifo_monit1_ampfifo_monit1_csrampfifo_monit1.ampfifo_monit1_csr
0x0d4-0x0e7BLOCKposfifo_monit1posfifo_monit1posfifo_monit1
0x0d4REGposfifo_monit1.posfifo_monit1_r0posfifo_monit1_posfifo_monit1_r0posfifo_monit1.posfifo_monit1_r0
0x0d8REGposfifo_monit1.posfifo_monit1_r1posfifo_monit1_posfifo_monit1_r1posfifo_monit1.posfifo_monit1_r1
0x0dcREGposfifo_monit1.posfifo_monit1_r2posfifo_monit1_posfifo_monit1_r2posfifo_monit1.posfifo_monit1_r2
0x0e0REGposfifo_monit1.posfifo_monit1_r3posfifo_monit1_posfifo_monit1_r3posfifo_monit1.posfifo_monit1_r3
0x0e4REGposfifo_monit1.posfifo_monit1_csrposfifo_monit1_posfifo_monit1_csrposfifo_monit1.posfifo_monit1_csr
0x0e8REGsw_tagsw_tagsw_tag
0x0ecREGsw_data_masksw_data_masksw_data_mask
0x0f0REGtbt_tagtbt_tagtbt_tag
0x0f4REGtbt_data_mask_ctltbt_data_mask_ctltbt_data_mask_ctl
0x0f8REGtbt_data_mask_samplestbt_data_mask_samplestbt_data_mask_samples
0x0fcREGmonit1_tagmonit1_tagmonit1_tag
0x100REGmonit1_data_mask_ctlmonit1_data_mask_ctlmonit1_data_mask_ctl
0x104REGmonit1_data_mask_samplesmonit1_data_mask_samplesmonit1_data_mask_samples
0x108REGmonit_tagmonit_tagmonit_tag
0x10cREGmonit_data_mask_ctlmonit_data_mask_ctlmonit_data_mask_ctl
0x110REGmonit_data_mask_samplesmonit_data_mask_samplesmonit_data_mask_samples
0x114REGoffset_xoffset_xoffset_x
0x118REGoffset_yoffset_yoffset_y
+ +

2. Register description

+ +

2.1. ds_tbt_thres

+ + + + + +
HW prefix:ds_tbt_thres
HW address:0x0
C prefix:ds_tbt_thres
C block offset:0x0
+

+Config divisor threshold TBT register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[5:0]val[25:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.2. ds_fofb_thres

+ + + + + +
HW prefix:ds_fofb_thres
HW address:0x4
C prefix:ds_fofb_thres
C block offset:0x4
+

+Config divisor threshold FOFB register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[5:0]val[25:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.3. ds_monit_thres

+ + + + + +
HW prefix:ds_monit_thres
HW address:0x8
C prefix:ds_monit_thres
C block offset:0x8
+

+Config divisor threshold Monit. register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[5:0]val[25:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.4. kx

+ + + + + +
HW prefix:kx
HW address:0xc
C prefix:kx
C block offset:0xc
+

+BPM sensitivity (X axis) parameter register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[6:0]val[24:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.5. ky

+ + + + + +
HW prefix:ky
HW address:0x10
C prefix:ky
C block offset:0x10
+

+BPM sensitivity (Y axis) parameter register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[6:0]val[24:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.6. ksum

+ + + + + +
HW prefix:ksum
HW address:0x14
C prefix:ksum
C block offset:0x14
+

+BPM sensitivity (Sum) parameter register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[6:0]val[24:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.7. dsp_ctnr_tbt

+ + + + + +
HW prefix:dsp_ctnr_tbt
HW address:0x18
C prefix:dsp_ctnr_tbt
C block offset:0x18
+

+DSP TBT incorrect TDM counter +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
ch23[15:8]
2322212019181716
ch23[7:0]
15141312111098
ch01[15:8]
76543210
ch01[7:0]
+ + +

2.8. dsp_ctnr_fofb

+ + + + + +
HW prefix:dsp_ctnr_fofb
HW address:0x1c
C prefix:dsp_ctnr_fofb
C block offset:0x1c
+

+DSP FOFB incorrect TDM counter +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
ch23[15:8]
2322212019181716
ch23[7:0]
15141312111098
ch01[15:8]
76543210
ch01[7:0]
+ + +

2.9. dsp_ctnr1_monit

+ + + + + +
HW prefix:dsp_ctnr1_monit
HW address:0x20
C prefix:dsp_ctnr1_monit
C block offset:0x20
+

+DSP Monit. incorrect TDM counter part 1 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
cfir[15:8]
2322212019181716
cfir[7:0]
15141312111098
cic[15:8]
76543210
cic[7:0]
+ + +

2.10. dsp_ctnr2_monit

+ + + + + +
HW prefix:dsp_ctnr2_monit
HW address:0x24
C prefix:dsp_ctnr2_monit
C block offset:0x24
+

+DSP Monit. incorrect TDM counter part 2 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
fir_01[15:8]
2322212019181716
fir_01[7:0]
15141312111098
pfir[15:8]
76543210
pfir[7:0]
+ + +

2.11. dsp_err_clr

+ + + + + +
HW prefix:dsp_err_clr
HW address:0x28
C prefix:dsp_err_clr
C block offset:0x28
+

+DSP error clearing +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
--------
76543210
----monit_part2monit_part1fofbtbt
+ + +

2.12. dds_cfg

+ + + + + +
HW prefix:dds_cfg
HW address:0x2c
C prefix:dds_cfg
C block offset:0x2c
+

+DDS general config registers for all channels +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved_ch3[6:0]valid_ch3
2322212019181716
reserved_ch2[6:0]valid_ch2
15141312111098
reserved_ch1[6:0]valid_ch1
76543210
reserved_ch0[5:0]test_datavalid_ch0
+ + +

2.13. dds_pinc_ch0

+ + + + + +
HW prefix:dds_pinc_ch0
HW address:0x30
C prefix:dds_pinc_ch0
C block offset:0x30
+

+DDS phase increment parameter register for channel 0 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[1:0]val[29:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.14. dds_pinc_ch1

+ + + + + +
HW prefix:dds_pinc_ch1
HW address:0x34
C prefix:dds_pinc_ch1
C block offset:0x34
+

+DDS phase increment parameter register for channel 1 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[1:0]val[29:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.15. dds_pinc_ch2

+ + + + + +
HW prefix:dds_pinc_ch2
HW address:0x38
C prefix:dds_pinc_ch2
C block offset:0x38
+

+DDS phase increment parameter register for channel 2 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[1:0]val[29:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.16. dds_pinc_ch3

+ + + + + +
HW prefix:dds_pinc_ch3
HW address:0x3c
C prefix:dds_pinc_ch3
C block offset:0x3c
+

+DDS phase increment parameter register for channel 3 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[1:0]val[29:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.17. dds_poff_ch0

+ + + + + +
HW prefix:dds_poff_ch0
HW address:0x40
C prefix:dds_poff_ch0
C block offset:0x40
+

+DDS phase offset parameter register for channel 0 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[1:0]val[29:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.18. dds_poff_ch1

+ + + + + +
HW prefix:dds_poff_ch1
HW address:0x44
C prefix:dds_poff_ch1
C block offset:0x44
+

+DDS phase offset parameter register for channel 1 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[1:0]val[29:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.19. dds_poff_ch2

+ + + + + +
HW prefix:dds_poff_ch2
HW address:0x48
C prefix:dds_poff_ch2
C block offset:0x48
+

+DDS phase offset parameter register for channel 2 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[1:0]val[29:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.20. dds_poff_ch3

+ + + + + +
HW prefix:dds_poff_ch3
HW address:0x4c
C prefix:dds_poff_ch3
C block offset:0x4c
+

+DDS phase offset parameter register for channel 3 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
reserved[1:0]val[29:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+ + +

2.21. dsp_monit_amp_ch0

+ + + + + +
HW prefix:dsp_monit_amp_ch0
HW address:0x50
C prefix:dsp_monit_amp_ch0
C block offset:0x50
+

+Monit. Amplitude Value for channel 0 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit_amp_ch0[31:24]
2322212019181716
dsp_monit_amp_ch0[23:16]
15141312111098
dsp_monit_amp_ch0[15:8]
76543210
dsp_monit_amp_ch0[7:0]
+ + +

2.22. dsp_monit_amp_ch1

+ + + + + +
HW prefix:dsp_monit_amp_ch1
HW address:0x54
C prefix:dsp_monit_amp_ch1
C block offset:0x54
+

+Monit. Amplitude Value for channel 1 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit_amp_ch1[31:24]
2322212019181716
dsp_monit_amp_ch1[23:16]
15141312111098
dsp_monit_amp_ch1[15:8]
76543210
dsp_monit_amp_ch1[7:0]
+ + +

2.23. dsp_monit_amp_ch2

+ + + + + +
HW prefix:dsp_monit_amp_ch2
HW address:0x58
C prefix:dsp_monit_amp_ch2
C block offset:0x58
+

+Monit. Amplitude Value for channel 2 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit_amp_ch2[31:24]
2322212019181716
dsp_monit_amp_ch2[23:16]
15141312111098
dsp_monit_amp_ch2[15:8]
76543210
dsp_monit_amp_ch2[7:0]
+ + +

2.24. dsp_monit_amp_ch3

+ + + + + +
HW prefix:dsp_monit_amp_ch3
HW address:0x5c
C prefix:dsp_monit_amp_ch3
C block offset:0x5c
+

+Monit. Amplitude Value for channel 3 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit_amp_ch3[31:24]
2322212019181716
dsp_monit_amp_ch3[23:16]
15141312111098
dsp_monit_amp_ch3[15:8]
76543210
dsp_monit_amp_ch3[7:0]
+ + +

2.25. dsp_monit_pos_x

+ + + + + +
HW prefix:dsp_monit_pos_x
HW address:0x60
C prefix:dsp_monit_pos_x
C block offset:0x60
+

+Monit. X Position Value +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit_pos_x[31:24]
2322212019181716
dsp_monit_pos_x[23:16]
15141312111098
dsp_monit_pos_x[15:8]
76543210
dsp_monit_pos_x[7:0]
+ + +

2.26. dsp_monit_pos_y

+ + + + + +
HW prefix:dsp_monit_pos_y
HW address:0x64
C prefix:dsp_monit_pos_y
C block offset:0x64
+

+Monit. Y Position Value +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit_pos_y[31:24]
2322212019181716
dsp_monit_pos_y[23:16]
15141312111098
dsp_monit_pos_y[15:8]
76543210
dsp_monit_pos_y[7:0]
+ + +

2.27. dsp_monit_pos_q

+ + + + + +
HW prefix:dsp_monit_pos_q
HW address:0x68
C prefix:dsp_monit_pos_q
C block offset:0x68
+

+Monit. Q Position Value +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit_pos_q[31:24]
2322212019181716
dsp_monit_pos_q[23:16]
15141312111098
dsp_monit_pos_q[15:8]
76543210
dsp_monit_pos_q[7:0]
+ + +

2.28. dsp_monit_pos_sum

+ + + + + +
HW prefix:dsp_monit_pos_sum
HW address:0x6c
C prefix:dsp_monit_pos_sum
C block offset:0x6c
+

+Monit. Sum Position Value +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit_pos_sum[31:24]
2322212019181716
dsp_monit_pos_sum[23:16]
15141312111098
dsp_monit_pos_sum[15:8]
76543210
dsp_monit_pos_sum[7:0]
+ + +

2.29. dsp_monit_updt

+ + + + + +
HW prefix:dsp_monit_updt
HW address:0x70
C prefix:dsp_monit_updt
C block offset:0x70
+

+Monit. Amp/Pos update trigger +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit_updt[31:24]
2322212019181716
dsp_monit_updt[23:16]
15141312111098
dsp_monit_updt[15:8]
76543210
dsp_monit_updt[7:0]
+ + +

2.30. dsp_monit1_amp_ch0

+ + + + + +
HW prefix:dsp_monit1_amp_ch0
HW address:0x74
C prefix:dsp_monit1_amp_ch0
C block offset:0x74
+

+Monit. 1 Amplitude Value for channel 0 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit1_amp_ch0[31:24]
2322212019181716
dsp_monit1_amp_ch0[23:16]
15141312111098
dsp_monit1_amp_ch0[15:8]
76543210
dsp_monit1_amp_ch0[7:0]
+ + +

2.31. dsp_monit1_amp_ch1

+ + + + + +
HW prefix:dsp_monit1_amp_ch1
HW address:0x78
C prefix:dsp_monit1_amp_ch1
C block offset:0x78
+

+Monit. 1 Amplitude Value for channel 1 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit1_amp_ch1[31:24]
2322212019181716
dsp_monit1_amp_ch1[23:16]
15141312111098
dsp_monit1_amp_ch1[15:8]
76543210
dsp_monit1_amp_ch1[7:0]
+ + +

2.32. dsp_monit1_amp_ch2

+ + + + + +
HW prefix:dsp_monit1_amp_ch2
HW address:0x7c
C prefix:dsp_monit1_amp_ch2
C block offset:0x7c
+

+Monit. 1 Amplitude Value for channel 2 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit1_amp_ch2[31:24]
2322212019181716
dsp_monit1_amp_ch2[23:16]
15141312111098
dsp_monit1_amp_ch2[15:8]
76543210
dsp_monit1_amp_ch2[7:0]
+ + +

2.33. dsp_monit1_amp_ch3

+ + + + + +
HW prefix:dsp_monit1_amp_ch3
HW address:0x80
C prefix:dsp_monit1_amp_ch3
C block offset:0x80
+

+Monit. 1 Amplitude Value for channel 3 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit1_amp_ch3[31:24]
2322212019181716
dsp_monit1_amp_ch3[23:16]
15141312111098
dsp_monit1_amp_ch3[15:8]
76543210
dsp_monit1_amp_ch3[7:0]
+ + +

2.34. dsp_monit1_pos_x

+ + + + + +
HW prefix:dsp_monit1_pos_x
HW address:0x84
C prefix:dsp_monit1_pos_x
C block offset:0x84
+

+Monit. 1 X Position Value +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit1_pos_x[31:24]
2322212019181716
dsp_monit1_pos_x[23:16]
15141312111098
dsp_monit1_pos_x[15:8]
76543210
dsp_monit1_pos_x[7:0]
+ + +

2.35. dsp_monit1_pos_y

+ + + + + +
HW prefix:dsp_monit1_pos_y
HW address:0x88
C prefix:dsp_monit1_pos_y
C block offset:0x88
+

+Monit. 1 Y Position Value +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit1_pos_y[31:24]
2322212019181716
dsp_monit1_pos_y[23:16]
15141312111098
dsp_monit1_pos_y[15:8]
76543210
dsp_monit1_pos_y[7:0]
+ + +

2.36. dsp_monit1_pos_q

+ + + + + +
HW prefix:dsp_monit1_pos_q
HW address:0x8c
C prefix:dsp_monit1_pos_q
C block offset:0x8c
+

+Monit. 1 Q Position Value +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit1_pos_q[31:24]
2322212019181716
dsp_monit1_pos_q[23:16]
15141312111098
dsp_monit1_pos_q[15:8]
76543210
dsp_monit1_pos_q[7:0]
+ + +

2.37. dsp_monit1_pos_sum

+ + + + + +
HW prefix:dsp_monit1_pos_sum
HW address:0x90
C prefix:dsp_monit1_pos_sum
C block offset:0x90
+

+Monit. 1 Sum Position Value +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit1_pos_sum[31:24]
2322212019181716
dsp_monit1_pos_sum[23:16]
15141312111098
dsp_monit1_pos_sum[15:8]
76543210
dsp_monit1_pos_sum[7:0]
+ + +

2.38. dsp_monit1_updt

+ + + + + +
HW prefix:dsp_monit1_updt
HW address:0x94
C prefix:dsp_monit1_updt
C block offset:0x94
+

+Monit. 1 Amp/Pos update trigger +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
dsp_monit1_updt[31:24]
2322212019181716
dsp_monit1_updt[23:16]
15141312111098
dsp_monit1_updt[15:8]
76543210
dsp_monit1_updt[7:0]
+ + +

2.39. ampfifo_monit.ampfifo_monit_r0

+ + + + + +
HW prefix:ampfifo_monit_ampfifo_monit_r0
HW address:0x98
C prefix:ampfifo_monit.ampfifo_monit_r0
C block offset:0x0
+

+FIFO 'AMP FIFO Monitoring' data output register 0 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
amp_ch0[31:24]
2322212019181716
amp_ch0[23:16]
15141312111098
amp_ch0[15:8]
76543210
amp_ch0[7:0]
+ + +

2.40. ampfifo_monit.ampfifo_monit_r1

+ + + + + +
HW prefix:ampfifo_monit_ampfifo_monit_r1
HW address:0x9c
C prefix:ampfifo_monit.ampfifo_monit_r1
C block offset:0x4
+

+FIFO 'AMP FIFO Monitoring' data output register 1 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
amp_ch1[31:24]
2322212019181716
amp_ch1[23:16]
15141312111098
amp_ch1[15:8]
76543210
amp_ch1[7:0]
+ + +

2.41. ampfifo_monit.ampfifo_monit_r2

+ + + + + +
HW prefix:ampfifo_monit_ampfifo_monit_r2
HW address:0xa0
C prefix:ampfifo_monit.ampfifo_monit_r2
C block offset:0x8
+

+FIFO 'AMP FIFO Monitoring' data output register 2 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
amp_ch2[31:24]
2322212019181716
amp_ch2[23:16]
15141312111098
amp_ch2[15:8]
76543210
amp_ch2[7:0]
+ + +

2.42. ampfifo_monit.ampfifo_monit_r3

+ + + + + +
HW prefix:ampfifo_monit_ampfifo_monit_r3
HW address:0xa4
C prefix:ampfifo_monit.ampfifo_monit_r3
C block offset:0xc
+

+FIFO 'AMP FIFO Monitoring' data output register 3 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
amp_ch3[31:24]
2322212019181716
amp_ch3[23:16]
15141312111098
amp_ch3[15:8]
76543210
amp_ch3[7:0]
+ + +

2.43. ampfifo_monit.ampfifo_monit_csr

+ + + + + +
HW prefix:ampfifo_monit_ampfifo_monit_csr
HW address:0xa8
C prefix:ampfifo_monit.ampfifo_monit_csr
C block offset:0x10
+

+FIFO 'AMP FIFO Monitoring' control/status register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
------emptyfull
15141312111098
--------
76543210
----count[3:0]
+ + +

2.44. posfifo_monit.posfifo_monit_r0

+ + + + + +
HW prefix:posfifo_monit_posfifo_monit_r0
HW address:0xac
C prefix:posfifo_monit.posfifo_monit_r0
C block offset:0x0
+

+FIFO 'POS FIFO Monitoring' data output register 0 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
pos_x[31:24]
2322212019181716
pos_x[23:16]
15141312111098
pos_x[15:8]
76543210
pos_x[7:0]
+ + +

2.45. posfifo_monit.posfifo_monit_r1

+ + + + + +
HW prefix:posfifo_monit_posfifo_monit_r1
HW address:0xb0
C prefix:posfifo_monit.posfifo_monit_r1
C block offset:0x4
+

+FIFO 'POS FIFO Monitoring' data output register 1 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
pos_y[31:24]
2322212019181716
pos_y[23:16]
15141312111098
pos_y[15:8]
76543210
pos_y[7:0]
+ + +

2.46. posfifo_monit.posfifo_monit_r2

+ + + + + +
HW prefix:posfifo_monit_posfifo_monit_r2
HW address:0xb4
C prefix:posfifo_monit.posfifo_monit_r2
C block offset:0x8
+

+FIFO 'POS FIFO Monitoring' data output register 2 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
pos_q[31:24]
2322212019181716
pos_q[23:16]
15141312111098
pos_q[15:8]
76543210
pos_q[7:0]
+ + +

2.47. posfifo_monit.posfifo_monit_r3

+ + + + + +
HW prefix:posfifo_monit_posfifo_monit_r3
HW address:0xb8
C prefix:posfifo_monit.posfifo_monit_r3
C block offset:0xc
+

+FIFO 'POS FIFO Monitoring' data output register 3 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
pos_sum[31:24]
2322212019181716
pos_sum[23:16]
15141312111098
pos_sum[15:8]
76543210
pos_sum[7:0]
+ + +

2.48. posfifo_monit.posfifo_monit_csr

+ + + + + +
HW prefix:posfifo_monit_posfifo_monit_csr
HW address:0xbc
C prefix:posfifo_monit.posfifo_monit_csr
C block offset:0x10
+

+FIFO 'POS FIFO Monitoring' control/status register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
------emptyfull
15141312111098
--------
76543210
----count[3:0]
+ + +

2.49. ampfifo_monit1.ampfifo_monit1_r0

+ + + + + +
HW prefix:ampfifo_monit1_ampfifo_monit1_r0
HW address:0xc0
C prefix:ampfifo_monit1.ampfifo_monit1_r0
C block offset:0x0
+

+FIFO 'AMP FIFO Monitoring 1' data output register 0 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
amp_ch0[31:24]
2322212019181716
amp_ch0[23:16]
15141312111098
amp_ch0[15:8]
76543210
amp_ch0[7:0]
+ + +

2.50. ampfifo_monit1.ampfifo_monit1_r1

+ + + + + +
HW prefix:ampfifo_monit1_ampfifo_monit1_r1
HW address:0xc4
C prefix:ampfifo_monit1.ampfifo_monit1_r1
C block offset:0x4
+

+FIFO 'AMP FIFO Monitoring 1' data output register 1 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
amp_ch1[31:24]
2322212019181716
amp_ch1[23:16]
15141312111098
amp_ch1[15:8]
76543210
amp_ch1[7:0]
+ + +

2.51. ampfifo_monit1.ampfifo_monit1_r2

+ + + + + +
HW prefix:ampfifo_monit1_ampfifo_monit1_r2
HW address:0xc8
C prefix:ampfifo_monit1.ampfifo_monit1_r2
C block offset:0x8
+

+FIFO 'AMP FIFO Monitoring 1' data output register 2 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
amp_ch2[31:24]
2322212019181716
amp_ch2[23:16]
15141312111098
amp_ch2[15:8]
76543210
amp_ch2[7:0]
+ + +

2.52. ampfifo_monit1.ampfifo_monit1_r3

+ + + + + +
HW prefix:ampfifo_monit1_ampfifo_monit1_r3
HW address:0xcc
C prefix:ampfifo_monit1.ampfifo_monit1_r3
C block offset:0xc
+

+FIFO 'AMP FIFO Monitoring 1' data output register 3 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
amp_ch3[31:24]
2322212019181716
amp_ch3[23:16]
15141312111098
amp_ch3[15:8]
76543210
amp_ch3[7:0]
+ + +

2.53. ampfifo_monit1.ampfifo_monit1_csr

+ + + + + +
HW prefix:ampfifo_monit1_ampfifo_monit1_csr
HW address:0xd0
C prefix:ampfifo_monit1.ampfifo_monit1_csr
C block offset:0x10
+

+FIFO 'AMP FIFO Monitoring 1' control/status register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
------emptyfull
15141312111098
--------
76543210
----count[3:0]
+ + +

2.54. posfifo_monit1.posfifo_monit1_r0

+ + + + + +
HW prefix:posfifo_monit1_posfifo_monit1_r0
HW address:0xd4
C prefix:posfifo_monit1.posfifo_monit1_r0
C block offset:0x0
+

+FIFO 'POS FIFO Monitoring 1' data output register 0 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
pos_x[31:24]
2322212019181716
pos_x[23:16]
15141312111098
pos_x[15:8]
76543210
pos_x[7:0]
+ + +

2.55. posfifo_monit1.posfifo_monit1_r1

+ + + + + +
HW prefix:posfifo_monit1_posfifo_monit1_r1
HW address:0xd8
C prefix:posfifo_monit1.posfifo_monit1_r1
C block offset:0x4
+

+FIFO 'POS FIFO Monitoring 1' data output register 1 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
pos_y[31:24]
2322212019181716
pos_y[23:16]
15141312111098
pos_y[15:8]
76543210
pos_y[7:0]
+ + +

2.56. posfifo_monit1.posfifo_monit1_r2

+ + + + + +
HW prefix:posfifo_monit1_posfifo_monit1_r2
HW address:0xdc
C prefix:posfifo_monit1.posfifo_monit1_r2
C block offset:0x8
+

+FIFO 'POS FIFO Monitoring 1' data output register 2 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
pos_q[31:24]
2322212019181716
pos_q[23:16]
15141312111098
pos_q[15:8]
76543210
pos_q[7:0]
+ + +

2.57. posfifo_monit1.posfifo_monit1_r3

+ + + + + +
HW prefix:posfifo_monit1_posfifo_monit1_r3
HW address:0xe0
C prefix:posfifo_monit1.posfifo_monit1_r3
C block offset:0xc
+

+FIFO 'POS FIFO Monitoring 1' data output register 3 +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
pos_sum[31:24]
2322212019181716
pos_sum[23:16]
15141312111098
pos_sum[15:8]
76543210
pos_sum[7:0]
+ + +

2.58. posfifo_monit1.posfifo_monit1_csr

+ + + + + +
HW prefix:posfifo_monit1_posfifo_monit1_csr
HW address:0xe4
C prefix:posfifo_monit1.posfifo_monit1_csr
C block offset:0x10
+

+FIFO 'POS FIFO Monitoring 1' control/status register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
------emptyfull
15141312111098
--------
76543210
----count[3:0]
+ + +

2.59. sw_tag

+ + + + + +
HW prefix:sw_tag
HW address:0xe8
C prefix:sw_tag
C block offset:0xe8
+

+Switching Tag synchronization +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
-desync_cnt[13:7]
15141312111098
desync_cnt[6:0]desync_cnt_rst
76543210
-------en
+ + +

2.60. sw_data_mask

+ + + + + +
HW prefix:sw_data_mask
HW address:0xec
C prefix:sw_data_mask
C block offset:0xec
+

+Switching Data Mask +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
-------samples[15:15]
15141312111098
samples[14:7]
76543210
samples[6:0]en
+ + +

2.61. tbt_tag

+ + + + + +
HW prefix:tbt_tag
HW address:0xf0
C prefix:tbt_tag
C block offset:0xf0
+

+TbT Synchronizing Trigger +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
desync_cnt[13:6]
2322212019181716
desync_cnt[5:0]desync_cnt_rstdly[15:15]
15141312111098
dly[14:7]
76543210
dly[6:0]en
+ + +

2.62. tbt_data_mask_ctl

+ + + + + +
HW prefix:tbt_data_mask_ctl
HW address:0xf4
C prefix:tbt_data_mask_ctl
C block offset:0xf4
+

+TbT Masking Control +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
--------
76543210
-------en
+ + +

2.63. tbt_data_mask_samples

+ + + + + +
HW prefix:tbt_data_mask_samples
HW address:0xf8
C prefix:tbt_data_mask_samples
C block offset:0xf8
+

+TbT Data Masking Samples +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
end[15:8]
2322212019181716
end[7:0]
15141312111098
beg[15:8]
76543210
beg[7:0]
+ + +

2.64. monit1_tag

+ + + + + +
HW prefix:monit1_tag
HW address:0xfc
C prefix:monit1_tag
C block offset:0xfc
+

+MONIT1 Synchronizing Trigger +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
desync_cnt[13:6]
2322212019181716
desync_cnt[5:0]desync_cnt_rstdly[15:15]
15141312111098
dly[14:7]
76543210
dly[6:0]en
+ + +

2.65. monit1_data_mask_ctl

+ + + + + +
HW prefix:monit1_data_mask_ctl
HW address:0x100
C prefix:monit1_data_mask_ctl
C block offset:0x100
+

+MONIT1 Masking Control +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
--------
76543210
-------en
+ + +

2.66. monit1_data_mask_samples

+ + + + + +
HW prefix:monit1_data_mask_samples
HW address:0x104
C prefix:monit1_data_mask_samples
C block offset:0x104
+

+MONIT1 Data Masking Samples +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
end[15:8]
2322212019181716
end[7:0]
15141312111098
beg[15:8]
76543210
beg[7:0]
+ + +

2.67. monit_tag

+ + + + + +
HW prefix:monit_tag
HW address:0x108
C prefix:monit_tag
C block offset:0x108
+

+MONIT Synchronizing Trigger +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
desync_cnt[13:6]
2322212019181716
desync_cnt[5:0]desync_cnt_rstdly[15:15]
15141312111098
dly[14:7]
76543210
dly[6:0]en
+ + +

2.68. monit_data_mask_ctl

+ + + + + +
HW prefix:monit_data_mask_ctl
HW address:0x10c
C prefix:monit_data_mask_ctl
C block offset:0x10c
+

+MONIT Masking Control +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
--------
76543210
-------en
+ + +

2.69. monit_data_mask_samples

+ + + + + +
HW prefix:monit_data_mask_samples
HW address:0x110
C prefix:monit_data_mask_samples
C block offset:0x110
+

+MONIT Data Masking Samples +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
end[15:8]
2322212019181716
end[7:0]
15141312111098
beg[15:8]
76543210
beg[7:0]
+ + +

2.70. offset_x

+ + + + + +
HW prefix:offset_x
HW address:0x114
C prefix:offset_x
C block offset:0x114
+

+BPM X position offset parameter register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
offset_x[31:24]
2322212019181716
offset_x[23:16]
15141312111098
offset_x[15:8]
76543210
offset_x[7:0]
+ + +

2.71. offset_y

+ + + + + +
HW prefix:offset_y
HW address:0x118
C prefix:offset_y
C block offset:0x118
+

+BPM Y position offset parameter register +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
offset_y[31:24]
2322212019181716
offset_y[23:16]
15141312111098
offset_y[15:8]
76543210
offset_y[7:0]
+ + + + + diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby new file mode 100644 index 00000000..a906ed76 --- /dev/null +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby @@ -0,0 +1,2022 @@ +memory-map: + bus: wb-32-be + name: pos_calc + description: Position Calculation Core registers + comment: | + Wishbone slave for Position Calculation Core + x-wbgen: + hdl_entity: wb_pos_calc_regs + children: +# -------------------------------------------- +# ------- Config Threshold Registers --------- +# -------------------------------------------- + - reg: + name: ds_tbt_thres + address: 0x00000000 + width: 32 + access: rw + description: Config divisor threshold TBT register + comment: | + Config Divisor for TBT rate. + Minimum amplitude sum in which the position + calculation is performed + children: + - field: + name: val + range: 25-0 + description: Config divisor threshold TBT + comment: | + Minimum amplitude sum in which the position + calculation for TBT rate is performed, in FIX26_22 + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-26 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - reg: + name: ds_fofb_thres + address: 0x00000004 + width: 32 + access: rw + description: Config divisor threshold FOFB register + comment: | + Config Divisor for FOFB rate. + Minimum amplitude sum in which the position + calculation is performed + children: + - field: + name: val + range: 25-0 + description: Config divisor threshold FOFB + comment: | + Minimum amplitude sum in which the position + calculation for FOFB rate is performed, in FIX26_22 + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-26 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - reg: + name: ds_monit_thres + address: 0x00000008 + width: 32 + access: rw + description: Config divisor threshold Monit. register + comment: | + Config Divisor for Monit. rate. + Minimum amplitude sum in which the position + calculation is performed + children: + - field: + name: val + range: 25-0 + description: Config Divisor Threshold Monit. + comment: | + Minimum amplitude sum in which the position + calculation for Monit. rate is performed, in FIX26_22 + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-26 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY +# -------------------------------------------- +# ------- Kx, Ky and Ksum Registers --------- +# -------------------------------------------- + - reg: + name: kx + address: 0x0000000c + width: 32 + access: rw + description: BPM sensitivity (X axis) parameter register + comment: | + BPM sensitivity (X axis) parameter + children: + - field: + name: val + range: 24-0 + description: BPM sensitivity (X axis) parameter register + comment: | + BPM sensitivity (X axis) parameter, in UFIX25_0. + It effectively multiplies the calculated position + with a determined value. Typical values lie around + 10000000d + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-25 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - reg: + name: ky + address: 0x00000010 + width: 32 + access: rw + description: BPM sensitivity (Y axis) parameter register + comment: | + BPM sensitivity (Y axis) parameter + children: + - field: + name: val + range: 24-0 + description: BPM sensitivity (Y axis) parameter register + comment: | + BPM sensitivity (Y axis) parameter, in UFIX25_0. + It effectively multiplies the calculated position + with a determined value. Typical values lie around + 10000000d + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-25 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - reg: + name: ksum + address: 0x00000014 + width: 32 + access: rw + description: BPM sensitivity (Sum) parameter register + comment: | + BPM sensitivity (Sum) parameter + children: + - field: + name: val + range: 24-0 + description: BPM sensitivity (Sum) parameter register + comment: | + BPM sensitivity (Sum) parameter, in FIX25_24. + It effectively multiplies the calculated position + with a determined value. Typical values lie around + 1.0d + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-25 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY +# -------------------------------------------- +# ------------- DSP Counters ---------------- +# -------------------------------------------- + - reg: + name: dsp_ctnr_tbt + address: 0x00000018 + width: 32 + access: ro + description: DSP TBT incorrect TDM counter + comment: | + This register counts the number of errors on TDM tranfers + for TBT DSP chain + children: + - field: + name: ch01 + range: 15-0 + description: TBT incorrect counter for channels 0/1 (multiplexed) + comment: | + This register holds the number of incorrect transfers + on TDM for channels 0/1 (multiplexed) + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - field: + name: ch23 + range: 31-16 + description: TBT incorrect counter for channels 2/3 (multiplexed) + comment: | + This register holds the number of incorrect transfers + on TDM for channels 2/3 (multiplexed) + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - reg: + name: dsp_ctnr_fofb + address: 0x0000001c + width: 32 + access: ro + description: DSP FOFB incorrect TDM counter + comment: | + This register counts the number of errors on TDM tranfers + for FOFB DSP chain + children: + - field: + name: ch01 + range: 15-0 + description: FOFB incorrect counter for channels 0/1 (multiplexed) + comment: | + This register holds the number of incorrect transfers + on TDM for channels 0/1 (multiplexed) + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - field: + name: ch23 + range: 31-16 + description: FOFB incorrect counter for channels 2/3 (multiplexed) + comment: | + This register holds the number of incorrect transfers + on TDM for channels 2/3 (multiplexed) + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - reg: + name: dsp_ctnr1_monit + address: 0x00000020 + width: 32 + access: ro + description: DSP Monit. incorrect TDM counter part 1 + comment: | + This register counts the number of errors on TDM tranfers + for CIC and CFIR filters of the Monit. DSP chain + children: + - field: + name: cic + range: 15-0 + description: Monit. CIC incorrect counter for channels 0/1/2/3 (multiplexed) + comment: | + This register holds the number of incorrect transfers + on TDM for channels 0/1/2/3 (multiplexed) + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - field: + name: cfir + range: 31-16 + description: Monit. CFIR incorrect counter for channels 0/1/2/3 (multiplexed) + comment: | + This register holds the number of incorrect transfers + on TDM for channels 0/1/2/3 (multiplexed) + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - reg: + name: dsp_ctnr2_monit + address: 0x00000024 + width: 32 + access: ro + description: DSP Monit. incorrect TDM counter part 2 + comment: | + This register counts the number of errors on TDM tranfers + for PFIR filter of the Monit. and Monit_01 DSP chain + children: + - field: + name: pfir + range: 15-0 + description: Monit. PFIR incorrect counter for channels 0/1/2/3 (multiplexed) + comment: | + This register holds the number of incorrect transfers + on TDM for channels 0/1/2/3 (multiplexed) on Monit. chain + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - field: + name: fir_01 + range: 31-16 + description: Monit. 0.1 Hz incorrect counter for channels 0/1/2/3 (multiplexed) + comment: | + This register holds the number of incorrect transfers + on TDM for channels 0/1/2/3 (multiplexed) on Monit_01 chain + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - reg: + name: dsp_err_clr + address: 0x00000028 + width: 32 + access: wo + description: DSP error clearing + comment: | + This register clears the error counters + children: + - field: + name: tbt + range: 0 + description: Clear TBT error counters + comment: | + This register clears the error counter for the TBT rate + write 0: no effect + write 1: clear error counter + x-wbgen: + type: MONOSTABLE + access_bus: WRITE_ONLY + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: fofb + range: 1 + description: Clear FOFB error counters + comment: | + This register clears the error counter for the FOFB rate + write 0: no effect + write 1: clear error counter + x-wbgen: + type: MONOSTABLE + access_bus: WRITE_ONLY + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: monit_part1 + range: 2 + description: Clear Monit. CIC and CFIR error counters + comment: | + This register clears the error counter for the CIC and CFIR rate + write 0: no effect + write 1: clear error counter + x-wbgen: + type: MONOSTABLE + access_bus: WRITE_ONLY + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: monit_part2 + range: 3 + description: Clear Monit. PFIR and Monit. 0.1 error counters + comment: | + This register clears the error counter for the Monit. PFIR + and Monit. 0.1 rate + write 0: no effect + write 1: clear error counter + x-wbgen: + type: MONOSTABLE + access_bus: WRITE_ONLY + access_dev: READ_ONLY + clock: fs_clk2x_i +# -------------------------------------------- +# ----- DDS General Config Registers -------- +# -------------------------------------------- + - reg: + name: dds_cfg + address: 0x0000002c + width: 32 + access: rw + description: DDS general config registers for all channels + comment: | + DDS general config registers for all channels + children: + - field: + name: valid_ch0 + range: 0 + description: Valid signal for channel 0 DDS + comment: | + Valid signal for channel 0 DDS: + write 0: no effect + write 1: write phase increment and offset into DDS + x-wbgen: + type: MONOSTABLE + access_bus: WRITE_ONLY + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: test_data + range: 1 + description: Test data counter for all channels + comment: | + Test data counter for all channels: + write 0: real data + write 1: test counter data + x-wbgen: + type: BIT + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: reserved_ch0 + range: 7-2 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - field: + name: valid_ch1 + range: 8 + description: Valid signal for channel 1 DDS + comment: | + Valid signal for channel 1 DDS: + write 0: no effect + write 1: write phase increment and offset into DDS + x-wbgen: + type: MONOSTABLE + access_bus: WRITE_ONLY + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: reserved_ch1 + range: 15-9 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - field: + name: valid_ch2 + range: 16 + description: Valid signal for channel 2 DDS + comment: | + Valid signal for channel 2 DDS: + write 0: no effect + write 1: write phase increment and offset into DDS + x-wbgen: + type: MONOSTABLE + access_bus: WRITE_ONLY + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: reserved_ch2 + range: 23-17 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - field: + name: valid_ch3 + range: 24 + description: Valid signal for channel 3 DDS + comment: | + Valid signal for channel 3 DDS: + write 0: no effect + write 1: write phase increment and offset into DDS + x-wbgen: + type: MONOSTABLE + access_bus: WRITE_ONLY + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: reserved_ch3 + range: 31-25 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY +# -------------------------------------------- +# ----- DDS Phase Increment Registers -------- +# -------------------------------------------- + - reg: + name: dds_pinc_ch0 + address: 0x00000030 + width: 32 + access: rw + description: DDS phase increment parameter register for channel 0 + comment: | + DDS phase increment parameter register for channel 0 + children: + - field: + name: val + range: 29-0 + description: DDS phase increment parameter register for channel 0 + comment: | + DDS phase increment parameter register for channel 0. + It can be calculated as phase_inc = f_out * 2^(B_theta) / f_clk, + in which B_theta = 30 and f_clk = adc_clk, f_out = desired frequency. + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-30 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - reg: + name: dds_pinc_ch1 + address: 0x00000034 + width: 32 + access: rw + description: DDS phase increment parameter register for channel 1 + comment: | + DDS phase increment parameter register for channel 1 + children: + - field: + name: val + range: 29-0 + description: DDS phase increment parameter register for channel 1 + comment: | + DDS phase increment parameter register for channel 1. + It can be calculated as phase_inc = f_out * 2^(B_theta) / f_clk, + in which B_theta = 30 and f_clk = adc_clk, f_out = desired frequency. + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-30 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - reg: + name: dds_pinc_ch2 + address: 0x00000038 + width: 32 + access: rw + description: DDS phase increment parameter register for channel 2 + comment: | + DDS phase increment parameter register for channel 2 + children: + - field: + name: val + range: 29-0 + description: DDS phase increment parameter register for channel 2 + comment: | + DDS phase increment parameter register for channel 2. + It can be calculated as phase_inc = f_out * 2^(B_theta) / f_clk, + in which B_theta = 30 and f_clk = adc_clk, f_out = desired frequency. + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-30 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - reg: + name: dds_pinc_ch3 + address: 0x0000003c + width: 32 + access: rw + description: DDS phase increment parameter register for channel 3 + comment: | + DDS phase increment parameter register for channel 3 + children: + - field: + name: val + range: 29-0 + description: DDS phase increment parameter register for channel 3 + comment: | + DDS phase increment parameter register for channel 3. + It can be calculated as phase_inc = f_out * 2^(B_theta) / f_clk, + in which B_theta = 30 and f_clk = adc_clk, f_out = desired frequency. + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-30 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY +# -------------------------------------------- +# ------ DDS Phase Offset Registers --------- +# -------------------------------------------- + - reg: + name: dds_poff_ch0 + address: 0x00000040 + width: 32 + access: rw + description: DDS phase offset parameter register for channel 0 + comment: | + DDS phase offset parameter register for channel 0 + children: + - field: + name: val + range: 29-0 + description: DDS phase offset parameter register for channel 0 + comment: | + DDS phase offset parameter register for channel 0. + It is determined as a fraction of a cycle, in FIX30_29. + For instance, 0.5 = 180 deegres offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-30 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - reg: + name: dds_poff_ch1 + address: 0x00000044 + width: 32 + access: rw + description: DDS phase offset parameter register for channel 1 + comment: | + DDS phase offset parameter register for channel 1 + children: + - field: + name: val + range: 29-0 + description: DDS phase offset parameter register for channel 1 + comment: | + DDS phase offset parameter register for channel 1. + It is determined as a fraction of a cycle, in FIX30_29. + For instance, 0.5 = 180 deegres offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-30 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - reg: + name: dds_poff_ch2 + address: 0x00000048 + width: 32 + access: rw + description: DDS phase offset parameter register for channel 2 + comment: | + DDS phase offset parameter register for channel 2 + children: + - field: + name: val + range: 29-0 + description: DDS phase offset parameter register for channel 2 + comment: | + DDS phase offset parameter register for channel 2. + It is determined as a fraction of a cycle, in FIX30_29. + For instance, 0.5 = 180 deegres offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-30 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + - reg: + name: dds_poff_ch3 + address: 0x0000004c + width: 32 + access: rw + description: DDS phase offset parameter register for channel 3 + comment: | + DDS phase offset parameter register for channel 3 + children: + - field: + name: val + range: 29-0 + description: DDS phase offset parameter register for channel 3 + comment: | + DDS phase offset parameter register for channel 2. + It is determined as a fraction of a cycle, in FIX30_29. + For instance, 0.5 = 180 deegres offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: reserved + range: 31-30 + description: Reserved + comment: | + Ignore on write, read as 0's + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY +# -------------------------------------------------------------------------- +# Monit. Amplitude Values +# -------------------------------------------------------------------------- + - reg: + name: dsp_monit_amp_ch0 + address: 0x00000050 + width: 32 + access: ro + description: Monit. Amplitude Value for channel 0 + comment: | + Monit. Amplitude Value for channel 0 + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. Amplitude Value for channel 0 + field_comment: | + Monit. Amplitude Value for channel 0 + read: Amplitude Value Monit. channel 0 + write: no effect + - reg: + name: dsp_monit_amp_ch1 + address: 0x00000054 + width: 32 + access: ro + description: Monit. Amplitude Value for channel 1 + comment: | + Monit. Amplitude Value for channel 1 + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. Amplitude Value for channel 1 + field_comment: | + Monit. Amplitude Value for channel 1 + read: Amplitude Value Monit. channel 1 + write: no effect + - reg: + name: dsp_monit_amp_ch2 + address: 0x00000058 + width: 32 + access: ro + description: Monit. Amplitude Value for channel 2 + comment: | + Monit. Amplitude Value for channel 2 + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. Amplitude Value for channel 2 + field_comment: | + Monit. Amplitude Value for channel 2 + read: Amplitude Value Monit. channel 2 + write: no effect + - reg: + name: dsp_monit_amp_ch3 + address: 0x0000005c + width: 32 + access: ro + description: Monit. Amplitude Value for channel 3 + comment: | + Monit. Amplitude Value for channel 3 + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. Amplitude Value for channel 3 + field_comment: | + Monit. Amplitude Value for channel 3 + read: Amplitude Value Monit. channel 3 + write: no effect +# -------------------------------------------------------------------------- +# Monit. Position Values +# -------------------------------------------------------------------------- + - reg: + name: dsp_monit_pos_x + address: 0x00000060 + width: 32 + access: ro + description: Monit. X Position Value + comment: | + Monit. X Position Value + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. X Position Value + field_comment: | + Monit. X Position Value + read: Monit. X Position Value + write: no effect + - reg: + name: dsp_monit_pos_y + address: 0x00000064 + width: 32 + access: ro + description: Monit. Y Position Value + comment: | + Monit. Y Position Value + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. Y Position Value + field_comment: | + Monit. Y Position Value + read: Monit. Y Position Value + write: no effect + - reg: + name: dsp_monit_pos_q + address: 0x00000068 + width: 32 + access: ro + description: Monit. Q Position Value + comment: | + Monit. Q Position Value + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. Q Position Value + field_comment: | + Monit. Q Position Value + read: Monit. Q Position Value + write: no effect + - reg: + name: dsp_monit_pos_sum + address: 0x0000006c + width: 32 + access: ro + description: Monit. Sum Position Value + comment: | + Monit. Sum Position Value + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. Sum Position Value + field_comment: | + Monit. Sum Position Value + read: Monit. Sum Position Value + write: no effect + - reg: + name: dsp_monit_updt + address: 0x00000070 + width: 32 + access: wo + description: Monit. Amp/Pos update trigger + comment: | + Monit. Amp/Pos update trigger + x-wbgen: + type: PASS_THROUGH + field_description: Monit. Amp/Pos Update (ignore on read) + x-hdl: + type: wire + x-hdl: + write-strobe: True +# -------------------------------------------------------------------------- +# Monit. 1 Amplitude Values +# -------------------------------------------------------------------------- + - reg: + name: dsp_monit1_amp_ch0 + address: 0x00000074 + width: 32 + access: ro + description: Monit. 1 Amplitude Value for channel 0 + comment: | + Monit. 1 Amplitude Value for channel 0 + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. 1 Amplitude Value for channel 0 + field_comment: | + Monit. 1 Amplitude Value for channel 0 + read: Amplitude Value Monit. channel 0 + write: no effect + - reg: + name: dsp_monit1_amp_ch1 + address: 0x00000078 + width: 32 + access: ro + description: Monit. 1 Amplitude Value for channel 1 + comment: | + Monit. 1 Amplitude Value for channel 1 + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. 1 Amplitude Value for channel 1 + field_comment: | + Monit. 1 Amplitude Value for channel 1 + read: Amplitude Value Monit. 1 channel 1 + write: no effect + - reg: + name: dsp_monit1_amp_ch2 + address: 0x0000007c + width: 32 + access: ro + description: Monit. 1 Amplitude Value for channel 2 + comment: | + Monit. 1 Amplitude Value for channel 2 + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. 1 Amplitude Value for channel 2 + field_comment: | + Monit. 1 Amplitude Value for channel 2 + read: Amplitude Value Monit. 1 channel 2 + write: no effect + - reg: + name: dsp_monit1_amp_ch3 + address: 0x00000080 + width: 32 + access: ro + description: Monit. 1 Amplitude Value for channel 3 + comment: | + Monit. 1 Amplitude Value for channel 3 + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. 1 Amplitude Value for channel 3 + field_comment: | + Monit. 1 Amplitude Value for channel 3 + read: Amplitude Value Monit. 1 channel 3 + write: no effect +# -------------------------------------------------------------------------- +# Monit. 1 Position Values +# -------------------------------------------------------------------------- + - reg: + name: dsp_monit1_pos_x + address: 0x00000084 + width: 32 + access: ro + description: Monit. 1 X Position Value + comment: | + Monit. 1 X Position Value + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. 1 X Position Value + field_comment: | + Monit. 1 X Position Value + read: Monit. 1 X Position Value + write: no effect + - reg: + name: dsp_monit1_pos_y + address: 0x00000088 + width: 32 + access: ro + description: Monit. 1 Y Position Value + comment: | + Monit. 1 Y Position Value + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. 1 Y Position Value + field_comment: | + Monit. 1 Y Position Value + read: Monit. 1 Y Position Value + write: no effect + - reg: + name: dsp_monit1_pos_q + address: 0x0000008c + width: 32 + access: ro + description: Monit. 1 Q Position Value + comment: | + Monit. 1 Q Position Value + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. 1 Q Position Value + field_comment: | + Monit. 1 Q Position Value + read: Monit. 1 Q Position Value + write: no effect + - reg: + name: dsp_monit1_pos_sum + address: 0x00000090 + width: 32 + access: ro + description: Monit. 1 Sum Position Value + comment: | + Monit. 1 Sum Position Value + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + field_description: Monit. 1 Sum Position Value + field_comment: | + Monit. 1 Sum Position Value + read: Monit. Sum Position Value + write: no effect + - reg: + name: dsp_monit1_updt + address: 0x00000094 + width: 32 + access: wo + description: Monit. 1 Amp/Pos update trigger + comment: | + Monit. 1 Amp/Pos update trigger + x-wbgen: + type: PASS_THROUGH + field_description: Monit. 1 Amp/Pos Update (ignore on read) + x-hdl: + type: wire + x-hdl: + write-strobe: True +# -------------------------------------------------------------------------- +# Monit. Amplitude/Position Values New Interface +# -------------------------------------------------------------------------- + - block: + name: ampfifo_monit + address: 0x00000098 + size: 20 + description: AMP FIFO Monitoring + comment: | + This FIFO holds most recent amplitude values from DSP Monit. chain + align: False + x-wbgen: + kind: fifo + direction: CORE_TO_BUS + depth: 16 + wire_full: True + wire_empty: True + wire_count: True + children: + - reg: + name: ampfifo_monit_r0 + address: 0x00000000 + width: 32 + access: ro + description: FIFO 'AMP FIFO Monitoring' data output register 0 + children: + - field: + name: amp_ch0 + range: 31-0 + description: Channel 0 Amplitude + x-wbgen: + type: SLV + - reg: + name: ampfifo_monit_r1 + address: 0x00000004 + width: 32 + access: ro + description: FIFO 'AMP FIFO Monitoring' data output register 1 + children: + - field: + name: amp_ch1 + range: 31-0 + description: Channel 1 Amplitude + x-wbgen: + type: SLV + - reg: + name: ampfifo_monit_r2 + address: 0x00000008 + width: 32 + access: ro + description: FIFO 'AMP FIFO Monitoring' data output register 2 + children: + - field: + name: amp_ch2 + range: 31-0 + description: Channel 2 Amplitude + x-wbgen: + type: SLV + - reg: + name: ampfifo_monit_r3 + address: 0x0000000c + width: 32 + access: ro + description: FIFO 'AMP FIFO Monitoring' data output register 3 + children: + - field: + name: amp_ch3 + range: 31-0 + description: Channel 3 Amplitude + x-wbgen: + type: SLV + - reg: + name: ampfifo_monit_csr + address: 0x00000010 + width: 32 + access: ro + description: FIFO 'AMP FIFO Monitoring' control/status register + x-wbgen: + kind: fifocs + children: + - field: + name: full + range: 16 + description: FIFO full flag + comment: | + 1: FIFO 'AMP FIFO Monitoring' is full + 0: FIFO is not full + x-wbgen: + type: BIT + kind: full + - field: + name: empty + range: 17 + description: FIFO empty flag + comment: | + 1: FIFO 'AMP FIFO Monitoring' is empty + 0: FIFO is not empty + x-wbgen: + type: BIT + kind: empty + - field: + name: count + range: 3-0 + description: FIFO counter + comment: | + Number of data records currently being stored in FIFO 'AMP FIFO Monitoring' + x-wbgen: + kind: count + - block: + name: posfifo_monit + address: 0x000000ac + size: 20 + description: POS FIFO Monitoring + comment: | + This FIFO holds most recent position values from DSP Monit. chain + align: False + x-wbgen: + kind: fifo + direction: CORE_TO_BUS + depth: 16 + wire_full: True + wire_empty: True + wire_count: True + children: + - reg: + name: posfifo_monit_r0 + address: 0x00000000 + width: 32 + access: ro + description: FIFO 'POS FIFO Monitoring' data output register 0 + children: + - field: + name: pos_x + range: 31-0 + description: Channel X Position + x-wbgen: + type: SLV + - reg: + name: posfifo_monit_r1 + address: 0x00000004 + width: 32 + access: ro + description: FIFO 'POS FIFO Monitoring' data output register 1 + children: + - field: + name: pos_y + range: 31-0 + description: Channel Y Position + x-wbgen: + type: SLV + - reg: + name: posfifo_monit_r2 + address: 0x00000008 + width: 32 + access: ro + description: FIFO 'POS FIFO Monitoring' data output register 2 + children: + - field: + name: pos_q + range: 31-0 + description: Channel Q Position + x-wbgen: + type: SLV + - reg: + name: posfifo_monit_r3 + address: 0x0000000c + width: 32 + access: ro + description: FIFO 'POS FIFO Monitoring' data output register 3 + children: + - field: + name: pos_sum + range: 31-0 + description: Channel Sum Position + x-wbgen: + type: SLV + - reg: + name: posfifo_monit_csr + address: 0x00000010 + width: 32 + access: ro + description: FIFO 'POS FIFO Monitoring' control/status register + x-wbgen: + kind: fifocs + children: + - field: + name: full + range: 16 + description: FIFO full flag + comment: | + 1: FIFO 'POS FIFO Monitoring' is full + 0: FIFO is not full + x-wbgen: + type: BIT + kind: full + - field: + name: empty + range: 17 + description: FIFO empty flag + comment: | + 1: FIFO 'POS FIFO Monitoring' is empty + 0: FIFO is not empty + x-wbgen: + type: BIT + kind: empty + - field: + name: count + range: 3-0 + description: FIFO counter + comment: | + Number of data records currently being stored in FIFO 'POS FIFO Monitoring' + x-wbgen: + kind: count +# -------------------------------------------------------------------------- +# Monit. 1 Amplitude/Position Values New Interface +# -------------------------------------------------------------------------- + - block: + name: ampfifo_monit1 + address: 0x000000c0 + size: 20 + description: AMP FIFO Monitoring 1 + comment: | + This FIFO holds most recent amplitude values from DSP Monit. 1 chain + align: False + x-wbgen: + kind: fifo + direction: CORE_TO_BUS + depth: 16 + wire_full: True + wire_empty: True + wire_count: True + children: + - reg: + name: ampfifo_monit1_r0 + address: 0x00000000 + width: 32 + access: ro + description: FIFO 'AMP FIFO Monitoring 1' data output register 0 + children: + - field: + name: amp_ch0 + range: 31-0 + description: Channel 0 Amplitude + x-wbgen: + type: SLV + - reg: + name: ampfifo_monit1_r1 + address: 0x00000004 + width: 32 + access: ro + description: FIFO 'AMP FIFO Monitoring 1' data output register 1 + children: + - field: + name: amp_ch1 + range: 31-0 + description: Channel 1 Amplitude + x-wbgen: + type: SLV + - reg: + name: ampfifo_monit1_r2 + address: 0x00000008 + width: 32 + access: ro + description: FIFO 'AMP FIFO Monitoring 1' data output register 2 + children: + - field: + name: amp_ch2 + range: 31-0 + description: Channel 2 Amplitude + x-wbgen: + type: SLV + - reg: + name: ampfifo_monit1_r3 + address: 0x0000000c + width: 32 + access: ro + description: FIFO 'AMP FIFO Monitoring 1' data output register 3 + children: + - field: + name: amp_ch3 + range: 31-0 + description: Channel 3 Amplitude + x-wbgen: + type: SLV + - reg: + name: ampfifo_monit1_csr + address: 0x00000010 + width: 32 + access: ro + description: FIFO 'AMP FIFO Monitoring 1' control/status register + x-wbgen: + kind: fifocs + children: + - field: + name: full + range: 16 + description: FIFO full flag + comment: | + 1: FIFO 'AMP FIFO Monitoring 1' is full + 0: FIFO is not full + x-wbgen: + type: BIT + kind: full + - field: + name: empty + range: 17 + description: FIFO empty flag + comment: | + 1: FIFO 'AMP FIFO Monitoring 1' is empty + 0: FIFO is not empty + x-wbgen: + type: BIT + kind: empty + - field: + name: count + range: 3-0 + description: FIFO counter + comment: | + Number of data records currently being stored in FIFO 'AMP FIFO Monitoring 1' + x-wbgen: + kind: count + - block: + name: posfifo_monit1 + address: 0x000000d4 + size: 20 + description: POS FIFO Monitoring 1 + comment: | + This FIFO holds most recent position values from DSP Monit. 1 chain + align: False + x-wbgen: + kind: fifo + direction: CORE_TO_BUS + depth: 16 + wire_full: True + wire_empty: True + wire_count: True + children: + - reg: + name: posfifo_monit1_r0 + address: 0x00000000 + width: 32 + access: ro + description: FIFO 'POS FIFO Monitoring 1' data output register 0 + children: + - field: + name: pos_x + range: 31-0 + description: Channel X Position + x-wbgen: + type: SLV + - reg: + name: posfifo_monit1_r1 + address: 0x00000004 + width: 32 + access: ro + description: FIFO 'POS FIFO Monitoring 1' data output register 1 + children: + - field: + name: pos_y + range: 31-0 + description: Channel Y Position + x-wbgen: + type: SLV + - reg: + name: posfifo_monit1_r2 + address: 0x00000008 + width: 32 + access: ro + description: FIFO 'POS FIFO Monitoring 1' data output register 2 + children: + - field: + name: pos_q + range: 31-0 + description: Channel Q Position + x-wbgen: + type: SLV + - reg: + name: posfifo_monit1_r3 + address: 0x0000000c + width: 32 + access: ro + description: FIFO 'POS FIFO Monitoring 1' data output register 3 + children: + - field: + name: pos_sum + range: 31-0 + description: Channel Sum Position + x-wbgen: + type: SLV + - reg: + name: posfifo_monit1_csr + address: 0x00000010 + width: 32 + access: ro + description: FIFO 'POS FIFO Monitoring 1' control/status register + x-wbgen: + kind: fifocs + children: + - field: + name: full + range: 16 + description: FIFO full flag + comment: | + 1: FIFO 'POS FIFO Monitoring 1' is full + 0: FIFO is not full + x-wbgen: + type: BIT + kind: full + - field: + name: empty + range: 17 + description: FIFO empty flag + comment: | + 1: FIFO 'POS FIFO Monitoring 1' is empty + 0: FIFO is not empty + x-wbgen: + type: BIT + kind: empty + - field: + name: count + range: 3-0 + description: FIFO counter + comment: | + Number of data records currently being stored in FIFO 'POS FIFO Monitoring 1' + x-wbgen: + kind: count + - reg: + name: sw_tag + address: 0x000000e8 + width: 32 + access: rw + description: Switching Tag synchronization + comment: | + Switching Tag synchronization + children: + - field: + name: en + range: 0 + description: Tag Synchronization Enable + comment: | + Switching Tag synchronization + write 0: disable tag synchronization + write 1: enable tag synchronization + x-wbgen: + type: BIT + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: desync_cnt_rst + range: 8 + description: Switching Desynchronization Counter Reset + comment: | + Switching Desynchronization Counter Reset + write 0: no change + write 1: reset counter + x-wbgen: + type: MONOSTABLE + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: desync_cnt + range: 22-9 + description: Switching Desynchronization Counter + comment: | + Switching Desynchronization Counter + write: number of samples to delay trigger + read: number of samples being delayed + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - reg: + name: sw_data_mask + address: 0x000000ec + width: 32 + access: rw + description: Switching Data Mask + comment: | + Switching Data Mask + children: + - field: + name: en + range: 0 + description: Switching Data Mask Enable + comment: | + Switching Data Mask Enable + write 0: disable data mask + write 1: enable data mask + x-wbgen: + type: BIT + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: samples + range: 16-1 + description: Switching Data Mask Samples + comment: | + Switching Data Mask Samples + write: number of samples to mask + read: number of samples being masked + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - reg: + name: tbt_tag + address: 0x000000f0 + width: 32 + access: rw + description: TbT Synchronizing Trigger + comment: | + TbT trigger synchronizing trigger. Used for achieving a true TbT + children: + - field: + name: en + range: 0 + description: TbT Synchronizing Trigger Enable + comment: | + TbT Synchronizing Trigger Enable + write 0: disable trigger + write 1: enable trigger + x-wbgen: + type: BIT + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: dly + range: 16-1 + description: TbT Synchronizing Trigger Delay + comment: | + TbT Synchronizing Trigger Delay + write: number of samples to delay trigger + read: number of samples being delayed + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: desync_cnt_rst + range: 17 + description: TbT Desynchronization Counter Reset + comment: | + TbT Desynchronization Counter Reset + write 0: no change + write 1: reset counter + x-wbgen: + type: MONOSTABLE + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: desync_cnt + range: 31-18 + description: TbT Desynchronization Counter + comment: | + TbT Desynchronization Counter + write: number of samples to delay trigger + read: number of samples being delayed + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - reg: + name: tbt_data_mask_ctl + address: 0x000000f4 + width: 32 + access: rw + description: TbT Masking Control + comment: | + TbT Masking Control + children: + - field: + name: en + range: 0 + description: TbT Masking Enable + comment: | + TbT Masking + write 0: disable data mask + write 1: enable data mask + x-wbgen: + type: BIT + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - reg: + name: tbt_data_mask_samples + address: 0x000000f8 + width: 32 + access: rw + description: TbT Data Masking Samples + comment: | + TbT data masking samples. Used for selecting a valid window for TbT. Increases SNR + children: + - field: + name: beg + range: 15-0 + description: TbT Beginning Data Masking Samples + comment: | + Select the number of samples to mask at the beginning of the TbT cycle + write: number of samples to mask + read: number of samples being masked + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: end + range: 31-16 + description: TbT Beginning Data Masking Samples + comment: | + Select the number of samples to mask at the ending of the TbT cycle + write: number of samples to mask + read: number of samples being masked + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - reg: + name: monit1_tag + address: 0x000000fc + width: 32 + access: rw + description: MONIT1 Synchronizing Trigger + comment: | + MONIT1 trigger synchronizing trigger. Used for achieving a true MONIT1 + children: + - field: + name: en + range: 0 + description: MONIT1 Synchronizing Trigger Enable + comment: | + MONIT1 Synchronizing Trigger Enable + write 0: disable trigger + write 1: enable trigger + x-wbgen: + type: BIT + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: dly + range: 16-1 + description: MONIT1 Synchronizing Trigger Delay + comment: | + MONIT1 Synchronizing Trigger Delay + write: number of samples to delay trigger + read: number of samples being delayed + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: desync_cnt_rst + range: 17 + description: MONIT1 Desynchronization Counter Reset + comment: | + MONIT1 Desynchronization Counter Reset + write 0: no change + write 1: reset counter + x-wbgen: + type: MONOSTABLE + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: desync_cnt + range: 31-18 + description: MONIT1 Desynchronization Counter + comment: | + MONIT1 Desynchronization Counter + write: number of samples to delay trigger + read: number of samples being delayed + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - reg: + name: monit1_data_mask_ctl + address: 0x00000100 + width: 32 + access: rw + description: MONIT1 Masking Control + comment: | + MONIT1 Masking Control + children: + - field: + name: en + range: 0 + description: MONIT1 Masking Enable + comment: | + MONIT1 Masking + write 0: disable data mask + write 1: enable data mask + x-wbgen: + type: BIT + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - reg: + name: monit1_data_mask_samples + address: 0x00000104 + width: 32 + access: rw + description: MONIT1 Data Masking Samples + comment: | + MONIT1 data masking samples. Used for selecting a valid window for MONIT1. Increases SNR + children: + - field: + name: beg + range: 15-0 + description: MONIT1 Beginning Data Masking Samples + comment: | + Select the number of samples to mask at the beginning of the MONIT1 cycle + write: number of samples to mask + read: number of samples being masked + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: end + range: 31-16 + description: MONIT1 Beginning Data Masking Samples + comment: | + Select the number of samples to mask at the ending of the MONIT1 cycle + write: number of samples to mask + read: number of samples being masked + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - reg: + name: monit_tag + address: 0x00000108 + width: 32 + access: rw + description: MONIT Synchronizing Trigger + comment: | + MONIT trigger synchronizing trigger. Used for achieving a true MONIT + children: + - field: + name: en + range: 0 + description: MONIT Synchronizing Trigger Enable + comment: | + MONIT Synchronizing Trigger Enable + write 0: disable trigger + write 1: enable trigger + x-wbgen: + type: BIT + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: dly + range: 16-1 + description: MONIT Synchronizing Trigger Delay + comment: | + MONIT Synchronizing Trigger Delay + write: number of samples to delay trigger + read: number of samples being delayed + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: desync_cnt_rst + range: 17 + description: MONIT Desynchronization Counter Reset + comment: | + MONIT Desynchronization Counter Reset + write 0: no change + write 1: reset counter + x-wbgen: + type: MONOSTABLE + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - field: + name: desync_cnt + range: 31-18 + description: MONIT Desynchronization Counter + comment: | + MONIT Desynchronization Counter + write: number of samples to delay trigger + read: number of samples being delayed + x-wbgen: + type: SLV + access_bus: READ_ONLY + access_dev: WRITE_ONLY + clock: fs_clk2x_i + - reg: + name: monit_data_mask_ctl + address: 0x0000010c + width: 32 + access: rw + description: MONIT Masking Control + comment: | + MONIT Masking Control + children: + - field: + name: en + range: 0 + description: MONIT Masking Enable + comment: | + MONIT Masking + write 0: disable data mask + write 1: enable data mask + x-wbgen: + type: BIT + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + size: 1 + - reg: + name: monit_data_mask_samples + address: 0x00000110 + width: 32 + access: rw + description: MONIT Data Masking Samples + comment: | + MONIT data masking samples. Used for selecting a valid window for MONIT. Increases SNR + children: + - field: + name: beg + range: 15-0 + description: MONIT Beginning Data Masking Samples + comment: | + Select the number of samples to mask at the beginning of the MONIT cycle + write: number of samples to mask + read: number of samples being masked + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - field: + name: end + range: 31-16 + description: MONIT Beginning Data Masking Samples + comment: | + Select the number of samples to mask at the ending of the MONIT cycle + write: number of samples to mask + read: number of samples being masked + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i +# -------------------------------------------- +# ----- X/Y position offsets Registers ------ +# -------------------------------------------- + - reg: + name: offset_x + address: 0x00000114 + width: 32 + access: rw + description: BPM X position offset parameter register + comment: | + BPM X position offset to be subtracted from calculated positions + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + field_description: BPM X position offset + field_comment: | + BPM X position offset to be subtracted from calculated positions + - reg: + name: offset_y + address: 0x00000118 + width: 32 + access: rw + description: BPM Y position offset parameter register + comment: | + BPM Y position offset to be subtracted from calculated positions + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + field_description: BPM Y position offset + field_comment: | + BPM Y position offset to be subtracted from calculated positions diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h new file mode 100644 index 00000000..7464232b --- /dev/null +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h @@ -0,0 +1,638 @@ +#ifndef __CHEBY__POS_CALC__H__ +#define __CHEBY__POS_CALC__H__ +#define POS_CALC_SIZE 284 + +/* Config divisor threshold TBT register */ +#define POS_CALC_DS_TBT_THRES 0x0UL +#define POS_CALC_DS_TBT_THRES_VAL_MASK 0x3ffffffUL +#define POS_CALC_DS_TBT_THRES_VAL_SHIFT 0 +#define POS_CALC_DS_TBT_THRES_RESERVED_MASK 0xfc000000UL +#define POS_CALC_DS_TBT_THRES_RESERVED_SHIFT 26 + +/* Config divisor threshold FOFB register */ +#define POS_CALC_DS_FOFB_THRES 0x4UL +#define POS_CALC_DS_FOFB_THRES_VAL_MASK 0x3ffffffUL +#define POS_CALC_DS_FOFB_THRES_VAL_SHIFT 0 +#define POS_CALC_DS_FOFB_THRES_RESERVED_MASK 0xfc000000UL +#define POS_CALC_DS_FOFB_THRES_RESERVED_SHIFT 26 + +/* Config divisor threshold Monit. register */ +#define POS_CALC_DS_MONIT_THRES 0x8UL +#define POS_CALC_DS_MONIT_THRES_VAL_MASK 0x3ffffffUL +#define POS_CALC_DS_MONIT_THRES_VAL_SHIFT 0 +#define POS_CALC_DS_MONIT_THRES_RESERVED_MASK 0xfc000000UL +#define POS_CALC_DS_MONIT_THRES_RESERVED_SHIFT 26 + +/* BPM sensitivity (X axis) parameter register */ +#define POS_CALC_KX 0xcUL +#define POS_CALC_KX_VAL_MASK 0x1ffffffUL +#define POS_CALC_KX_VAL_SHIFT 0 +#define POS_CALC_KX_RESERVED_MASK 0xfe000000UL +#define POS_CALC_KX_RESERVED_SHIFT 25 + +/* BPM sensitivity (Y axis) parameter register */ +#define POS_CALC_KY 0x10UL +#define POS_CALC_KY_VAL_MASK 0x1ffffffUL +#define POS_CALC_KY_VAL_SHIFT 0 +#define POS_CALC_KY_RESERVED_MASK 0xfe000000UL +#define POS_CALC_KY_RESERVED_SHIFT 25 + +/* BPM sensitivity (Sum) parameter register */ +#define POS_CALC_KSUM 0x14UL +#define POS_CALC_KSUM_VAL_MASK 0x1ffffffUL +#define POS_CALC_KSUM_VAL_SHIFT 0 +#define POS_CALC_KSUM_RESERVED_MASK 0xfe000000UL +#define POS_CALC_KSUM_RESERVED_SHIFT 25 + +/* DSP TBT incorrect TDM counter */ +#define POS_CALC_DSP_CTNR_TBT 0x18UL +#define POS_CALC_DSP_CTNR_TBT_CH01_MASK 0xffffUL +#define POS_CALC_DSP_CTNR_TBT_CH01_SHIFT 0 +#define POS_CALC_DSP_CTNR_TBT_CH23_MASK 0xffff0000UL +#define POS_CALC_DSP_CTNR_TBT_CH23_SHIFT 16 + +/* DSP FOFB incorrect TDM counter */ +#define POS_CALC_DSP_CTNR_FOFB 0x1cUL +#define POS_CALC_DSP_CTNR_FOFB_CH01_MASK 0xffffUL +#define POS_CALC_DSP_CTNR_FOFB_CH01_SHIFT 0 +#define POS_CALC_DSP_CTNR_FOFB_CH23_MASK 0xffff0000UL +#define POS_CALC_DSP_CTNR_FOFB_CH23_SHIFT 16 + +/* DSP Monit. incorrect TDM counter part 1 */ +#define POS_CALC_DSP_CTNR1_MONIT 0x20UL +#define POS_CALC_DSP_CTNR1_MONIT_CIC_MASK 0xffffUL +#define POS_CALC_DSP_CTNR1_MONIT_CIC_SHIFT 0 +#define POS_CALC_DSP_CTNR1_MONIT_CFIR_MASK 0xffff0000UL +#define POS_CALC_DSP_CTNR1_MONIT_CFIR_SHIFT 16 + +/* DSP Monit. incorrect TDM counter part 2 */ +#define POS_CALC_DSP_CTNR2_MONIT 0x24UL +#define POS_CALC_DSP_CTNR2_MONIT_PFIR_MASK 0xffffUL +#define POS_CALC_DSP_CTNR2_MONIT_PFIR_SHIFT 0 +#define POS_CALC_DSP_CTNR2_MONIT_FIR_01_MASK 0xffff0000UL +#define POS_CALC_DSP_CTNR2_MONIT_FIR_01_SHIFT 16 + +/* DSP error clearing */ +#define POS_CALC_DSP_ERR_CLR 0x28UL +#define POS_CALC_DSP_ERR_CLR_TBT 0x1UL +#define POS_CALC_DSP_ERR_CLR_FOFB 0x2UL +#define POS_CALC_DSP_ERR_CLR_MONIT_PART1 0x4UL +#define POS_CALC_DSP_ERR_CLR_MONIT_PART2 0x8UL + +/* DDS general config registers for all channels */ +#define POS_CALC_DDS_CFG 0x2cUL +#define POS_CALC_DDS_CFG_VALID_CH0 0x1UL +#define POS_CALC_DDS_CFG_TEST_DATA 0x2UL +#define POS_CALC_DDS_CFG_RESERVED_CH0_MASK 0xfcUL +#define POS_CALC_DDS_CFG_RESERVED_CH0_SHIFT 2 +#define POS_CALC_DDS_CFG_VALID_CH1 0x100UL +#define POS_CALC_DDS_CFG_RESERVED_CH1_MASK 0xfe00UL +#define POS_CALC_DDS_CFG_RESERVED_CH1_SHIFT 9 +#define POS_CALC_DDS_CFG_VALID_CH2 0x10000UL +#define POS_CALC_DDS_CFG_RESERVED_CH2_MASK 0xfe0000UL +#define POS_CALC_DDS_CFG_RESERVED_CH2_SHIFT 17 +#define POS_CALC_DDS_CFG_VALID_CH3 0x1000000UL +#define POS_CALC_DDS_CFG_RESERVED_CH3_MASK 0xfe000000UL +#define POS_CALC_DDS_CFG_RESERVED_CH3_SHIFT 25 + +/* DDS phase increment parameter register for channel 0 */ +#define POS_CALC_DDS_PINC_CH0 0x30UL +#define POS_CALC_DDS_PINC_CH0_VAL_MASK 0x3fffffffUL +#define POS_CALC_DDS_PINC_CH0_VAL_SHIFT 0 +#define POS_CALC_DDS_PINC_CH0_RESERVED_MASK 0xc0000000UL +#define POS_CALC_DDS_PINC_CH0_RESERVED_SHIFT 30 + +/* DDS phase increment parameter register for channel 1 */ +#define POS_CALC_DDS_PINC_CH1 0x34UL +#define POS_CALC_DDS_PINC_CH1_VAL_MASK 0x3fffffffUL +#define POS_CALC_DDS_PINC_CH1_VAL_SHIFT 0 +#define POS_CALC_DDS_PINC_CH1_RESERVED_MASK 0xc0000000UL +#define POS_CALC_DDS_PINC_CH1_RESERVED_SHIFT 30 + +/* DDS phase increment parameter register for channel 2 */ +#define POS_CALC_DDS_PINC_CH2 0x38UL +#define POS_CALC_DDS_PINC_CH2_VAL_MASK 0x3fffffffUL +#define POS_CALC_DDS_PINC_CH2_VAL_SHIFT 0 +#define POS_CALC_DDS_PINC_CH2_RESERVED_MASK 0xc0000000UL +#define POS_CALC_DDS_PINC_CH2_RESERVED_SHIFT 30 + +/* DDS phase increment parameter register for channel 3 */ +#define POS_CALC_DDS_PINC_CH3 0x3cUL +#define POS_CALC_DDS_PINC_CH3_VAL_MASK 0x3fffffffUL +#define POS_CALC_DDS_PINC_CH3_VAL_SHIFT 0 +#define POS_CALC_DDS_PINC_CH3_RESERVED_MASK 0xc0000000UL +#define POS_CALC_DDS_PINC_CH3_RESERVED_SHIFT 30 + +/* DDS phase offset parameter register for channel 0 */ +#define POS_CALC_DDS_POFF_CH0 0x40UL +#define POS_CALC_DDS_POFF_CH0_VAL_MASK 0x3fffffffUL +#define POS_CALC_DDS_POFF_CH0_VAL_SHIFT 0 +#define POS_CALC_DDS_POFF_CH0_RESERVED_MASK 0xc0000000UL +#define POS_CALC_DDS_POFF_CH0_RESERVED_SHIFT 30 + +/* DDS phase offset parameter register for channel 1 */ +#define POS_CALC_DDS_POFF_CH1 0x44UL +#define POS_CALC_DDS_POFF_CH1_VAL_MASK 0x3fffffffUL +#define POS_CALC_DDS_POFF_CH1_VAL_SHIFT 0 +#define POS_CALC_DDS_POFF_CH1_RESERVED_MASK 0xc0000000UL +#define POS_CALC_DDS_POFF_CH1_RESERVED_SHIFT 30 + +/* DDS phase offset parameter register for channel 2 */ +#define POS_CALC_DDS_POFF_CH2 0x48UL +#define POS_CALC_DDS_POFF_CH2_VAL_MASK 0x3fffffffUL +#define POS_CALC_DDS_POFF_CH2_VAL_SHIFT 0 +#define POS_CALC_DDS_POFF_CH2_RESERVED_MASK 0xc0000000UL +#define POS_CALC_DDS_POFF_CH2_RESERVED_SHIFT 30 + +/* DDS phase offset parameter register for channel 3 */ +#define POS_CALC_DDS_POFF_CH3 0x4cUL +#define POS_CALC_DDS_POFF_CH3_VAL_MASK 0x3fffffffUL +#define POS_CALC_DDS_POFF_CH3_VAL_SHIFT 0 +#define POS_CALC_DDS_POFF_CH3_RESERVED_MASK 0xc0000000UL +#define POS_CALC_DDS_POFF_CH3_RESERVED_SHIFT 30 + +/* Monit. Amplitude Value for channel 0 */ +#define POS_CALC_DSP_MONIT_AMP_CH0 0x50UL + +/* Monit. Amplitude Value for channel 1 */ +#define POS_CALC_DSP_MONIT_AMP_CH1 0x54UL + +/* Monit. Amplitude Value for channel 2 */ +#define POS_CALC_DSP_MONIT_AMP_CH2 0x58UL + +/* Monit. Amplitude Value for channel 3 */ +#define POS_CALC_DSP_MONIT_AMP_CH3 0x5cUL + +/* Monit. X Position Value */ +#define POS_CALC_DSP_MONIT_POS_X 0x60UL + +/* Monit. Y Position Value */ +#define POS_CALC_DSP_MONIT_POS_Y 0x64UL + +/* Monit. Q Position Value */ +#define POS_CALC_DSP_MONIT_POS_Q 0x68UL + +/* Monit. Sum Position Value */ +#define POS_CALC_DSP_MONIT_POS_SUM 0x6cUL + +/* Monit. Amp/Pos update trigger */ +#define POS_CALC_DSP_MONIT_UPDT 0x70UL + +/* Monit. 1 Amplitude Value for channel 0 */ +#define POS_CALC_DSP_MONIT1_AMP_CH0 0x74UL + +/* Monit. 1 Amplitude Value for channel 1 */ +#define POS_CALC_DSP_MONIT1_AMP_CH1 0x78UL + +/* Monit. 1 Amplitude Value for channel 2 */ +#define POS_CALC_DSP_MONIT1_AMP_CH2 0x7cUL + +/* Monit. 1 Amplitude Value for channel 3 */ +#define POS_CALC_DSP_MONIT1_AMP_CH3 0x80UL + +/* Monit. 1 X Position Value */ +#define POS_CALC_DSP_MONIT1_POS_X 0x84UL + +/* Monit. 1 Y Position Value */ +#define POS_CALC_DSP_MONIT1_POS_Y 0x88UL + +/* Monit. 1 Q Position Value */ +#define POS_CALC_DSP_MONIT1_POS_Q 0x8cUL + +/* Monit. 1 Sum Position Value */ +#define POS_CALC_DSP_MONIT1_POS_SUM 0x90UL + +/* Monit. 1 Amp/Pos update trigger */ +#define POS_CALC_DSP_MONIT1_UPDT 0x94UL + +/* AMP FIFO Monitoring */ +#define POS_CALC_AMPFIFO_MONIT 0x98UL +#define POS_CALC_AMPFIFO_MONIT_SIZE 20 + +/* FIFO 'AMP FIFO Monitoring' data output register 0 */ +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0 0x98UL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0_AMP_CH0_MASK 0xffffffffUL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0_AMP_CH0_SHIFT 0 + +/* FIFO 'AMP FIFO Monitoring' data output register 1 */ +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1 0x9cUL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1_AMP_CH1_MASK 0xffffffffUL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1_AMP_CH1_SHIFT 0 + +/* FIFO 'AMP FIFO Monitoring' data output register 2 */ +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2 0xa0UL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2_AMP_CH2_MASK 0xffffffffUL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2_AMP_CH2_SHIFT 0 + +/* FIFO 'AMP FIFO Monitoring' data output register 3 */ +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3 0xa4UL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3_AMP_CH3_MASK 0xffffffffUL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3_AMP_CH3_SHIFT 0 + +/* FIFO 'AMP FIFO Monitoring' control/status register */ +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR 0xa8UL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_FULL 0x10000UL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_EMPTY 0x20000UL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_COUNT_MASK 0xfUL +#define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_COUNT_SHIFT 0 + +/* POS FIFO Monitoring */ +#define POS_CALC_POSFIFO_MONIT 0xacUL +#define POS_CALC_POSFIFO_MONIT_SIZE 20 + +/* FIFO 'POS FIFO Monitoring' data output register 0 */ +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0 0xacUL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0_POS_X_MASK 0xffffffffUL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0_POS_X_SHIFT 0 + +/* FIFO 'POS FIFO Monitoring' data output register 1 */ +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1 0xb0UL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1_POS_Y_MASK 0xffffffffUL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1_POS_Y_SHIFT 0 + +/* FIFO 'POS FIFO Monitoring' data output register 2 */ +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2 0xb4UL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2_POS_Q_MASK 0xffffffffUL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2_POS_Q_SHIFT 0 + +/* FIFO 'POS FIFO Monitoring' data output register 3 */ +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3 0xb8UL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3_POS_SUM_MASK 0xffffffffUL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3_POS_SUM_SHIFT 0 + +/* FIFO 'POS FIFO Monitoring' control/status register */ +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR 0xbcUL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_FULL 0x10000UL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_EMPTY 0x20000UL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_COUNT_MASK 0xfUL +#define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_COUNT_SHIFT 0 + +/* AMP FIFO Monitoring 1 */ +#define POS_CALC_AMPFIFO_MONIT1 0xc0UL +#define POS_CALC_AMPFIFO_MONIT1_SIZE 20 + +/* FIFO 'AMP FIFO Monitoring 1' data output register 0 */ +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0 0xc0UL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0_AMP_CH0_MASK 0xffffffffUL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0_AMP_CH0_SHIFT 0 + +/* FIFO 'AMP FIFO Monitoring 1' data output register 1 */ +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1 0xc4UL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1_AMP_CH1_MASK 0xffffffffUL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1_AMP_CH1_SHIFT 0 + +/* FIFO 'AMP FIFO Monitoring 1' data output register 2 */ +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2 0xc8UL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2_AMP_CH2_MASK 0xffffffffUL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2_AMP_CH2_SHIFT 0 + +/* FIFO 'AMP FIFO Monitoring 1' data output register 3 */ +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3 0xccUL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3_AMP_CH3_MASK 0xffffffffUL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3_AMP_CH3_SHIFT 0 + +/* FIFO 'AMP FIFO Monitoring 1' control/status register */ +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR 0xd0UL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_FULL 0x10000UL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_EMPTY 0x20000UL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_COUNT_MASK 0xfUL +#define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_COUNT_SHIFT 0 + +/* POS FIFO Monitoring 1 */ +#define POS_CALC_POSFIFO_MONIT1 0xd4UL +#define POS_CALC_POSFIFO_MONIT1_SIZE 20 + +/* FIFO 'POS FIFO Monitoring 1' data output register 0 */ +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0 0xd4UL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0_POS_X_MASK 0xffffffffUL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0_POS_X_SHIFT 0 + +/* FIFO 'POS FIFO Monitoring 1' data output register 1 */ +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1 0xd8UL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1_POS_Y_MASK 0xffffffffUL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1_POS_Y_SHIFT 0 + +/* FIFO 'POS FIFO Monitoring 1' data output register 2 */ +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2 0xdcUL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2_POS_Q_MASK 0xffffffffUL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2_POS_Q_SHIFT 0 + +/* FIFO 'POS FIFO Monitoring 1' data output register 3 */ +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3 0xe0UL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3_POS_SUM_MASK 0xffffffffUL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3_POS_SUM_SHIFT 0 + +/* FIFO 'POS FIFO Monitoring 1' control/status register */ +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR 0xe4UL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_FULL 0x10000UL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_EMPTY 0x20000UL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_COUNT_MASK 0xfUL +#define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_COUNT_SHIFT 0 + +/* Switching Tag synchronization */ +#define POS_CALC_SW_TAG 0xe8UL +#define POS_CALC_SW_TAG_EN 0x1UL +#define POS_CALC_SW_TAG_DESYNC_CNT_RST 0x100UL +#define POS_CALC_SW_TAG_DESYNC_CNT_MASK 0x7ffe00UL +#define POS_CALC_SW_TAG_DESYNC_CNT_SHIFT 9 + +/* Switching Data Mask */ +#define POS_CALC_SW_DATA_MASK 0xecUL +#define POS_CALC_SW_DATA_MASK_EN 0x1UL +#define POS_CALC_SW_DATA_MASK_SAMPLES_MASK 0x1fffeUL +#define POS_CALC_SW_DATA_MASK_SAMPLES_SHIFT 1 + +/* TbT Synchronizing Trigger */ +#define POS_CALC_TBT_TAG 0xf0UL +#define POS_CALC_TBT_TAG_EN 0x1UL +#define POS_CALC_TBT_TAG_DLY_MASK 0x1fffeUL +#define POS_CALC_TBT_TAG_DLY_SHIFT 1 +#define POS_CALC_TBT_TAG_DESYNC_CNT_RST 0x20000UL +#define POS_CALC_TBT_TAG_DESYNC_CNT_MASK 0xfffc0000UL +#define POS_CALC_TBT_TAG_DESYNC_CNT_SHIFT 18 + +/* TbT Masking Control */ +#define POS_CALC_TBT_DATA_MASK_CTL 0xf4UL +#define POS_CALC_TBT_DATA_MASK_CTL_EN 0x1UL + +/* TbT Data Masking Samples */ +#define POS_CALC_TBT_DATA_MASK_SAMPLES 0xf8UL +#define POS_CALC_TBT_DATA_MASK_SAMPLES_BEG_MASK 0xffffUL +#define POS_CALC_TBT_DATA_MASK_SAMPLES_BEG_SHIFT 0 +#define POS_CALC_TBT_DATA_MASK_SAMPLES_END_MASK 0xffff0000UL +#define POS_CALC_TBT_DATA_MASK_SAMPLES_END_SHIFT 16 + +/* MONIT1 Synchronizing Trigger */ +#define POS_CALC_MONIT1_TAG 0xfcUL +#define POS_CALC_MONIT1_TAG_EN 0x1UL +#define POS_CALC_MONIT1_TAG_DLY_MASK 0x1fffeUL +#define POS_CALC_MONIT1_TAG_DLY_SHIFT 1 +#define POS_CALC_MONIT1_TAG_DESYNC_CNT_RST 0x20000UL +#define POS_CALC_MONIT1_TAG_DESYNC_CNT_MASK 0xfffc0000UL +#define POS_CALC_MONIT1_TAG_DESYNC_CNT_SHIFT 18 + +/* MONIT1 Masking Control */ +#define POS_CALC_MONIT1_DATA_MASK_CTL 0x100UL +#define POS_CALC_MONIT1_DATA_MASK_CTL_EN 0x1UL + +/* MONIT1 Data Masking Samples */ +#define POS_CALC_MONIT1_DATA_MASK_SAMPLES 0x104UL +#define POS_CALC_MONIT1_DATA_MASK_SAMPLES_BEG_MASK 0xffffUL +#define POS_CALC_MONIT1_DATA_MASK_SAMPLES_BEG_SHIFT 0 +#define POS_CALC_MONIT1_DATA_MASK_SAMPLES_END_MASK 0xffff0000UL +#define POS_CALC_MONIT1_DATA_MASK_SAMPLES_END_SHIFT 16 + +/* MONIT Synchronizing Trigger */ +#define POS_CALC_MONIT_TAG 0x108UL +#define POS_CALC_MONIT_TAG_EN 0x1UL +#define POS_CALC_MONIT_TAG_DLY_MASK 0x1fffeUL +#define POS_CALC_MONIT_TAG_DLY_SHIFT 1 +#define POS_CALC_MONIT_TAG_DESYNC_CNT_RST 0x20000UL +#define POS_CALC_MONIT_TAG_DESYNC_CNT_MASK 0xfffc0000UL +#define POS_CALC_MONIT_TAG_DESYNC_CNT_SHIFT 18 + +/* MONIT Masking Control */ +#define POS_CALC_MONIT_DATA_MASK_CTL 0x10cUL +#define POS_CALC_MONIT_DATA_MASK_CTL_EN 0x1UL + +/* MONIT Data Masking Samples */ +#define POS_CALC_MONIT_DATA_MASK_SAMPLES 0x110UL +#define POS_CALC_MONIT_DATA_MASK_SAMPLES_BEG_MASK 0xffffUL +#define POS_CALC_MONIT_DATA_MASK_SAMPLES_BEG_SHIFT 0 +#define POS_CALC_MONIT_DATA_MASK_SAMPLES_END_MASK 0xffff0000UL +#define POS_CALC_MONIT_DATA_MASK_SAMPLES_END_SHIFT 16 + +/* BPM X position offset parameter register */ +#define POS_CALC_OFFSET_X 0x114UL + +/* BPM Y position offset parameter register */ +#define POS_CALC_OFFSET_Y 0x118UL + +struct pos_calc { + /* [0x0]: REG (rw) Config divisor threshold TBT register */ + uint32_t ds_tbt_thres; + + /* [0x4]: REG (rw) Config divisor threshold FOFB register */ + uint32_t ds_fofb_thres; + + /* [0x8]: REG (rw) Config divisor threshold Monit. register */ + uint32_t ds_monit_thres; + + /* [0xc]: REG (rw) BPM sensitivity (X axis) parameter register */ + uint32_t kx; + + /* [0x10]: REG (rw) BPM sensitivity (Y axis) parameter register */ + uint32_t ky; + + /* [0x14]: REG (rw) BPM sensitivity (Sum) parameter register */ + uint32_t ksum; + + /* [0x18]: REG (ro) DSP TBT incorrect TDM counter */ + uint32_t dsp_ctnr_tbt; + + /* [0x1c]: REG (ro) DSP FOFB incorrect TDM counter */ + uint32_t dsp_ctnr_fofb; + + /* [0x20]: REG (ro) DSP Monit. incorrect TDM counter part 1 */ + uint32_t dsp_ctnr1_monit; + + /* [0x24]: REG (ro) DSP Monit. incorrect TDM counter part 2 */ + uint32_t dsp_ctnr2_monit; + + /* [0x28]: REG (wo) DSP error clearing */ + uint32_t dsp_err_clr; + + /* [0x2c]: REG (rw) DDS general config registers for all channels */ + uint32_t dds_cfg; + + /* [0x30]: REG (rw) DDS phase increment parameter register for channel 0 */ + uint32_t dds_pinc_ch0; + + /* [0x34]: REG (rw) DDS phase increment parameter register for channel 1 */ + uint32_t dds_pinc_ch1; + + /* [0x38]: REG (rw) DDS phase increment parameter register for channel 2 */ + uint32_t dds_pinc_ch2; + + /* [0x3c]: REG (rw) DDS phase increment parameter register for channel 3 */ + uint32_t dds_pinc_ch3; + + /* [0x40]: REG (rw) DDS phase offset parameter register for channel 0 */ + uint32_t dds_poff_ch0; + + /* [0x44]: REG (rw) DDS phase offset parameter register for channel 1 */ + uint32_t dds_poff_ch1; + + /* [0x48]: REG (rw) DDS phase offset parameter register for channel 2 */ + uint32_t dds_poff_ch2; + + /* [0x4c]: REG (rw) DDS phase offset parameter register for channel 3 */ + uint32_t dds_poff_ch3; + + /* [0x50]: REG (ro) Monit. Amplitude Value for channel 0 */ + uint32_t dsp_monit_amp_ch0; + + /* [0x54]: REG (ro) Monit. Amplitude Value for channel 1 */ + uint32_t dsp_monit_amp_ch1; + + /* [0x58]: REG (ro) Monit. Amplitude Value for channel 2 */ + uint32_t dsp_monit_amp_ch2; + + /* [0x5c]: REG (ro) Monit. Amplitude Value for channel 3 */ + uint32_t dsp_monit_amp_ch3; + + /* [0x60]: REG (ro) Monit. X Position Value */ + uint32_t dsp_monit_pos_x; + + /* [0x64]: REG (ro) Monit. Y Position Value */ + uint32_t dsp_monit_pos_y; + + /* [0x68]: REG (ro) Monit. Q Position Value */ + uint32_t dsp_monit_pos_q; + + /* [0x6c]: REG (ro) Monit. Sum Position Value */ + uint32_t dsp_monit_pos_sum; + + /* [0x70]: REG (wo) Monit. Amp/Pos update trigger */ + uint32_t dsp_monit_updt; + + /* [0x74]: REG (ro) Monit. 1 Amplitude Value for channel 0 */ + uint32_t dsp_monit1_amp_ch0; + + /* [0x78]: REG (ro) Monit. 1 Amplitude Value for channel 1 */ + uint32_t dsp_monit1_amp_ch1; + + /* [0x7c]: REG (ro) Monit. 1 Amplitude Value for channel 2 */ + uint32_t dsp_monit1_amp_ch2; + + /* [0x80]: REG (ro) Monit. 1 Amplitude Value for channel 3 */ + uint32_t dsp_monit1_amp_ch3; + + /* [0x84]: REG (ro) Monit. 1 X Position Value */ + uint32_t dsp_monit1_pos_x; + + /* [0x88]: REG (ro) Monit. 1 Y Position Value */ + uint32_t dsp_monit1_pos_y; + + /* [0x8c]: REG (ro) Monit. 1 Q Position Value */ + uint32_t dsp_monit1_pos_q; + + /* [0x90]: REG (ro) Monit. 1 Sum Position Value */ + uint32_t dsp_monit1_pos_sum; + + /* [0x94]: REG (wo) Monit. 1 Amp/Pos update trigger */ + uint32_t dsp_monit1_updt; + + /* [0x98]: BLOCK AMP FIFO Monitoring */ + struct ampfifo_monit { + /* [0x0]: REG (ro) FIFO 'AMP FIFO Monitoring' data output register 0 */ + uint32_t ampfifo_monit_r0; + + /* [0x4]: REG (ro) FIFO 'AMP FIFO Monitoring' data output register 1 */ + uint32_t ampfifo_monit_r1; + + /* [0x8]: REG (ro) FIFO 'AMP FIFO Monitoring' data output register 2 */ + uint32_t ampfifo_monit_r2; + + /* [0xc]: REG (ro) FIFO 'AMP FIFO Monitoring' data output register 3 */ + uint32_t ampfifo_monit_r3; + + /* [0x10]: REG (ro) FIFO 'AMP FIFO Monitoring' control/status register */ + uint32_t ampfifo_monit_csr; + } ampfifo_monit; + + /* [0xac]: BLOCK POS FIFO Monitoring */ + struct posfifo_monit { + /* [0x0]: REG (ro) FIFO 'POS FIFO Monitoring' data output register 0 */ + uint32_t posfifo_monit_r0; + + /* [0x4]: REG (ro) FIFO 'POS FIFO Monitoring' data output register 1 */ + uint32_t posfifo_monit_r1; + + /* [0x8]: REG (ro) FIFO 'POS FIFO Monitoring' data output register 2 */ + uint32_t posfifo_monit_r2; + + /* [0xc]: REG (ro) FIFO 'POS FIFO Monitoring' data output register 3 */ + uint32_t posfifo_monit_r3; + + /* [0x10]: REG (ro) FIFO 'POS FIFO Monitoring' control/status register */ + uint32_t posfifo_monit_csr; + } posfifo_monit; + + /* [0xc0]: BLOCK AMP FIFO Monitoring 1 */ + struct ampfifo_monit1 { + /* [0x0]: REG (ro) FIFO 'AMP FIFO Monitoring 1' data output register 0 */ + uint32_t ampfifo_monit1_r0; + + /* [0x4]: REG (ro) FIFO 'AMP FIFO Monitoring 1' data output register 1 */ + uint32_t ampfifo_monit1_r1; + + /* [0x8]: REG (ro) FIFO 'AMP FIFO Monitoring 1' data output register 2 */ + uint32_t ampfifo_monit1_r2; + + /* [0xc]: REG (ro) FIFO 'AMP FIFO Monitoring 1' data output register 3 */ + uint32_t ampfifo_monit1_r3; + + /* [0x10]: REG (ro) FIFO 'AMP FIFO Monitoring 1' control/status register */ + uint32_t ampfifo_monit1_csr; + } ampfifo_monit1; + + /* [0xd4]: BLOCK POS FIFO Monitoring 1 */ + struct posfifo_monit1 { + /* [0x0]: REG (ro) FIFO 'POS FIFO Monitoring 1' data output register 0 */ + uint32_t posfifo_monit1_r0; + + /* [0x4]: REG (ro) FIFO 'POS FIFO Monitoring 1' data output register 1 */ + uint32_t posfifo_monit1_r1; + + /* [0x8]: REG (ro) FIFO 'POS FIFO Monitoring 1' data output register 2 */ + uint32_t posfifo_monit1_r2; + + /* [0xc]: REG (ro) FIFO 'POS FIFO Monitoring 1' data output register 3 */ + uint32_t posfifo_monit1_r3; + + /* [0x10]: REG (ro) FIFO 'POS FIFO Monitoring 1' control/status register */ + uint32_t posfifo_monit1_csr; + } posfifo_monit1; + + /* [0xe8]: REG (rw) Switching Tag synchronization */ + uint32_t sw_tag; + + /* [0xec]: REG (rw) Switching Data Mask */ + uint32_t sw_data_mask; + + /* [0xf0]: REG (rw) TbT Synchronizing Trigger */ + uint32_t tbt_tag; + + /* [0xf4]: REG (rw) TbT Masking Control */ + uint32_t tbt_data_mask_ctl; + + /* [0xf8]: REG (rw) TbT Data Masking Samples */ + uint32_t tbt_data_mask_samples; + + /* [0xfc]: REG (rw) MONIT1 Synchronizing Trigger */ + uint32_t monit1_tag; + + /* [0x100]: REG (rw) MONIT1 Masking Control */ + uint32_t monit1_data_mask_ctl; + + /* [0x104]: REG (rw) MONIT1 Data Masking Samples */ + uint32_t monit1_data_mask_samples; + + /* [0x108]: REG (rw) MONIT Synchronizing Trigger */ + uint32_t monit_tag; + + /* [0x10c]: REG (rw) MONIT Masking Control */ + uint32_t monit_data_mask_ctl; + + /* [0x110]: REG (rw) MONIT Data Masking Samples */ + uint32_t monit_data_mask_samples; + + /* [0x114]: REG (rw) BPM X position offset parameter register */ + uint32_t offset_x; + + /* [0x118]: REG (rw) BPM Y position offset parameter register */ + uint32_t offset_y; +}; + +#endif /* __CHEBY__POS_CALC__H__ */ diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd new file mode 100644 index 00000000..b7cab18f --- /dev/null +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd @@ -0,0 +1,3282 @@ +------------------------------------------------------------------------------- +-- Title : Wishbone slave core for Position Calculation Core registers +------------------------------------------------------------------------------- +-- File : wb_pos_calc_regs.vhdl +-- Author : auto-generated by wbgen2 from wb_pos_calc_regs.wb +-- Created : Fri Aug 21 09:53:04 2020 +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_pos_calc_regs.wb +-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wbgen2_pkg.all; + +entity wb_pos_calc_regs is + port ( + rst_n_i : in std_logic; + clk_sys_i : in std_logic; + wb_adr_i : in std_logic_vector(6 downto 0); + wb_dat_i : in std_logic_vector(31 downto 0); + wb_dat_o : out std_logic_vector(31 downto 0); + wb_cyc_i : in std_logic; + wb_sel_i : in std_logic_vector(3 downto 0); + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_ack_o : out std_logic; + wb_stall_o : out std_logic; + fs_clk2x_i : in std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'Config divisor threshold TBT' in reg: 'Config divisor threshold TBT register' + pos_calc_ds_tbt_thres_val_o : out std_logic_vector(25 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'Config divisor threshold TBT register' + pos_calc_ds_tbt_thres_reserved_i : in std_logic_vector(5 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'Config divisor threshold FOFB' in reg: 'Config divisor threshold FOFB register' + pos_calc_ds_fofb_thres_val_o : out std_logic_vector(25 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'Config divisor threshold FOFB register' + pos_calc_ds_fofb_thres_reserved_i : in std_logic_vector(5 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'Config Divisor Threshold Monit.' in reg: 'Config divisor threshold Monit. register' + pos_calc_ds_monit_thres_val_o : out std_logic_vector(25 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'Config divisor threshold Monit. register' + pos_calc_ds_monit_thres_reserved_i : in std_logic_vector(5 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'BPM sensitivity (X axis) parameter register' in reg: 'BPM sensitivity (X axis) parameter register' + pos_calc_kx_val_o : out std_logic_vector(24 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'BPM sensitivity (X axis) parameter register' + pos_calc_kx_reserved_i : in std_logic_vector(6 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'BPM sensitivity (Y axis) parameter register' in reg: 'BPM sensitivity (Y axis) parameter register' + pos_calc_ky_val_o : out std_logic_vector(24 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'BPM sensitivity (Y axis) parameter register' + pos_calc_ky_reserved_i : in std_logic_vector(6 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'BPM sensitivity (Sum) parameter register' in reg: 'BPM sensitivity (Sum) parameter register' + pos_calc_ksum_val_o : out std_logic_vector(24 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'BPM sensitivity (Sum) parameter register' + pos_calc_ksum_reserved_i : in std_logic_vector(6 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'TBT incorrect counter for channels 0/1 (multiplexed)' in reg: 'DSP TBT incorrect TDM counter' + pos_calc_dsp_ctnr_tbt_ch01_i : in std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'TBT incorrect counter for channels 2/3 (multiplexed)' in reg: 'DSP TBT incorrect TDM counter' + pos_calc_dsp_ctnr_tbt_ch23_i : in std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'FOFB incorrect counter for channels 0/1 (multiplexed)' in reg: 'DSP FOFB incorrect TDM counter' + pos_calc_dsp_ctnr_fofb_ch01_i : in std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'FOFB incorrect counter for channels 2/3 (multiplexed)' in reg: 'DSP FOFB incorrect TDM counter' + pos_calc_dsp_ctnr_fofb_ch23_i : in std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'Monit. CIC incorrect counter for channels 0/1/2/3 (multiplexed)' in reg: 'DSP Monit. incorrect TDM counter part 1' + pos_calc_dsp_ctnr1_monit_cic_i : in std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'Monit. CFIR incorrect counter for channels 0/1/2/3 (multiplexed)' in reg: 'DSP Monit. incorrect TDM counter part 1' + pos_calc_dsp_ctnr1_monit_cfir_i : in std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'Monit. PFIR incorrect counter for channels 0/1/2/3 (multiplexed)' in reg: 'DSP Monit. incorrect TDM counter part 2' + pos_calc_dsp_ctnr2_monit_pfir_i : in std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'Monit. 0.1 Hz incorrect counter for channels 0/1/2/3 (multiplexed)' in reg: 'DSP Monit. incorrect TDM counter part 2' + pos_calc_dsp_ctnr2_monit_fir_01_i : in std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'Clear TBT error counters' in reg: 'DSP error clearing' + pos_calc_dsp_err_clr_tbt_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'Clear FOFB error counters' in reg: 'DSP error clearing' + pos_calc_dsp_err_clr_fofb_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'Clear Monit. CIC and CFIR error counters' in reg: 'DSP error clearing' + pos_calc_dsp_err_clr_monit_part1_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'Clear Monit. PFIR and Monit. 0.1 error counters' in reg: 'DSP error clearing' + pos_calc_dsp_err_clr_monit_part2_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'Valid signal for channel 0 DDS' in reg: 'DDS general config registers for all channels' + pos_calc_dds_cfg_valid_ch0_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) BIT field: 'Test data counter for all channels' in reg: 'DDS general config registers for all channels' + pos_calc_dds_cfg_test_data_o : out std_logic; + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS general config registers for all channels' + pos_calc_dds_cfg_reserved_ch0_i : in std_logic_vector(5 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'Valid signal for channel 1 DDS' in reg: 'DDS general config registers for all channels' + pos_calc_dds_cfg_valid_ch1_o : out std_logic; + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS general config registers for all channels' + pos_calc_dds_cfg_reserved_ch1_i : in std_logic_vector(6 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'Valid signal for channel 2 DDS' in reg: 'DDS general config registers for all channels' + pos_calc_dds_cfg_valid_ch2_o : out std_logic; + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS general config registers for all channels' + pos_calc_dds_cfg_reserved_ch2_i : in std_logic_vector(6 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'Valid signal for channel 3 DDS' in reg: 'DDS general config registers for all channels' + pos_calc_dds_cfg_valid_ch3_o : out std_logic; + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS general config registers for all channels' + pos_calc_dds_cfg_reserved_ch3_i : in std_logic_vector(6 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'DDS phase increment parameter register for channel 0' in reg: 'DDS phase increment parameter register for channel 0' + pos_calc_dds_pinc_ch0_val_o : out std_logic_vector(29 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS phase increment parameter register for channel 0' + pos_calc_dds_pinc_ch0_reserved_i : in std_logic_vector(1 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'DDS phase increment parameter register for channel 1' in reg: 'DDS phase increment parameter register for channel 1' + pos_calc_dds_pinc_ch1_val_o : out std_logic_vector(29 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS phase increment parameter register for channel 1' + pos_calc_dds_pinc_ch1_reserved_i : in std_logic_vector(1 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'DDS phase increment parameter register for channel 2' in reg: 'DDS phase increment parameter register for channel 2' + pos_calc_dds_pinc_ch2_val_o : out std_logic_vector(29 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS phase increment parameter register for channel 2' + pos_calc_dds_pinc_ch2_reserved_i : in std_logic_vector(1 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'DDS phase increment parameter register for channel 3' in reg: 'DDS phase increment parameter register for channel 3' + pos_calc_dds_pinc_ch3_val_o : out std_logic_vector(29 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS phase increment parameter register for channel 3' + pos_calc_dds_pinc_ch3_reserved_i : in std_logic_vector(1 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'DDS phase offset parameter register for channel 0' in reg: 'DDS phase offset parameter register for channel 0' + pos_calc_dds_poff_ch0_val_o : out std_logic_vector(29 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS phase offset parameter register for channel 0' + pos_calc_dds_poff_ch0_reserved_i : in std_logic_vector(1 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'DDS phase offset parameter register for channel 1' in reg: 'DDS phase offset parameter register for channel 1' + pos_calc_dds_poff_ch1_val_o : out std_logic_vector(29 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS phase offset parameter register for channel 1' + pos_calc_dds_poff_ch1_reserved_i : in std_logic_vector(1 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'DDS phase offset parameter register for channel 2' in reg: 'DDS phase offset parameter register for channel 2' + pos_calc_dds_poff_ch2_val_o : out std_logic_vector(29 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS phase offset parameter register for channel 2' + pos_calc_dds_poff_ch2_reserved_i : in std_logic_vector(1 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'DDS phase offset parameter register for channel 3' in reg: 'DDS phase offset parameter register for channel 3' + pos_calc_dds_poff_ch3_val_o : out std_logic_vector(29 downto 0); + -- Port for std_logic_vector field: 'Reserved' in reg: 'DDS phase offset parameter register for channel 3' + pos_calc_dds_poff_ch3_reserved_i : in std_logic_vector(1 downto 0); + -- Port for std_logic_vector field: 'Monit. Amplitude Value for channel 0' in reg: 'Monit. Amplitude Value for channel 0' + pos_calc_dsp_monit_amp_ch0_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. Amplitude Value for channel 1' in reg: 'Monit. Amplitude Value for channel 1' + pos_calc_dsp_monit_amp_ch1_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. Amplitude Value for channel 2' in reg: 'Monit. Amplitude Value for channel 2' + pos_calc_dsp_monit_amp_ch2_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. Amplitude Value for channel 3' in reg: 'Monit. Amplitude Value for channel 3' + pos_calc_dsp_monit_amp_ch3_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. X Position Value' in reg: 'Monit. X Position Value' + pos_calc_dsp_monit_pos_x_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. Y Position Value' in reg: 'Monit. Y Position Value' + pos_calc_dsp_monit_pos_y_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. Q Position Value' in reg: 'Monit. Q Position Value' + pos_calc_dsp_monit_pos_q_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. Sum Position Value' in reg: 'Monit. Sum Position Value' + pos_calc_dsp_monit_pos_sum_i : in std_logic_vector(31 downto 0); + -- Ports for PASS_THROUGH field: 'Monit. Amp/Pos Update (ignore on read)' in reg: 'Monit. Amp/Pos update trigger' + pos_calc_dsp_monit_updt_o : out std_logic_vector(31 downto 0); + pos_calc_dsp_monit_updt_wr_o : out std_logic; + -- Port for std_logic_vector field: 'Monit. 1 Amplitude Value for channel 0' in reg: 'Monit. 1 Amplitude Value for channel 0' + pos_calc_dsp_monit1_amp_ch0_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. 1 Amplitude Value for channel 1' in reg: 'Monit. 1 Amplitude Value for channel 1' + pos_calc_dsp_monit1_amp_ch1_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. 1 Amplitude Value for channel 2' in reg: 'Monit. 1 Amplitude Value for channel 2' + pos_calc_dsp_monit1_amp_ch2_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. 1 Amplitude Value for channel 3' in reg: 'Monit. 1 Amplitude Value for channel 3' + pos_calc_dsp_monit1_amp_ch3_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. 1 X Position Value' in reg: 'Monit. 1 X Position Value' + pos_calc_dsp_monit1_pos_x_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. 1 Y Position Value' in reg: 'Monit. 1 Y Position Value' + pos_calc_dsp_monit1_pos_y_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. 1 Q Position Value' in reg: 'Monit. 1 Q Position Value' + pos_calc_dsp_monit1_pos_q_i : in std_logic_vector(31 downto 0); + -- Port for std_logic_vector field: 'Monit. 1 Sum Position Value' in reg: 'Monit. 1 Sum Position Value' + pos_calc_dsp_monit1_pos_sum_i : in std_logic_vector(31 downto 0); + -- Ports for PASS_THROUGH field: 'Monit. 1 Amp/Pos Update (ignore on read)' in reg: 'Monit. 1 Amp/Pos update trigger' + pos_calc_dsp_monit1_updt_o : out std_logic_vector(31 downto 0); + pos_calc_dsp_monit1_updt_wr_o : out std_logic; + -- FIFO write request + pos_calc_ampfifo_monit_wr_req_i : in std_logic; + -- FIFO full flag + pos_calc_ampfifo_monit_wr_full_o : out std_logic; + -- FIFO empty flag + pos_calc_ampfifo_monit_wr_empty_o : out std_logic; + -- FIFO number of used words + pos_calc_ampfifo_monit_wr_usedw_o : out std_logic_vector(3 downto 0); + pos_calc_ampfifo_monit_amp_ch0_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit_amp_ch1_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit_amp_ch2_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit_amp_ch3_i : in std_logic_vector(31 downto 0); + -- FIFO write request + pos_calc_posfifo_monit_wr_req_i : in std_logic; + -- FIFO full flag + pos_calc_posfifo_monit_wr_full_o : out std_logic; + -- FIFO empty flag + pos_calc_posfifo_monit_wr_empty_o : out std_logic; + -- FIFO number of used words + pos_calc_posfifo_monit_wr_usedw_o : out std_logic_vector(3 downto 0); + pos_calc_posfifo_monit_pos_x_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit_pos_y_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit_pos_q_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit_pos_sum_i : in std_logic_vector(31 downto 0); + -- FIFO write request + pos_calc_ampfifo_monit1_wr_req_i : in std_logic; + -- FIFO full flag + pos_calc_ampfifo_monit1_wr_full_o : out std_logic; + -- FIFO empty flag + pos_calc_ampfifo_monit1_wr_empty_o : out std_logic; + -- FIFO number of used words + pos_calc_ampfifo_monit1_wr_usedw_o : out std_logic_vector(3 downto 0); + pos_calc_ampfifo_monit1_amp_ch0_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit1_amp_ch1_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit1_amp_ch2_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit1_amp_ch3_i : in std_logic_vector(31 downto 0); + -- FIFO write request + pos_calc_posfifo_monit1_wr_req_i : in std_logic; + -- FIFO full flag + pos_calc_posfifo_monit1_wr_full_o : out std_logic; + -- FIFO empty flag + pos_calc_posfifo_monit1_wr_empty_o : out std_logic; + -- FIFO number of used words + pos_calc_posfifo_monit1_wr_usedw_o : out std_logic_vector(3 downto 0); + pos_calc_posfifo_monit1_pos_x_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit1_pos_y_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit1_pos_q_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit1_pos_sum_i : in std_logic_vector(31 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) BIT field: 'Tag Synchronization Enable' in reg: 'Switching Tag synchronization' + pos_calc_sw_tag_en_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'Switching Desynchronization Counter Reset' in reg: 'Switching Tag synchronization' + pos_calc_sw_tag_desync_cnt_rst_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'Switching Desynchronization Counter' in reg: 'Switching Tag synchronization' + pos_calc_sw_tag_desync_cnt_i : in std_logic_vector(13 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) BIT field: 'Switching Data Mask Enable' in reg: 'Switching Data Mask' + pos_calc_sw_data_mask_en_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'Switching Data Mask Samples' in reg: 'Switching Data Mask' + pos_calc_sw_data_mask_samples_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) BIT field: 'TbT Synchronizing Trigger Enable' in reg: 'TbT Synchronizing Trigger' + pos_calc_tbt_tag_en_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'TbT Synchronizing Trigger Delay' in reg: 'TbT Synchronizing Trigger' + pos_calc_tbt_tag_dly_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'TbT Desynchronization Counter Reset' in reg: 'TbT Synchronizing Trigger' + pos_calc_tbt_tag_desync_cnt_rst_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'TbT Desynchronization Counter' in reg: 'TbT Synchronizing Trigger' + pos_calc_tbt_tag_desync_cnt_i : in std_logic_vector(13 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) BIT field: 'TbT Masking Enable' in reg: 'TbT Masking Control' + pos_calc_tbt_data_mask_ctl_en_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'TbT Beginning Data Masking Samples' in reg: 'TbT Data Masking Samples' + pos_calc_tbt_data_mask_samples_beg_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'TbT Beginning Data Masking Samples' in reg: 'TbT Data Masking Samples' + pos_calc_tbt_data_mask_samples_end_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) BIT field: 'MONIT1 Synchronizing Trigger Enable' in reg: 'MONIT1 Synchronizing Trigger' + pos_calc_monit1_tag_en_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'MONIT1 Synchronizing Trigger Delay' in reg: 'MONIT1 Synchronizing Trigger' + pos_calc_monit1_tag_dly_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'MONIT1 Desynchronization Counter Reset' in reg: 'MONIT1 Synchronizing Trigger' + pos_calc_monit1_tag_desync_cnt_rst_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'MONIT1 Desynchronization Counter' in reg: 'MONIT1 Synchronizing Trigger' + pos_calc_monit1_tag_desync_cnt_i : in std_logic_vector(13 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) BIT field: 'MONIT1 Masking Enable' in reg: 'MONIT1 Masking Control' + pos_calc_monit1_data_mask_ctl_en_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'MONIT1 Beginning Data Masking Samples' in reg: 'MONIT1 Data Masking Samples' + pos_calc_monit1_data_mask_samples_beg_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'MONIT1 Beginning Data Masking Samples' in reg: 'MONIT1 Data Masking Samples' + pos_calc_monit1_data_mask_samples_end_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) BIT field: 'MONIT Synchronizing Trigger Enable' in reg: 'MONIT Synchronizing Trigger' + pos_calc_monit_tag_en_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'MONIT Synchronizing Trigger Delay' in reg: 'MONIT Synchronizing Trigger' + pos_calc_monit_tag_dly_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) MONOSTABLE field: 'MONIT Desynchronization Counter Reset' in reg: 'MONIT Synchronizing Trigger' + pos_calc_monit_tag_desync_cnt_rst_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'MONIT Desynchronization Counter' in reg: 'MONIT Synchronizing Trigger' + pos_calc_monit_tag_desync_cnt_i : in std_logic_vector(13 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) BIT field: 'MONIT Masking Enable' in reg: 'MONIT Masking Control' + pos_calc_monit_data_mask_ctl_en_o : out std_logic; + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'MONIT Beginning Data Masking Samples' in reg: 'MONIT Data Masking Samples' + pos_calc_monit_data_mask_samples_beg_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'MONIT Beginning Data Masking Samples' in reg: 'MONIT Data Masking Samples' + pos_calc_monit_data_mask_samples_end_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'BPM X position offset' in reg: 'BPM X position offset parameter register' + pos_calc_offset_x_o : out std_logic_vector(31 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'BPM Y position offset' in reg: 'BPM Y position offset parameter register' + pos_calc_offset_y_o : out std_logic_vector(31 downto 0) + ); +end wb_pos_calc_regs; + +architecture syn of wb_pos_calc_regs is + + signal pos_calc_ds_tbt_thres_val_int : std_logic_vector(25 downto 0); + signal pos_calc_ds_tbt_thres_val_swb : std_logic; + signal pos_calc_ds_tbt_thres_val_swb_delay : std_logic; + signal pos_calc_ds_tbt_thres_val_swb_s0 : std_logic; + signal pos_calc_ds_tbt_thres_val_swb_s1 : std_logic; + signal pos_calc_ds_tbt_thres_val_swb_s2 : std_logic; + signal pos_calc_ds_fofb_thres_val_int : std_logic_vector(25 downto 0); + signal pos_calc_ds_fofb_thres_val_swb : std_logic; + signal pos_calc_ds_fofb_thres_val_swb_delay : std_logic; + signal pos_calc_ds_fofb_thres_val_swb_s0 : std_logic; + signal pos_calc_ds_fofb_thres_val_swb_s1 : std_logic; + signal pos_calc_ds_fofb_thres_val_swb_s2 : std_logic; + signal pos_calc_ds_monit_thres_val_int : std_logic_vector(25 downto 0); + signal pos_calc_ds_monit_thres_val_swb : std_logic; + signal pos_calc_ds_monit_thres_val_swb_delay : std_logic; + signal pos_calc_ds_monit_thres_val_swb_s0 : std_logic; + signal pos_calc_ds_monit_thres_val_swb_s1 : std_logic; + signal pos_calc_ds_monit_thres_val_swb_s2 : std_logic; + signal pos_calc_kx_val_int : std_logic_vector(24 downto 0); + signal pos_calc_kx_val_swb : std_logic; + signal pos_calc_kx_val_swb_delay : std_logic; + signal pos_calc_kx_val_swb_s0 : std_logic; + signal pos_calc_kx_val_swb_s1 : std_logic; + signal pos_calc_kx_val_swb_s2 : std_logic; + signal pos_calc_ky_val_int : std_logic_vector(24 downto 0); + signal pos_calc_ky_val_swb : std_logic; + signal pos_calc_ky_val_swb_delay : std_logic; + signal pos_calc_ky_val_swb_s0 : std_logic; + signal pos_calc_ky_val_swb_s1 : std_logic; + signal pos_calc_ky_val_swb_s2 : std_logic; + signal pos_calc_ksum_val_int : std_logic_vector(24 downto 0); + signal pos_calc_ksum_val_swb : std_logic; + signal pos_calc_ksum_val_swb_delay : std_logic; + signal pos_calc_ksum_val_swb_s0 : std_logic; + signal pos_calc_ksum_val_swb_s1 : std_logic; + signal pos_calc_ksum_val_swb_s2 : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch01_int : std_logic_vector(15 downto 0); + signal pos_calc_dsp_ctnr_tbt_ch01_lwb : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch01_lwb_delay : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch01_lwb_s0 : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch23_int : std_logic_vector(15 downto 0); + signal pos_calc_dsp_ctnr_tbt_ch23_lwb : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch23_lwb_delay : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch23_lwb_s0 : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 : std_logic; + signal pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch01_int : std_logic_vector(15 downto 0); + signal pos_calc_dsp_ctnr_fofb_ch01_lwb : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch01_lwb_delay : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch01_lwb_s0 : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch23_int : std_logic_vector(15 downto 0); + signal pos_calc_dsp_ctnr_fofb_ch23_lwb : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch23_lwb_delay : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch23_lwb_s0 : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 : std_logic; + signal pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 : std_logic; + signal pos_calc_dsp_ctnr1_monit_cic_int : std_logic_vector(15 downto 0); + signal pos_calc_dsp_ctnr1_monit_cic_lwb : std_logic; + signal pos_calc_dsp_ctnr1_monit_cic_lwb_delay : std_logic; + signal pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress : std_logic; + signal pos_calc_dsp_ctnr1_monit_cic_lwb_s0 : std_logic; + signal pos_calc_dsp_ctnr1_monit_cic_lwb_s1 : std_logic; + signal pos_calc_dsp_ctnr1_monit_cic_lwb_s2 : std_logic; + signal pos_calc_dsp_ctnr1_monit_cfir_int : std_logic_vector(15 downto 0); + signal pos_calc_dsp_ctnr1_monit_cfir_lwb : std_logic; + signal pos_calc_dsp_ctnr1_monit_cfir_lwb_delay : std_logic; + signal pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress : std_logic; + signal pos_calc_dsp_ctnr1_monit_cfir_lwb_s0 : std_logic; + signal pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 : std_logic; + signal pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 : std_logic; + signal pos_calc_dsp_ctnr2_monit_pfir_int : std_logic_vector(15 downto 0); + signal pos_calc_dsp_ctnr2_monit_pfir_lwb : std_logic; + signal pos_calc_dsp_ctnr2_monit_pfir_lwb_delay : std_logic; + signal pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress : std_logic; + signal pos_calc_dsp_ctnr2_monit_pfir_lwb_s0 : std_logic; + signal pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 : std_logic; + signal pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 : std_logic; + signal pos_calc_dsp_ctnr2_monit_fir_01_int : std_logic_vector(15 downto 0); + signal pos_calc_dsp_ctnr2_monit_fir_01_lwb : std_logic; + signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay : std_logic; + signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress : std_logic; + signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0 : std_logic; + signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 : std_logic; + signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 : std_logic; + signal pos_calc_dsp_err_clr_tbt_int : std_logic; + signal pos_calc_dsp_err_clr_tbt_int_delay : std_logic; + signal pos_calc_dsp_err_clr_tbt_sync0 : std_logic; + signal pos_calc_dsp_err_clr_tbt_sync1 : std_logic; + signal pos_calc_dsp_err_clr_tbt_sync2 : std_logic; + signal pos_calc_dsp_err_clr_fofb_int : std_logic; + signal pos_calc_dsp_err_clr_fofb_int_delay : std_logic; + signal pos_calc_dsp_err_clr_fofb_sync0 : std_logic; + signal pos_calc_dsp_err_clr_fofb_sync1 : std_logic; + signal pos_calc_dsp_err_clr_fofb_sync2 : std_logic; + signal pos_calc_dsp_err_clr_monit_part1_int : std_logic; + signal pos_calc_dsp_err_clr_monit_part1_int_delay : std_logic; + signal pos_calc_dsp_err_clr_monit_part1_sync0 : std_logic; + signal pos_calc_dsp_err_clr_monit_part1_sync1 : std_logic; + signal pos_calc_dsp_err_clr_monit_part1_sync2 : std_logic; + signal pos_calc_dsp_err_clr_monit_part2_int : std_logic; + signal pos_calc_dsp_err_clr_monit_part2_int_delay : std_logic; + signal pos_calc_dsp_err_clr_monit_part2_sync0 : std_logic; + signal pos_calc_dsp_err_clr_monit_part2_sync1 : std_logic; + signal pos_calc_dsp_err_clr_monit_part2_sync2 : std_logic; + signal pos_calc_dds_cfg_valid_ch0_int : std_logic; + signal pos_calc_dds_cfg_valid_ch0_int_delay : std_logic; + signal pos_calc_dds_cfg_valid_ch0_sync0 : std_logic; + signal pos_calc_dds_cfg_valid_ch0_sync1 : std_logic; + signal pos_calc_dds_cfg_valid_ch0_sync2 : std_logic; + signal pos_calc_dds_cfg_test_data_int : std_logic; + signal pos_calc_dds_cfg_test_data_sync0 : std_logic; + signal pos_calc_dds_cfg_test_data_sync1 : std_logic; + signal pos_calc_dds_cfg_valid_ch1_int : std_logic; + signal pos_calc_dds_cfg_valid_ch1_int_delay : std_logic; + signal pos_calc_dds_cfg_valid_ch1_sync0 : std_logic; + signal pos_calc_dds_cfg_valid_ch1_sync1 : std_logic; + signal pos_calc_dds_cfg_valid_ch1_sync2 : std_logic; + signal pos_calc_dds_cfg_valid_ch2_int : std_logic; + signal pos_calc_dds_cfg_valid_ch2_int_delay : std_logic; + signal pos_calc_dds_cfg_valid_ch2_sync0 : std_logic; + signal pos_calc_dds_cfg_valid_ch2_sync1 : std_logic; + signal pos_calc_dds_cfg_valid_ch2_sync2 : std_logic; + signal pos_calc_dds_cfg_valid_ch3_int : std_logic; + signal pos_calc_dds_cfg_valid_ch3_int_delay : std_logic; + signal pos_calc_dds_cfg_valid_ch3_sync0 : std_logic; + signal pos_calc_dds_cfg_valid_ch3_sync1 : std_logic; + signal pos_calc_dds_cfg_valid_ch3_sync2 : std_logic; + signal pos_calc_dds_pinc_ch0_val_int : std_logic_vector(29 downto 0); + signal pos_calc_dds_pinc_ch0_val_swb : std_logic; + signal pos_calc_dds_pinc_ch0_val_swb_delay : std_logic; + signal pos_calc_dds_pinc_ch0_val_swb_s0 : std_logic; + signal pos_calc_dds_pinc_ch0_val_swb_s1 : std_logic; + signal pos_calc_dds_pinc_ch0_val_swb_s2 : std_logic; + signal pos_calc_dds_pinc_ch1_val_int : std_logic_vector(29 downto 0); + signal pos_calc_dds_pinc_ch1_val_swb : std_logic; + signal pos_calc_dds_pinc_ch1_val_swb_delay : std_logic; + signal pos_calc_dds_pinc_ch1_val_swb_s0 : std_logic; + signal pos_calc_dds_pinc_ch1_val_swb_s1 : std_logic; + signal pos_calc_dds_pinc_ch1_val_swb_s2 : std_logic; + signal pos_calc_dds_pinc_ch2_val_int : std_logic_vector(29 downto 0); + signal pos_calc_dds_pinc_ch2_val_swb : std_logic; + signal pos_calc_dds_pinc_ch2_val_swb_delay : std_logic; + signal pos_calc_dds_pinc_ch2_val_swb_s0 : std_logic; + signal pos_calc_dds_pinc_ch2_val_swb_s1 : std_logic; + signal pos_calc_dds_pinc_ch2_val_swb_s2 : std_logic; + signal pos_calc_dds_pinc_ch3_val_int : std_logic_vector(29 downto 0); + signal pos_calc_dds_pinc_ch3_val_swb : std_logic; + signal pos_calc_dds_pinc_ch3_val_swb_delay : std_logic; + signal pos_calc_dds_pinc_ch3_val_swb_s0 : std_logic; + signal pos_calc_dds_pinc_ch3_val_swb_s1 : std_logic; + signal pos_calc_dds_pinc_ch3_val_swb_s2 : std_logic; + signal pos_calc_dds_poff_ch0_val_int : std_logic_vector(29 downto 0); + signal pos_calc_dds_poff_ch0_val_swb : std_logic; + signal pos_calc_dds_poff_ch0_val_swb_delay : std_logic; + signal pos_calc_dds_poff_ch0_val_swb_s0 : std_logic; + signal pos_calc_dds_poff_ch0_val_swb_s1 : std_logic; + signal pos_calc_dds_poff_ch0_val_swb_s2 : std_logic; + signal pos_calc_dds_poff_ch1_val_int : std_logic_vector(29 downto 0); + signal pos_calc_dds_poff_ch1_val_swb : std_logic; + signal pos_calc_dds_poff_ch1_val_swb_delay : std_logic; + signal pos_calc_dds_poff_ch1_val_swb_s0 : std_logic; + signal pos_calc_dds_poff_ch1_val_swb_s1 : std_logic; + signal pos_calc_dds_poff_ch1_val_swb_s2 : std_logic; + signal pos_calc_dds_poff_ch2_val_int : std_logic_vector(29 downto 0); + signal pos_calc_dds_poff_ch2_val_swb : std_logic; + signal pos_calc_dds_poff_ch2_val_swb_delay : std_logic; + signal pos_calc_dds_poff_ch2_val_swb_s0 : std_logic; + signal pos_calc_dds_poff_ch2_val_swb_s1 : std_logic; + signal pos_calc_dds_poff_ch2_val_swb_s2 : std_logic; + signal pos_calc_dds_poff_ch3_val_int : std_logic_vector(29 downto 0); + signal pos_calc_dds_poff_ch3_val_swb : std_logic; + signal pos_calc_dds_poff_ch3_val_swb_delay : std_logic; + signal pos_calc_dds_poff_ch3_val_swb_s0 : std_logic; + signal pos_calc_dds_poff_ch3_val_swb_s1 : std_logic; + signal pos_calc_dds_poff_ch3_val_swb_s2 : std_logic; + signal pos_calc_ampfifo_monit_rst_n : std_logic; + signal pos_calc_ampfifo_monit_in_int : std_logic_vector(127 downto 0); + signal pos_calc_ampfifo_monit_out_int : std_logic_vector(127 downto 0); + signal pos_calc_ampfifo_monit_rdreq_int : std_logic; + signal pos_calc_ampfifo_monit_rdreq_int_d0 : std_logic; + signal pos_calc_posfifo_monit_rst_n : std_logic; + signal pos_calc_posfifo_monit_in_int : std_logic_vector(127 downto 0); + signal pos_calc_posfifo_monit_out_int : std_logic_vector(127 downto 0); + signal pos_calc_posfifo_monit_rdreq_int : std_logic; + signal pos_calc_posfifo_monit_rdreq_int_d0 : std_logic; + signal pos_calc_ampfifo_monit1_rst_n : std_logic; + signal pos_calc_ampfifo_monit1_in_int : std_logic_vector(127 downto 0); + signal pos_calc_ampfifo_monit1_out_int : std_logic_vector(127 downto 0); + signal pos_calc_ampfifo_monit1_rdreq_int : std_logic; + signal pos_calc_ampfifo_monit1_rdreq_int_d0 : std_logic; + signal pos_calc_posfifo_monit1_rst_n : std_logic; + signal pos_calc_posfifo_monit1_in_int : std_logic_vector(127 downto 0); + signal pos_calc_posfifo_monit1_out_int : std_logic_vector(127 downto 0); + signal pos_calc_posfifo_monit1_rdreq_int : std_logic; + signal pos_calc_posfifo_monit1_rdreq_int_d0 : std_logic; + signal pos_calc_sw_tag_en_int : std_logic; + signal pos_calc_sw_tag_en_sync0 : std_logic; + signal pos_calc_sw_tag_en_sync1 : std_logic; + signal pos_calc_sw_tag_desync_cnt_rst_int : std_logic; + signal pos_calc_sw_tag_desync_cnt_rst_int_delay : std_logic; + signal pos_calc_sw_tag_desync_cnt_rst_sync0 : std_logic; + signal pos_calc_sw_tag_desync_cnt_rst_sync1 : std_logic; + signal pos_calc_sw_tag_desync_cnt_rst_sync2 : std_logic; + signal pos_calc_sw_tag_desync_cnt_int : std_logic_vector(13 downto 0); + signal pos_calc_sw_tag_desync_cnt_lwb : std_logic; + signal pos_calc_sw_tag_desync_cnt_lwb_delay : std_logic; + signal pos_calc_sw_tag_desync_cnt_lwb_in_progress : std_logic; + signal pos_calc_sw_tag_desync_cnt_lwb_s0 : std_logic; + signal pos_calc_sw_tag_desync_cnt_lwb_s1 : std_logic; + signal pos_calc_sw_tag_desync_cnt_lwb_s2 : std_logic; + signal pos_calc_sw_data_mask_en_int : std_logic; + signal pos_calc_sw_data_mask_en_sync0 : std_logic; + signal pos_calc_sw_data_mask_en_sync1 : std_logic; + signal pos_calc_sw_data_mask_samples_int : std_logic_vector(15 downto 0); + signal pos_calc_sw_data_mask_samples_swb : std_logic; + signal pos_calc_sw_data_mask_samples_swb_delay : std_logic; + signal pos_calc_sw_data_mask_samples_swb_s0 : std_logic; + signal pos_calc_sw_data_mask_samples_swb_s1 : std_logic; + signal pos_calc_sw_data_mask_samples_swb_s2 : std_logic; + signal pos_calc_tbt_tag_en_int : std_logic; + signal pos_calc_tbt_tag_en_sync0 : std_logic; + signal pos_calc_tbt_tag_en_sync1 : std_logic; + signal pos_calc_tbt_tag_dly_int : std_logic_vector(15 downto 0); + signal pos_calc_tbt_tag_dly_swb : std_logic; + signal pos_calc_tbt_tag_dly_swb_delay : std_logic; + signal pos_calc_tbt_tag_dly_swb_s0 : std_logic; + signal pos_calc_tbt_tag_dly_swb_s1 : std_logic; + signal pos_calc_tbt_tag_dly_swb_s2 : std_logic; + signal pos_calc_tbt_tag_desync_cnt_rst_int : std_logic; + signal pos_calc_tbt_tag_desync_cnt_rst_int_delay : std_logic; + signal pos_calc_tbt_tag_desync_cnt_rst_sync0 : std_logic; + signal pos_calc_tbt_tag_desync_cnt_rst_sync1 : std_logic; + signal pos_calc_tbt_tag_desync_cnt_rst_sync2 : std_logic; + signal pos_calc_tbt_tag_desync_cnt_int : std_logic_vector(13 downto 0); + signal pos_calc_tbt_tag_desync_cnt_lwb : std_logic; + signal pos_calc_tbt_tag_desync_cnt_lwb_delay : std_logic; + signal pos_calc_tbt_tag_desync_cnt_lwb_in_progress : std_logic; + signal pos_calc_tbt_tag_desync_cnt_lwb_s0 : std_logic; + signal pos_calc_tbt_tag_desync_cnt_lwb_s1 : std_logic; + signal pos_calc_tbt_tag_desync_cnt_lwb_s2 : std_logic; + signal pos_calc_tbt_data_mask_ctl_en_int : std_logic; + signal pos_calc_tbt_data_mask_ctl_en_sync0 : std_logic; + signal pos_calc_tbt_data_mask_ctl_en_sync1 : std_logic; + signal pos_calc_tbt_data_mask_samples_beg_int : std_logic_vector(15 downto 0); + signal pos_calc_tbt_data_mask_samples_beg_swb : std_logic; + signal pos_calc_tbt_data_mask_samples_beg_swb_delay : std_logic; + signal pos_calc_tbt_data_mask_samples_beg_swb_s0 : std_logic; + signal pos_calc_tbt_data_mask_samples_beg_swb_s1 : std_logic; + signal pos_calc_tbt_data_mask_samples_beg_swb_s2 : std_logic; + signal pos_calc_tbt_data_mask_samples_end_int : std_logic_vector(15 downto 0); + signal pos_calc_tbt_data_mask_samples_end_swb : std_logic; + signal pos_calc_tbt_data_mask_samples_end_swb_delay : std_logic; + signal pos_calc_tbt_data_mask_samples_end_swb_s0 : std_logic; + signal pos_calc_tbt_data_mask_samples_end_swb_s1 : std_logic; + signal pos_calc_tbt_data_mask_samples_end_swb_s2 : std_logic; + signal pos_calc_monit1_tag_en_int : std_logic; + signal pos_calc_monit1_tag_en_sync0 : std_logic; + signal pos_calc_monit1_tag_en_sync1 : std_logic; + signal pos_calc_monit1_tag_dly_int : std_logic_vector(15 downto 0); + signal pos_calc_monit1_tag_dly_swb : std_logic; + signal pos_calc_monit1_tag_dly_swb_delay : std_logic; + signal pos_calc_monit1_tag_dly_swb_s0 : std_logic; + signal pos_calc_monit1_tag_dly_swb_s1 : std_logic; + signal pos_calc_monit1_tag_dly_swb_s2 : std_logic; + signal pos_calc_monit1_tag_desync_cnt_rst_int : std_logic; + signal pos_calc_monit1_tag_desync_cnt_rst_int_delay : std_logic; + signal pos_calc_monit1_tag_desync_cnt_rst_sync0 : std_logic; + signal pos_calc_monit1_tag_desync_cnt_rst_sync1 : std_logic; + signal pos_calc_monit1_tag_desync_cnt_rst_sync2 : std_logic; + signal pos_calc_monit1_tag_desync_cnt_int : std_logic_vector(13 downto 0); + signal pos_calc_monit1_tag_desync_cnt_lwb : std_logic; + signal pos_calc_monit1_tag_desync_cnt_lwb_delay : std_logic; + signal pos_calc_monit1_tag_desync_cnt_lwb_in_progress : std_logic; + signal pos_calc_monit1_tag_desync_cnt_lwb_s0 : std_logic; + signal pos_calc_monit1_tag_desync_cnt_lwb_s1 : std_logic; + signal pos_calc_monit1_tag_desync_cnt_lwb_s2 : std_logic; + signal pos_calc_monit1_data_mask_ctl_en_int : std_logic; + signal pos_calc_monit1_data_mask_ctl_en_sync0 : std_logic; + signal pos_calc_monit1_data_mask_ctl_en_sync1 : std_logic; + signal pos_calc_monit1_data_mask_samples_beg_int : std_logic_vector(15 downto 0); + signal pos_calc_monit1_data_mask_samples_beg_swb : std_logic; + signal pos_calc_monit1_data_mask_samples_beg_swb_delay : std_logic; + signal pos_calc_monit1_data_mask_samples_beg_swb_s0 : std_logic; + signal pos_calc_monit1_data_mask_samples_beg_swb_s1 : std_logic; + signal pos_calc_monit1_data_mask_samples_beg_swb_s2 : std_logic; + signal pos_calc_monit1_data_mask_samples_end_int : std_logic_vector(15 downto 0); + signal pos_calc_monit1_data_mask_samples_end_swb : std_logic; + signal pos_calc_monit1_data_mask_samples_end_swb_delay : std_logic; + signal pos_calc_monit1_data_mask_samples_end_swb_s0 : std_logic; + signal pos_calc_monit1_data_mask_samples_end_swb_s1 : std_logic; + signal pos_calc_monit1_data_mask_samples_end_swb_s2 : std_logic; + signal pos_calc_monit_tag_en_int : std_logic; + signal pos_calc_monit_tag_en_sync0 : std_logic; + signal pos_calc_monit_tag_en_sync1 : std_logic; + signal pos_calc_monit_tag_dly_int : std_logic_vector(15 downto 0); + signal pos_calc_monit_tag_dly_swb : std_logic; + signal pos_calc_monit_tag_dly_swb_delay : std_logic; + signal pos_calc_monit_tag_dly_swb_s0 : std_logic; + signal pos_calc_monit_tag_dly_swb_s1 : std_logic; + signal pos_calc_monit_tag_dly_swb_s2 : std_logic; + signal pos_calc_monit_tag_desync_cnt_rst_int : std_logic; + signal pos_calc_monit_tag_desync_cnt_rst_int_delay : std_logic; + signal pos_calc_monit_tag_desync_cnt_rst_sync0 : std_logic; + signal pos_calc_monit_tag_desync_cnt_rst_sync1 : std_logic; + signal pos_calc_monit_tag_desync_cnt_rst_sync2 : std_logic; + signal pos_calc_monit_tag_desync_cnt_int : std_logic_vector(13 downto 0); + signal pos_calc_monit_tag_desync_cnt_lwb : std_logic; + signal pos_calc_monit_tag_desync_cnt_lwb_delay : std_logic; + signal pos_calc_monit_tag_desync_cnt_lwb_in_progress : std_logic; + signal pos_calc_monit_tag_desync_cnt_lwb_s0 : std_logic; + signal pos_calc_monit_tag_desync_cnt_lwb_s1 : std_logic; + signal pos_calc_monit_tag_desync_cnt_lwb_s2 : std_logic; + signal pos_calc_monit_data_mask_ctl_en_int : std_logic; + signal pos_calc_monit_data_mask_ctl_en_sync0 : std_logic; + signal pos_calc_monit_data_mask_ctl_en_sync1 : std_logic; + signal pos_calc_monit_data_mask_samples_beg_int : std_logic_vector(15 downto 0); + signal pos_calc_monit_data_mask_samples_beg_swb : std_logic; + signal pos_calc_monit_data_mask_samples_beg_swb_delay : std_logic; + signal pos_calc_monit_data_mask_samples_beg_swb_s0 : std_logic; + signal pos_calc_monit_data_mask_samples_beg_swb_s1 : std_logic; + signal pos_calc_monit_data_mask_samples_beg_swb_s2 : std_logic; + signal pos_calc_monit_data_mask_samples_end_int : std_logic_vector(15 downto 0); + signal pos_calc_monit_data_mask_samples_end_swb : std_logic; + signal pos_calc_monit_data_mask_samples_end_swb_delay : std_logic; + signal pos_calc_monit_data_mask_samples_end_swb_s0 : std_logic; + signal pos_calc_monit_data_mask_samples_end_swb_s1 : std_logic; + signal pos_calc_monit_data_mask_samples_end_swb_s2 : std_logic; + signal pos_calc_offset_x_int : std_logic_vector(31 downto 0); + signal pos_calc_offset_x_swb : std_logic; + signal pos_calc_offset_x_swb_delay : std_logic; + signal pos_calc_offset_x_swb_s0 : std_logic; + signal pos_calc_offset_x_swb_s1 : std_logic; + signal pos_calc_offset_x_swb_s2 : std_logic; + signal pos_calc_offset_y_int : std_logic_vector(31 downto 0); + signal pos_calc_offset_y_swb : std_logic; + signal pos_calc_offset_y_swb_delay : std_logic; + signal pos_calc_offset_y_swb_s0 : std_logic; + signal pos_calc_offset_y_swb_s1 : std_logic; + signal pos_calc_offset_y_swb_s2 : std_logic; + signal pos_calc_ampfifo_monit_full_int : std_logic; + signal pos_calc_ampfifo_monit_empty_int : std_logic; + signal pos_calc_ampfifo_monit_usedw_int : std_logic_vector(3 downto 0); + signal pos_calc_posfifo_monit_full_int : std_logic; + signal pos_calc_posfifo_monit_empty_int : std_logic; + signal pos_calc_posfifo_monit_usedw_int : std_logic_vector(3 downto 0); + signal pos_calc_ampfifo_monit1_full_int : std_logic; + signal pos_calc_ampfifo_monit1_empty_int : std_logic; + signal pos_calc_ampfifo_monit1_usedw_int : std_logic_vector(3 downto 0); + signal pos_calc_posfifo_monit1_full_int : std_logic; + signal pos_calc_posfifo_monit1_empty_int : std_logic; + signal pos_calc_posfifo_monit1_usedw_int : std_logic_vector(3 downto 0); + signal ack_sreg : std_logic_vector(9 downto 0); + signal rddata_reg : std_logic_vector(31 downto 0); + signal wrdata_reg : std_logic_vector(31 downto 0); + signal bwsel_reg : std_logic_vector(3 downto 0); + signal rwaddr_reg : std_logic_vector(6 downto 0); + signal ack_in_progress : std_logic; + signal wr_int : std_logic; + signal rd_int : std_logic; + signal allones : std_logic_vector(31 downto 0); + signal allzeros : std_logic_vector(31 downto 0); + +begin + -- Some internal signals assignments. For (foreseen) compatibility with other bus standards. + wrdata_reg <= wb_dat_i; + bwsel_reg <= wb_sel_i; + rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i)); + wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i); + allones <= (others => '1'); + allzeros <= (others => '0'); + -- + -- Main register bank access process. + process (clk_sys_i, rst_n_i) + begin + if (rst_n_i = '0') then + ack_sreg <= "0000000000"; + ack_in_progress <= '0'; + rddata_reg <= "00000000000000000000000000000000"; + pos_calc_ds_tbt_thres_val_int <= "00000000000000000000000000"; + pos_calc_ds_tbt_thres_val_swb <= '0'; + pos_calc_ds_tbt_thres_val_swb_delay <= '0'; + pos_calc_ds_fofb_thres_val_int <= "00000000000000000000000000"; + pos_calc_ds_fofb_thres_val_swb <= '0'; + pos_calc_ds_fofb_thres_val_swb_delay <= '0'; + pos_calc_ds_monit_thres_val_int <= "00000000000000000000000000"; + pos_calc_ds_monit_thres_val_swb <= '0'; + pos_calc_ds_monit_thres_val_swb_delay <= '0'; + pos_calc_kx_val_int <= "0000000000000000000000000"; + pos_calc_kx_val_swb <= '0'; + pos_calc_kx_val_swb_delay <= '0'; + pos_calc_ky_val_int <= "0000000000000000000000000"; + pos_calc_ky_val_swb <= '0'; + pos_calc_ky_val_swb_delay <= '0'; + pos_calc_ksum_val_int <= "0000000000000000000000000"; + pos_calc_ksum_val_swb <= '0'; + pos_calc_ksum_val_swb_delay <= '0'; + pos_calc_dsp_ctnr_tbt_ch01_lwb <= '0'; + pos_calc_dsp_ctnr_tbt_ch01_lwb_delay <= '0'; + pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress <= '0'; + pos_calc_dsp_ctnr_tbt_ch23_lwb <= '0'; + pos_calc_dsp_ctnr_tbt_ch23_lwb_delay <= '0'; + pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress <= '0'; + pos_calc_dsp_ctnr_fofb_ch01_lwb <= '0'; + pos_calc_dsp_ctnr_fofb_ch01_lwb_delay <= '0'; + pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress <= '0'; + pos_calc_dsp_ctnr_fofb_ch23_lwb <= '0'; + pos_calc_dsp_ctnr_fofb_ch23_lwb_delay <= '0'; + pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress <= '0'; + pos_calc_dsp_ctnr1_monit_cic_lwb <= '0'; + pos_calc_dsp_ctnr1_monit_cic_lwb_delay <= '0'; + pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress <= '0'; + pos_calc_dsp_ctnr1_monit_cfir_lwb <= '0'; + pos_calc_dsp_ctnr1_monit_cfir_lwb_delay <= '0'; + pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress <= '0'; + pos_calc_dsp_ctnr2_monit_pfir_lwb <= '0'; + pos_calc_dsp_ctnr2_monit_pfir_lwb_delay <= '0'; + pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress <= '0'; + pos_calc_dsp_ctnr2_monit_fir_01_lwb <= '0'; + pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay <= '0'; + pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress <= '0'; + pos_calc_dsp_err_clr_tbt_int <= '0'; + pos_calc_dsp_err_clr_tbt_int_delay <= '0'; + pos_calc_dsp_err_clr_fofb_int <= '0'; + pos_calc_dsp_err_clr_fofb_int_delay <= '0'; + pos_calc_dsp_err_clr_monit_part1_int <= '0'; + pos_calc_dsp_err_clr_monit_part1_int_delay <= '0'; + pos_calc_dsp_err_clr_monit_part2_int <= '0'; + pos_calc_dsp_err_clr_monit_part2_int_delay <= '0'; + pos_calc_dds_cfg_valid_ch0_int <= '0'; + pos_calc_dds_cfg_valid_ch0_int_delay <= '0'; + pos_calc_dds_cfg_test_data_int <= '0'; + pos_calc_dds_cfg_valid_ch1_int <= '0'; + pos_calc_dds_cfg_valid_ch1_int_delay <= '0'; + pos_calc_dds_cfg_valid_ch2_int <= '0'; + pos_calc_dds_cfg_valid_ch2_int_delay <= '0'; + pos_calc_dds_cfg_valid_ch3_int <= '0'; + pos_calc_dds_cfg_valid_ch3_int_delay <= '0'; + pos_calc_dds_pinc_ch0_val_int <= "000000000000000000000000000000"; + pos_calc_dds_pinc_ch0_val_swb <= '0'; + pos_calc_dds_pinc_ch0_val_swb_delay <= '0'; + pos_calc_dds_pinc_ch1_val_int <= "000000000000000000000000000000"; + pos_calc_dds_pinc_ch1_val_swb <= '0'; + pos_calc_dds_pinc_ch1_val_swb_delay <= '0'; + pos_calc_dds_pinc_ch2_val_int <= "000000000000000000000000000000"; + pos_calc_dds_pinc_ch2_val_swb <= '0'; + pos_calc_dds_pinc_ch2_val_swb_delay <= '0'; + pos_calc_dds_pinc_ch3_val_int <= "000000000000000000000000000000"; + pos_calc_dds_pinc_ch3_val_swb <= '0'; + pos_calc_dds_pinc_ch3_val_swb_delay <= '0'; + pos_calc_dds_poff_ch0_val_int <= "000000000000000000000000000000"; + pos_calc_dds_poff_ch0_val_swb <= '0'; + pos_calc_dds_poff_ch0_val_swb_delay <= '0'; + pos_calc_dds_poff_ch1_val_int <= "000000000000000000000000000000"; + pos_calc_dds_poff_ch1_val_swb <= '0'; + pos_calc_dds_poff_ch1_val_swb_delay <= '0'; + pos_calc_dds_poff_ch2_val_int <= "000000000000000000000000000000"; + pos_calc_dds_poff_ch2_val_swb <= '0'; + pos_calc_dds_poff_ch2_val_swb_delay <= '0'; + pos_calc_dds_poff_ch3_val_int <= "000000000000000000000000000000"; + pos_calc_dds_poff_ch3_val_swb <= '0'; + pos_calc_dds_poff_ch3_val_swb_delay <= '0'; + pos_calc_dsp_monit_updt_wr_o <= '0'; + pos_calc_dsp_monit1_updt_wr_o <= '0'; + pos_calc_sw_tag_en_int <= '0'; + pos_calc_sw_tag_desync_cnt_rst_int <= '0'; + pos_calc_sw_tag_desync_cnt_rst_int_delay <= '0'; + pos_calc_sw_tag_desync_cnt_lwb <= '0'; + pos_calc_sw_tag_desync_cnt_lwb_delay <= '0'; + pos_calc_sw_tag_desync_cnt_lwb_in_progress <= '0'; + pos_calc_sw_data_mask_en_int <= '0'; + pos_calc_sw_data_mask_samples_int <= "0000000000000000"; + pos_calc_sw_data_mask_samples_swb <= '0'; + pos_calc_sw_data_mask_samples_swb_delay <= '0'; + pos_calc_tbt_tag_en_int <= '0'; + pos_calc_tbt_tag_dly_int <= "0000000000000000"; + pos_calc_tbt_tag_dly_swb <= '0'; + pos_calc_tbt_tag_dly_swb_delay <= '0'; + pos_calc_tbt_tag_desync_cnt_rst_int <= '0'; + pos_calc_tbt_tag_desync_cnt_rst_int_delay <= '0'; + pos_calc_tbt_tag_desync_cnt_lwb <= '0'; + pos_calc_tbt_tag_desync_cnt_lwb_delay <= '0'; + pos_calc_tbt_tag_desync_cnt_lwb_in_progress <= '0'; + pos_calc_tbt_data_mask_ctl_en_int <= '0'; + pos_calc_tbt_data_mask_samples_beg_int <= "0000000000000000"; + pos_calc_tbt_data_mask_samples_beg_swb <= '0'; + pos_calc_tbt_data_mask_samples_beg_swb_delay <= '0'; + pos_calc_tbt_data_mask_samples_end_int <= "0000000000000000"; + pos_calc_tbt_data_mask_samples_end_swb <= '0'; + pos_calc_tbt_data_mask_samples_end_swb_delay <= '0'; + pos_calc_monit1_tag_en_int <= '0'; + pos_calc_monit1_tag_dly_int <= "0000000000000000"; + pos_calc_monit1_tag_dly_swb <= '0'; + pos_calc_monit1_tag_dly_swb_delay <= '0'; + pos_calc_monit1_tag_desync_cnt_rst_int <= '0'; + pos_calc_monit1_tag_desync_cnt_rst_int_delay <= '0'; + pos_calc_monit1_tag_desync_cnt_lwb <= '0'; + pos_calc_monit1_tag_desync_cnt_lwb_delay <= '0'; + pos_calc_monit1_tag_desync_cnt_lwb_in_progress <= '0'; + pos_calc_monit1_data_mask_ctl_en_int <= '0'; + pos_calc_monit1_data_mask_samples_beg_int <= "0000000000000000"; + pos_calc_monit1_data_mask_samples_beg_swb <= '0'; + pos_calc_monit1_data_mask_samples_beg_swb_delay <= '0'; + pos_calc_monit1_data_mask_samples_end_int <= "0000000000000000"; + pos_calc_monit1_data_mask_samples_end_swb <= '0'; + pos_calc_monit1_data_mask_samples_end_swb_delay <= '0'; + pos_calc_monit_tag_en_int <= '0'; + pos_calc_monit_tag_dly_int <= "0000000000000000"; + pos_calc_monit_tag_dly_swb <= '0'; + pos_calc_monit_tag_dly_swb_delay <= '0'; + pos_calc_monit_tag_desync_cnt_rst_int <= '0'; + pos_calc_monit_tag_desync_cnt_rst_int_delay <= '0'; + pos_calc_monit_tag_desync_cnt_lwb <= '0'; + pos_calc_monit_tag_desync_cnt_lwb_delay <= '0'; + pos_calc_monit_tag_desync_cnt_lwb_in_progress <= '0'; + pos_calc_monit_data_mask_ctl_en_int <= '0'; + pos_calc_monit_data_mask_samples_beg_int <= "0000000000000000"; + pos_calc_monit_data_mask_samples_beg_swb <= '0'; + pos_calc_monit_data_mask_samples_beg_swb_delay <= '0'; + pos_calc_monit_data_mask_samples_end_int <= "0000000000000000"; + pos_calc_monit_data_mask_samples_end_swb <= '0'; + pos_calc_monit_data_mask_samples_end_swb_delay <= '0'; + pos_calc_offset_x_int <= "00000000000000000000000000000000"; + pos_calc_offset_x_swb <= '0'; + pos_calc_offset_x_swb_delay <= '0'; + pos_calc_offset_y_int <= "00000000000000000000000000000000"; + pos_calc_offset_y_swb <= '0'; + pos_calc_offset_y_swb_delay <= '0'; + pos_calc_ampfifo_monit_rdreq_int <= '0'; + pos_calc_posfifo_monit_rdreq_int <= '0'; + pos_calc_ampfifo_monit1_rdreq_int <= '0'; + pos_calc_posfifo_monit1_rdreq_int <= '0'; + elsif rising_edge(clk_sys_i) then + -- advance the ACK generator shift register + ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); + ack_sreg(9) <= '0'; + if (ack_in_progress = '1') then + if (ack_sreg(0) = '1') then + pos_calc_dsp_monit_updt_wr_o <= '0'; + pos_calc_dsp_monit1_updt_wr_o <= '0'; + ack_in_progress <= '0'; + else + pos_calc_ds_tbt_thres_val_swb <= pos_calc_ds_tbt_thres_val_swb_delay; + pos_calc_ds_tbt_thres_val_swb_delay <= '0'; + pos_calc_ds_fofb_thres_val_swb <= pos_calc_ds_fofb_thres_val_swb_delay; + pos_calc_ds_fofb_thres_val_swb_delay <= '0'; + pos_calc_ds_monit_thres_val_swb <= pos_calc_ds_monit_thres_val_swb_delay; + pos_calc_ds_monit_thres_val_swb_delay <= '0'; + pos_calc_kx_val_swb <= pos_calc_kx_val_swb_delay; + pos_calc_kx_val_swb_delay <= '0'; + pos_calc_ky_val_swb <= pos_calc_ky_val_swb_delay; + pos_calc_ky_val_swb_delay <= '0'; + pos_calc_ksum_val_swb <= pos_calc_ksum_val_swb_delay; + pos_calc_ksum_val_swb_delay <= '0'; + pos_calc_dsp_ctnr_tbt_ch01_lwb <= pos_calc_dsp_ctnr_tbt_ch01_lwb_delay; + pos_calc_dsp_ctnr_tbt_ch01_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress = '1')) then + rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr_tbt_ch01_int; + pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress <= '0'; + end if; + pos_calc_dsp_ctnr_tbt_ch23_lwb <= pos_calc_dsp_ctnr_tbt_ch23_lwb_delay; + pos_calc_dsp_ctnr_tbt_ch23_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress = '1')) then + rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr_tbt_ch23_int; + pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress <= '0'; + end if; + pos_calc_dsp_ctnr_fofb_ch01_lwb <= pos_calc_dsp_ctnr_fofb_ch01_lwb_delay; + pos_calc_dsp_ctnr_fofb_ch01_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress = '1')) then + rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr_fofb_ch01_int; + pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress <= '0'; + end if; + pos_calc_dsp_ctnr_fofb_ch23_lwb <= pos_calc_dsp_ctnr_fofb_ch23_lwb_delay; + pos_calc_dsp_ctnr_fofb_ch23_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress = '1')) then + rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr_fofb_ch23_int; + pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress <= '0'; + end if; + pos_calc_dsp_ctnr1_monit_cic_lwb <= pos_calc_dsp_ctnr1_monit_cic_lwb_delay; + pos_calc_dsp_ctnr1_monit_cic_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress = '1')) then + rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr1_monit_cic_int; + pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress <= '0'; + end if; + pos_calc_dsp_ctnr1_monit_cfir_lwb <= pos_calc_dsp_ctnr1_monit_cfir_lwb_delay; + pos_calc_dsp_ctnr1_monit_cfir_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress = '1')) then + rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr1_monit_cfir_int; + pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress <= '0'; + end if; + pos_calc_dsp_ctnr2_monit_pfir_lwb <= pos_calc_dsp_ctnr2_monit_pfir_lwb_delay; + pos_calc_dsp_ctnr2_monit_pfir_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress = '1')) then + rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr2_monit_pfir_int; + pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress <= '0'; + end if; + pos_calc_dsp_ctnr2_monit_fir_01_lwb <= pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay; + pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress = '1')) then + rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr2_monit_fir_01_int; + pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress <= '0'; + end if; + pos_calc_dsp_err_clr_tbt_int <= pos_calc_dsp_err_clr_tbt_int_delay; + pos_calc_dsp_err_clr_tbt_int_delay <= '0'; + pos_calc_dsp_err_clr_fofb_int <= pos_calc_dsp_err_clr_fofb_int_delay; + pos_calc_dsp_err_clr_fofb_int_delay <= '0'; + pos_calc_dsp_err_clr_monit_part1_int <= pos_calc_dsp_err_clr_monit_part1_int_delay; + pos_calc_dsp_err_clr_monit_part1_int_delay <= '0'; + pos_calc_dsp_err_clr_monit_part2_int <= pos_calc_dsp_err_clr_monit_part2_int_delay; + pos_calc_dsp_err_clr_monit_part2_int_delay <= '0'; + pos_calc_dds_cfg_valid_ch0_int <= pos_calc_dds_cfg_valid_ch0_int_delay; + pos_calc_dds_cfg_valid_ch0_int_delay <= '0'; + pos_calc_dds_cfg_valid_ch1_int <= pos_calc_dds_cfg_valid_ch1_int_delay; + pos_calc_dds_cfg_valid_ch1_int_delay <= '0'; + pos_calc_dds_cfg_valid_ch2_int <= pos_calc_dds_cfg_valid_ch2_int_delay; + pos_calc_dds_cfg_valid_ch2_int_delay <= '0'; + pos_calc_dds_cfg_valid_ch3_int <= pos_calc_dds_cfg_valid_ch3_int_delay; + pos_calc_dds_cfg_valid_ch3_int_delay <= '0'; + pos_calc_dds_pinc_ch0_val_swb <= pos_calc_dds_pinc_ch0_val_swb_delay; + pos_calc_dds_pinc_ch0_val_swb_delay <= '0'; + pos_calc_dds_pinc_ch1_val_swb <= pos_calc_dds_pinc_ch1_val_swb_delay; + pos_calc_dds_pinc_ch1_val_swb_delay <= '0'; + pos_calc_dds_pinc_ch2_val_swb <= pos_calc_dds_pinc_ch2_val_swb_delay; + pos_calc_dds_pinc_ch2_val_swb_delay <= '0'; + pos_calc_dds_pinc_ch3_val_swb <= pos_calc_dds_pinc_ch3_val_swb_delay; + pos_calc_dds_pinc_ch3_val_swb_delay <= '0'; + pos_calc_dds_poff_ch0_val_swb <= pos_calc_dds_poff_ch0_val_swb_delay; + pos_calc_dds_poff_ch0_val_swb_delay <= '0'; + pos_calc_dds_poff_ch1_val_swb <= pos_calc_dds_poff_ch1_val_swb_delay; + pos_calc_dds_poff_ch1_val_swb_delay <= '0'; + pos_calc_dds_poff_ch2_val_swb <= pos_calc_dds_poff_ch2_val_swb_delay; + pos_calc_dds_poff_ch2_val_swb_delay <= '0'; + pos_calc_dds_poff_ch3_val_swb <= pos_calc_dds_poff_ch3_val_swb_delay; + pos_calc_dds_poff_ch3_val_swb_delay <= '0'; + pos_calc_dsp_monit_updt_wr_o <= '0'; + pos_calc_dsp_monit1_updt_wr_o <= '0'; + pos_calc_sw_tag_desync_cnt_rst_int <= pos_calc_sw_tag_desync_cnt_rst_int_delay; + pos_calc_sw_tag_desync_cnt_rst_int_delay <= '0'; + pos_calc_sw_tag_desync_cnt_lwb <= pos_calc_sw_tag_desync_cnt_lwb_delay; + pos_calc_sw_tag_desync_cnt_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_sw_tag_desync_cnt_lwb_in_progress = '1')) then + rddata_reg(22 downto 9) <= pos_calc_sw_tag_desync_cnt_int; + pos_calc_sw_tag_desync_cnt_lwb_in_progress <= '0'; + end if; + pos_calc_sw_data_mask_samples_swb <= pos_calc_sw_data_mask_samples_swb_delay; + pos_calc_sw_data_mask_samples_swb_delay <= '0'; + pos_calc_tbt_tag_dly_swb <= pos_calc_tbt_tag_dly_swb_delay; + pos_calc_tbt_tag_dly_swb_delay <= '0'; + pos_calc_tbt_tag_desync_cnt_rst_int <= pos_calc_tbt_tag_desync_cnt_rst_int_delay; + pos_calc_tbt_tag_desync_cnt_rst_int_delay <= '0'; + pos_calc_tbt_tag_desync_cnt_lwb <= pos_calc_tbt_tag_desync_cnt_lwb_delay; + pos_calc_tbt_tag_desync_cnt_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_tbt_tag_desync_cnt_lwb_in_progress = '1')) then + rddata_reg(31 downto 18) <= pos_calc_tbt_tag_desync_cnt_int; + pos_calc_tbt_tag_desync_cnt_lwb_in_progress <= '0'; + end if; + pos_calc_tbt_data_mask_samples_beg_swb <= pos_calc_tbt_data_mask_samples_beg_swb_delay; + pos_calc_tbt_data_mask_samples_beg_swb_delay <= '0'; + pos_calc_tbt_data_mask_samples_end_swb <= pos_calc_tbt_data_mask_samples_end_swb_delay; + pos_calc_tbt_data_mask_samples_end_swb_delay <= '0'; + pos_calc_monit1_tag_dly_swb <= pos_calc_monit1_tag_dly_swb_delay; + pos_calc_monit1_tag_dly_swb_delay <= '0'; + pos_calc_monit1_tag_desync_cnt_rst_int <= pos_calc_monit1_tag_desync_cnt_rst_int_delay; + pos_calc_monit1_tag_desync_cnt_rst_int_delay <= '0'; + pos_calc_monit1_tag_desync_cnt_lwb <= pos_calc_monit1_tag_desync_cnt_lwb_delay; + pos_calc_monit1_tag_desync_cnt_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_monit1_tag_desync_cnt_lwb_in_progress = '1')) then + rddata_reg(31 downto 18) <= pos_calc_monit1_tag_desync_cnt_int; + pos_calc_monit1_tag_desync_cnt_lwb_in_progress <= '0'; + end if; + pos_calc_monit1_data_mask_samples_beg_swb <= pos_calc_monit1_data_mask_samples_beg_swb_delay; + pos_calc_monit1_data_mask_samples_beg_swb_delay <= '0'; + pos_calc_monit1_data_mask_samples_end_swb <= pos_calc_monit1_data_mask_samples_end_swb_delay; + pos_calc_monit1_data_mask_samples_end_swb_delay <= '0'; + pos_calc_monit_tag_dly_swb <= pos_calc_monit_tag_dly_swb_delay; + pos_calc_monit_tag_dly_swb_delay <= '0'; + pos_calc_monit_tag_desync_cnt_rst_int <= pos_calc_monit_tag_desync_cnt_rst_int_delay; + pos_calc_monit_tag_desync_cnt_rst_int_delay <= '0'; + pos_calc_monit_tag_desync_cnt_lwb <= pos_calc_monit_tag_desync_cnt_lwb_delay; + pos_calc_monit_tag_desync_cnt_lwb_delay <= '0'; + if ((ack_sreg(1) = '1') and (pos_calc_monit_tag_desync_cnt_lwb_in_progress = '1')) then + rddata_reg(31 downto 18) <= pos_calc_monit_tag_desync_cnt_int; + pos_calc_monit_tag_desync_cnt_lwb_in_progress <= '0'; + end if; + pos_calc_monit_data_mask_samples_beg_swb <= pos_calc_monit_data_mask_samples_beg_swb_delay; + pos_calc_monit_data_mask_samples_beg_swb_delay <= '0'; + pos_calc_monit_data_mask_samples_end_swb <= pos_calc_monit_data_mask_samples_end_swb_delay; + pos_calc_monit_data_mask_samples_end_swb_delay <= '0'; + pos_calc_offset_x_swb <= pos_calc_offset_x_swb_delay; + pos_calc_offset_x_swb_delay <= '0'; + pos_calc_offset_y_swb <= pos_calc_offset_y_swb_delay; + pos_calc_offset_y_swb_delay <= '0'; + end if; + else + if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then + case rwaddr_reg(6 downto 0) is + when "0000000" => + if (wb_we_i = '1') then + pos_calc_ds_tbt_thres_val_int <= wrdata_reg(25 downto 0); + pos_calc_ds_tbt_thres_val_swb <= '1'; + pos_calc_ds_tbt_thres_val_swb_delay <= '1'; + end if; + rddata_reg(25 downto 0) <= pos_calc_ds_tbt_thres_val_int; + rddata_reg(31 downto 26) <= pos_calc_ds_tbt_thres_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0000001" => + if (wb_we_i = '1') then + pos_calc_ds_fofb_thres_val_int <= wrdata_reg(25 downto 0); + pos_calc_ds_fofb_thres_val_swb <= '1'; + pos_calc_ds_fofb_thres_val_swb_delay <= '1'; + end if; + rddata_reg(25 downto 0) <= pos_calc_ds_fofb_thres_val_int; + rddata_reg(31 downto 26) <= pos_calc_ds_fofb_thres_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0000010" => + if (wb_we_i = '1') then + pos_calc_ds_monit_thres_val_int <= wrdata_reg(25 downto 0); + pos_calc_ds_monit_thres_val_swb <= '1'; + pos_calc_ds_monit_thres_val_swb_delay <= '1'; + end if; + rddata_reg(25 downto 0) <= pos_calc_ds_monit_thres_val_int; + rddata_reg(31 downto 26) <= pos_calc_ds_monit_thres_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0000011" => + if (wb_we_i = '1') then + pos_calc_kx_val_int <= wrdata_reg(24 downto 0); + pos_calc_kx_val_swb <= '1'; + pos_calc_kx_val_swb_delay <= '1'; + end if; + rddata_reg(24 downto 0) <= pos_calc_kx_val_int; + rddata_reg(31 downto 25) <= pos_calc_kx_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0000100" => + if (wb_we_i = '1') then + pos_calc_ky_val_int <= wrdata_reg(24 downto 0); + pos_calc_ky_val_swb <= '1'; + pos_calc_ky_val_swb_delay <= '1'; + end if; + rddata_reg(24 downto 0) <= pos_calc_ky_val_int; + rddata_reg(31 downto 25) <= pos_calc_ky_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0000101" => + if (wb_we_i = '1') then + pos_calc_ksum_val_int <= wrdata_reg(24 downto 0); + pos_calc_ksum_val_swb <= '1'; + pos_calc_ksum_val_swb_delay <= '1'; + end if; + rddata_reg(24 downto 0) <= pos_calc_ksum_val_int; + rddata_reg(31 downto 25) <= pos_calc_ksum_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0000110" => + if (wb_we_i = '1') then + end if; + if (wb_we_i = '0') then + pos_calc_dsp_ctnr_tbt_ch01_lwb <= '1'; + pos_calc_dsp_ctnr_tbt_ch01_lwb_delay <= '1'; + pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress <= '1'; + end if; + if (wb_we_i = '0') then + pos_calc_dsp_ctnr_tbt_ch23_lwb <= '1'; + pos_calc_dsp_ctnr_tbt_ch23_lwb_delay <= '1'; + pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress <= '1'; + end if; + ack_sreg(5) <= '1'; + ack_in_progress <= '1'; + when "0000111" => + if (wb_we_i = '1') then + end if; + if (wb_we_i = '0') then + pos_calc_dsp_ctnr_fofb_ch01_lwb <= '1'; + pos_calc_dsp_ctnr_fofb_ch01_lwb_delay <= '1'; + pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress <= '1'; + end if; + if (wb_we_i = '0') then + pos_calc_dsp_ctnr_fofb_ch23_lwb <= '1'; + pos_calc_dsp_ctnr_fofb_ch23_lwb_delay <= '1'; + pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress <= '1'; + end if; + ack_sreg(5) <= '1'; + ack_in_progress <= '1'; + when "0001000" => + if (wb_we_i = '1') then + end if; + if (wb_we_i = '0') then + pos_calc_dsp_ctnr1_monit_cic_lwb <= '1'; + pos_calc_dsp_ctnr1_monit_cic_lwb_delay <= '1'; + pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress <= '1'; + end if; + if (wb_we_i = '0') then + pos_calc_dsp_ctnr1_monit_cfir_lwb <= '1'; + pos_calc_dsp_ctnr1_monit_cfir_lwb_delay <= '1'; + pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress <= '1'; + end if; + ack_sreg(5) <= '1'; + ack_in_progress <= '1'; + when "0001001" => + if (wb_we_i = '1') then + end if; + if (wb_we_i = '0') then + pos_calc_dsp_ctnr2_monit_pfir_lwb <= '1'; + pos_calc_dsp_ctnr2_monit_pfir_lwb_delay <= '1'; + pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress <= '1'; + end if; + if (wb_we_i = '0') then + pos_calc_dsp_ctnr2_monit_fir_01_lwb <= '1'; + pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay <= '1'; + pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress <= '1'; + end if; + ack_sreg(5) <= '1'; + ack_in_progress <= '1'; + when "0001010" => + if (wb_we_i = '1') then + pos_calc_dsp_err_clr_tbt_int <= wrdata_reg(0); + pos_calc_dsp_err_clr_tbt_int_delay <= wrdata_reg(0); + pos_calc_dsp_err_clr_fofb_int <= wrdata_reg(1); + pos_calc_dsp_err_clr_fofb_int_delay <= wrdata_reg(1); + pos_calc_dsp_err_clr_monit_part1_int <= wrdata_reg(2); + pos_calc_dsp_err_clr_monit_part1_int_delay <= wrdata_reg(2); + pos_calc_dsp_err_clr_monit_part2_int <= wrdata_reg(3); + pos_calc_dsp_err_clr_monit_part2_int_delay <= wrdata_reg(3); + end if; + rddata_reg(0) <= '0'; + rddata_reg(1) <= '0'; + rddata_reg(2) <= '0'; + rddata_reg(3) <= '0'; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(4) <= '1'; + ack_in_progress <= '1'; + when "0001011" => + if (wb_we_i = '1') then + pos_calc_dds_cfg_valid_ch0_int <= wrdata_reg(0); + pos_calc_dds_cfg_valid_ch0_int_delay <= wrdata_reg(0); + pos_calc_dds_cfg_test_data_int <= wrdata_reg(1); + pos_calc_dds_cfg_valid_ch1_int <= wrdata_reg(8); + pos_calc_dds_cfg_valid_ch1_int_delay <= wrdata_reg(8); + pos_calc_dds_cfg_valid_ch2_int <= wrdata_reg(16); + pos_calc_dds_cfg_valid_ch2_int_delay <= wrdata_reg(16); + pos_calc_dds_cfg_valid_ch3_int <= wrdata_reg(24); + pos_calc_dds_cfg_valid_ch3_int_delay <= wrdata_reg(24); + end if; + rddata_reg(0) <= '0'; + rddata_reg(1) <= pos_calc_dds_cfg_test_data_int; + rddata_reg(7 downto 2) <= pos_calc_dds_cfg_reserved_ch0_i; + rddata_reg(8) <= '0'; + rddata_reg(15 downto 9) <= pos_calc_dds_cfg_reserved_ch1_i; + rddata_reg(16) <= '0'; + rddata_reg(23 downto 17) <= pos_calc_dds_cfg_reserved_ch2_i; + rddata_reg(24) <= '0'; + rddata_reg(31 downto 25) <= pos_calc_dds_cfg_reserved_ch3_i; + ack_sreg(4) <= '1'; + ack_in_progress <= '1'; + when "0001100" => + if (wb_we_i = '1') then + pos_calc_dds_pinc_ch0_val_int <= wrdata_reg(29 downto 0); + pos_calc_dds_pinc_ch0_val_swb <= '1'; + pos_calc_dds_pinc_ch0_val_swb_delay <= '1'; + end if; + rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch0_val_int; + rddata_reg(31 downto 30) <= pos_calc_dds_pinc_ch0_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0001101" => + if (wb_we_i = '1') then + pos_calc_dds_pinc_ch1_val_int <= wrdata_reg(29 downto 0); + pos_calc_dds_pinc_ch1_val_swb <= '1'; + pos_calc_dds_pinc_ch1_val_swb_delay <= '1'; + end if; + rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch1_val_int; + rddata_reg(31 downto 30) <= pos_calc_dds_pinc_ch1_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0001110" => + if (wb_we_i = '1') then + pos_calc_dds_pinc_ch2_val_int <= wrdata_reg(29 downto 0); + pos_calc_dds_pinc_ch2_val_swb <= '1'; + pos_calc_dds_pinc_ch2_val_swb_delay <= '1'; + end if; + rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch2_val_int; + rddata_reg(31 downto 30) <= pos_calc_dds_pinc_ch2_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0001111" => + if (wb_we_i = '1') then + pos_calc_dds_pinc_ch3_val_int <= wrdata_reg(29 downto 0); + pos_calc_dds_pinc_ch3_val_swb <= '1'; + pos_calc_dds_pinc_ch3_val_swb_delay <= '1'; + end if; + rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch3_val_int; + rddata_reg(31 downto 30) <= pos_calc_dds_pinc_ch3_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0010000" => + if (wb_we_i = '1') then + pos_calc_dds_poff_ch0_val_int <= wrdata_reg(29 downto 0); + pos_calc_dds_poff_ch0_val_swb <= '1'; + pos_calc_dds_poff_ch0_val_swb_delay <= '1'; + end if; + rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch0_val_int; + rddata_reg(31 downto 30) <= pos_calc_dds_poff_ch0_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0010001" => + if (wb_we_i = '1') then + pos_calc_dds_poff_ch1_val_int <= wrdata_reg(29 downto 0); + pos_calc_dds_poff_ch1_val_swb <= '1'; + pos_calc_dds_poff_ch1_val_swb_delay <= '1'; + end if; + rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch1_val_int; + rddata_reg(31 downto 30) <= pos_calc_dds_poff_ch1_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0010010" => + if (wb_we_i = '1') then + pos_calc_dds_poff_ch2_val_int <= wrdata_reg(29 downto 0); + pos_calc_dds_poff_ch2_val_swb <= '1'; + pos_calc_dds_poff_ch2_val_swb_delay <= '1'; + end if; + rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch2_val_int; + rddata_reg(31 downto 30) <= pos_calc_dds_poff_ch2_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0010011" => + if (wb_we_i = '1') then + pos_calc_dds_poff_ch3_val_int <= wrdata_reg(29 downto 0); + pos_calc_dds_poff_ch3_val_swb <= '1'; + pos_calc_dds_poff_ch3_val_swb_delay <= '1'; + end if; + rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch3_val_int; + rddata_reg(31 downto 30) <= pos_calc_dds_poff_ch3_reserved_i; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0010100" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit_amp_ch0_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0010101" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit_amp_ch1_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0010110" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit_amp_ch2_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0010111" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit_amp_ch3_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0011000" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit_pos_x_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0011001" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit_pos_y_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0011010" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit_pos_q_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0011011" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit_pos_sum_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0011100" => + if (wb_we_i = '1') then + pos_calc_dsp_monit_updt_wr_o <= '1'; + end if; + rddata_reg(0) <= 'X'; + rddata_reg(1) <= 'X'; + rddata_reg(2) <= 'X'; + rddata_reg(3) <= 'X'; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0011101" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit1_amp_ch0_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0011110" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit1_amp_ch1_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0011111" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit1_amp_ch2_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0100000" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit1_amp_ch3_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0100001" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit1_pos_x_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0100010" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit1_pos_y_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0100011" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit1_pos_q_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0100100" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_dsp_monit1_pos_sum_i; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0100101" => + if (wb_we_i = '1') then + pos_calc_dsp_monit1_updt_wr_o <= '1'; + end if; + rddata_reg(0) <= 'X'; + rddata_reg(1) <= 'X'; + rddata_reg(2) <= 'X'; + rddata_reg(3) <= 'X'; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0111010" => + if (wb_we_i = '1') then + pos_calc_sw_tag_en_int <= wrdata_reg(0); + pos_calc_sw_tag_desync_cnt_rst_int <= wrdata_reg(8); + pos_calc_sw_tag_desync_cnt_rst_int_delay <= wrdata_reg(8); + end if; + rddata_reg(0) <= pos_calc_sw_tag_en_int; + rddata_reg(8) <= '0'; + if (wb_we_i = '0') then + pos_calc_sw_tag_desync_cnt_lwb <= '1'; + pos_calc_sw_tag_desync_cnt_lwb_delay <= '1'; + pos_calc_sw_tag_desync_cnt_lwb_in_progress <= '1'; + end if; + rddata_reg(1) <= 'X'; + rddata_reg(2) <= 'X'; + rddata_reg(3) <= 'X'; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(5) <= '1'; + ack_in_progress <= '1'; + when "0111011" => + if (wb_we_i = '1') then + pos_calc_sw_data_mask_en_int <= wrdata_reg(0); + pos_calc_sw_data_mask_samples_int <= wrdata_reg(16 downto 1); + pos_calc_sw_data_mask_samples_swb <= '1'; + pos_calc_sw_data_mask_samples_swb_delay <= '1'; + end if; + rddata_reg(0) <= pos_calc_sw_data_mask_en_int; + rddata_reg(16 downto 1) <= pos_calc_sw_data_mask_samples_int; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0111100" => + if (wb_we_i = '1') then + pos_calc_tbt_tag_en_int <= wrdata_reg(0); + pos_calc_tbt_tag_dly_int <= wrdata_reg(16 downto 1); + pos_calc_tbt_tag_dly_swb <= '1'; + pos_calc_tbt_tag_dly_swb_delay <= '1'; + pos_calc_tbt_tag_desync_cnt_rst_int <= wrdata_reg(17); + pos_calc_tbt_tag_desync_cnt_rst_int_delay <= wrdata_reg(17); + end if; + rddata_reg(0) <= pos_calc_tbt_tag_en_int; + rddata_reg(16 downto 1) <= pos_calc_tbt_tag_dly_int; + rddata_reg(17) <= '0'; + if (wb_we_i = '0') then + pos_calc_tbt_tag_desync_cnt_lwb <= '1'; + pos_calc_tbt_tag_desync_cnt_lwb_delay <= '1'; + pos_calc_tbt_tag_desync_cnt_lwb_in_progress <= '1'; + end if; + ack_sreg(5) <= '1'; + ack_in_progress <= '1'; + when "0111101" => + if (wb_we_i = '1') then + pos_calc_tbt_data_mask_ctl_en_int <= wrdata_reg(0); + end if; + rddata_reg(0) <= pos_calc_tbt_data_mask_ctl_en_int; + rddata_reg(1) <= 'X'; + rddata_reg(2) <= 'X'; + rddata_reg(3) <= 'X'; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0111110" => + if (wb_we_i = '1') then + pos_calc_tbt_data_mask_samples_beg_int <= wrdata_reg(15 downto 0); + pos_calc_tbt_data_mask_samples_beg_swb <= '1'; + pos_calc_tbt_data_mask_samples_beg_swb_delay <= '1'; + pos_calc_tbt_data_mask_samples_end_int <= wrdata_reg(31 downto 16); + pos_calc_tbt_data_mask_samples_end_swb <= '1'; + pos_calc_tbt_data_mask_samples_end_swb_delay <= '1'; + end if; + rddata_reg(15 downto 0) <= pos_calc_tbt_data_mask_samples_beg_int; + rddata_reg(31 downto 16) <= pos_calc_tbt_data_mask_samples_end_int; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0111111" => + if (wb_we_i = '1') then + pos_calc_monit1_tag_en_int <= wrdata_reg(0); + pos_calc_monit1_tag_dly_int <= wrdata_reg(16 downto 1); + pos_calc_monit1_tag_dly_swb <= '1'; + pos_calc_monit1_tag_dly_swb_delay <= '1'; + pos_calc_monit1_tag_desync_cnt_rst_int <= wrdata_reg(17); + pos_calc_monit1_tag_desync_cnt_rst_int_delay <= wrdata_reg(17); + end if; + rddata_reg(0) <= pos_calc_monit1_tag_en_int; + rddata_reg(16 downto 1) <= pos_calc_monit1_tag_dly_int; + rddata_reg(17) <= '0'; + if (wb_we_i = '0') then + pos_calc_monit1_tag_desync_cnt_lwb <= '1'; + pos_calc_monit1_tag_desync_cnt_lwb_delay <= '1'; + pos_calc_monit1_tag_desync_cnt_lwb_in_progress <= '1'; + end if; + ack_sreg(5) <= '1'; + ack_in_progress <= '1'; + when "1000000" => + if (wb_we_i = '1') then + pos_calc_monit1_data_mask_ctl_en_int <= wrdata_reg(0); + end if; + rddata_reg(0) <= pos_calc_monit1_data_mask_ctl_en_int; + rddata_reg(1) <= 'X'; + rddata_reg(2) <= 'X'; + rddata_reg(3) <= 'X'; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1000001" => + if (wb_we_i = '1') then + pos_calc_monit1_data_mask_samples_beg_int <= wrdata_reg(15 downto 0); + pos_calc_monit1_data_mask_samples_beg_swb <= '1'; + pos_calc_monit1_data_mask_samples_beg_swb_delay <= '1'; + pos_calc_monit1_data_mask_samples_end_int <= wrdata_reg(31 downto 16); + pos_calc_monit1_data_mask_samples_end_swb <= '1'; + pos_calc_monit1_data_mask_samples_end_swb_delay <= '1'; + end if; + rddata_reg(15 downto 0) <= pos_calc_monit1_data_mask_samples_beg_int; + rddata_reg(31 downto 16) <= pos_calc_monit1_data_mask_samples_end_int; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1000010" => + if (wb_we_i = '1') then + pos_calc_monit_tag_en_int <= wrdata_reg(0); + pos_calc_monit_tag_dly_int <= wrdata_reg(16 downto 1); + pos_calc_monit_tag_dly_swb <= '1'; + pos_calc_monit_tag_dly_swb_delay <= '1'; + pos_calc_monit_tag_desync_cnt_rst_int <= wrdata_reg(17); + pos_calc_monit_tag_desync_cnt_rst_int_delay <= wrdata_reg(17); + end if; + rddata_reg(0) <= pos_calc_monit_tag_en_int; + rddata_reg(16 downto 1) <= pos_calc_monit_tag_dly_int; + rddata_reg(17) <= '0'; + if (wb_we_i = '0') then + pos_calc_monit_tag_desync_cnt_lwb <= '1'; + pos_calc_monit_tag_desync_cnt_lwb_delay <= '1'; + pos_calc_monit_tag_desync_cnt_lwb_in_progress <= '1'; + end if; + ack_sreg(5) <= '1'; + ack_in_progress <= '1'; + when "1000011" => + if (wb_we_i = '1') then + pos_calc_monit_data_mask_ctl_en_int <= wrdata_reg(0); + end if; + rddata_reg(0) <= pos_calc_monit_data_mask_ctl_en_int; + rddata_reg(1) <= 'X'; + rddata_reg(2) <= 'X'; + rddata_reg(3) <= 'X'; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1000100" => + if (wb_we_i = '1') then + pos_calc_monit_data_mask_samples_beg_int <= wrdata_reg(15 downto 0); + pos_calc_monit_data_mask_samples_beg_swb <= '1'; + pos_calc_monit_data_mask_samples_beg_swb_delay <= '1'; + pos_calc_monit_data_mask_samples_end_int <= wrdata_reg(31 downto 16); + pos_calc_monit_data_mask_samples_end_swb <= '1'; + pos_calc_monit_data_mask_samples_end_swb_delay <= '1'; + end if; + rddata_reg(15 downto 0) <= pos_calc_monit_data_mask_samples_beg_int; + rddata_reg(31 downto 16) <= pos_calc_monit_data_mask_samples_end_int; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1000101" => + if (wb_we_i = '1') then + pos_calc_offset_x_int <= wrdata_reg(31 downto 0); + pos_calc_offset_x_swb <= '1'; + pos_calc_offset_x_swb_delay <= '1'; + end if; + rddata_reg(31 downto 0) <= pos_calc_offset_x_int; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1000110" => + if (wb_we_i = '1') then + pos_calc_offset_y_int <= wrdata_reg(31 downto 0); + pos_calc_offset_y_swb <= '1'; + pos_calc_offset_y_swb_delay <= '1'; + end if; + rddata_reg(31 downto 0) <= pos_calc_offset_y_int; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "0100110" => + if (wb_we_i = '1') then + end if; + if (pos_calc_ampfifo_monit_rdreq_int_d0 = '0') then + pos_calc_ampfifo_monit_rdreq_int <= not pos_calc_ampfifo_monit_rdreq_int; + else + rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit_out_int(31 downto 0); + ack_in_progress <= '1'; + ack_sreg(0) <= '1'; + end if; + when "0100111" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit_out_int(63 downto 32); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0101000" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit_out_int(95 downto 64); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0101001" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit_out_int(127 downto 96); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0101010" => + if (wb_we_i = '1') then + end if; + rddata_reg(16) <= pos_calc_ampfifo_monit_full_int; + rddata_reg(17) <= pos_calc_ampfifo_monit_empty_int; + rddata_reg(3 downto 0) <= pos_calc_ampfifo_monit_usedw_int; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0101011" => + if (wb_we_i = '1') then + end if; + if (pos_calc_posfifo_monit_rdreq_int_d0 = '0') then + pos_calc_posfifo_monit_rdreq_int <= not pos_calc_posfifo_monit_rdreq_int; + else + rddata_reg(31 downto 0) <= pos_calc_posfifo_monit_out_int(31 downto 0); + ack_in_progress <= '1'; + ack_sreg(0) <= '1'; + end if; + when "0101100" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_posfifo_monit_out_int(63 downto 32); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0101101" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_posfifo_monit_out_int(95 downto 64); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0101110" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_posfifo_monit_out_int(127 downto 96); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0101111" => + if (wb_we_i = '1') then + end if; + rddata_reg(16) <= pos_calc_posfifo_monit_full_int; + rddata_reg(17) <= pos_calc_posfifo_monit_empty_int; + rddata_reg(3 downto 0) <= pos_calc_posfifo_monit_usedw_int; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0110000" => + if (wb_we_i = '1') then + end if; + if (pos_calc_ampfifo_monit1_rdreq_int_d0 = '0') then + pos_calc_ampfifo_monit1_rdreq_int <= not pos_calc_ampfifo_monit1_rdreq_int; + else + rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit1_out_int(31 downto 0); + ack_in_progress <= '1'; + ack_sreg(0) <= '1'; + end if; + when "0110001" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit1_out_int(63 downto 32); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0110010" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit1_out_int(95 downto 64); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0110011" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit1_out_int(127 downto 96); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0110100" => + if (wb_we_i = '1') then + end if; + rddata_reg(16) <= pos_calc_ampfifo_monit1_full_int; + rddata_reg(17) <= pos_calc_ampfifo_monit1_empty_int; + rddata_reg(3 downto 0) <= pos_calc_ampfifo_monit1_usedw_int; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0110101" => + if (wb_we_i = '1') then + end if; + if (pos_calc_posfifo_monit1_rdreq_int_d0 = '0') then + pos_calc_posfifo_monit1_rdreq_int <= not pos_calc_posfifo_monit1_rdreq_int; + else + rddata_reg(31 downto 0) <= pos_calc_posfifo_monit1_out_int(31 downto 0); + ack_in_progress <= '1'; + ack_sreg(0) <= '1'; + end if; + when "0110110" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_posfifo_monit1_out_int(63 downto 32); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0110111" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_posfifo_monit1_out_int(95 downto 64); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0111000" => + if (wb_we_i = '1') then + end if; + rddata_reg(31 downto 0) <= pos_calc_posfifo_monit1_out_int(127 downto 96); + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "0111001" => + if (wb_we_i = '1') then + end if; + rddata_reg(16) <= pos_calc_posfifo_monit1_full_int; + rddata_reg(17) <= pos_calc_posfifo_monit1_empty_int; + rddata_reg(3 downto 0) <= pos_calc_posfifo_monit1_usedw_int; + rddata_reg(4) <= 'X'; + rddata_reg(5) <= 'X'; + rddata_reg(6) <= 'X'; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when others => + -- prevent the slave from hanging the bus on invalid address + ack_in_progress <= '1'; + ack_sreg(0) <= '1'; + end case; + end if; + end if; + end if; + end process; + + + -- Drive the data output bus + wb_dat_o <= rddata_reg; + -- Config divisor threshold TBT + -- asynchronous std_logic_vector register : Config divisor threshold TBT (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_ds_tbt_thres_val_swb_s0 <= '0'; + pos_calc_ds_tbt_thres_val_swb_s1 <= '0'; + pos_calc_ds_tbt_thres_val_swb_s2 <= '0'; + pos_calc_ds_tbt_thres_val_o <= "00000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_ds_tbt_thres_val_swb_s0 <= pos_calc_ds_tbt_thres_val_swb; + pos_calc_ds_tbt_thres_val_swb_s1 <= pos_calc_ds_tbt_thres_val_swb_s0; + pos_calc_ds_tbt_thres_val_swb_s2 <= pos_calc_ds_tbt_thres_val_swb_s1; + if ((pos_calc_ds_tbt_thres_val_swb_s2 = '0') and (pos_calc_ds_tbt_thres_val_swb_s1 = '1')) then + pos_calc_ds_tbt_thres_val_o <= pos_calc_ds_tbt_thres_val_int; + end if; + end if; + end process; + + + -- Reserved + -- Config divisor threshold FOFB + -- asynchronous std_logic_vector register : Config divisor threshold FOFB (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_ds_fofb_thres_val_swb_s0 <= '0'; + pos_calc_ds_fofb_thres_val_swb_s1 <= '0'; + pos_calc_ds_fofb_thres_val_swb_s2 <= '0'; + pos_calc_ds_fofb_thres_val_o <= "00000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_ds_fofb_thres_val_swb_s0 <= pos_calc_ds_fofb_thres_val_swb; + pos_calc_ds_fofb_thres_val_swb_s1 <= pos_calc_ds_fofb_thres_val_swb_s0; + pos_calc_ds_fofb_thres_val_swb_s2 <= pos_calc_ds_fofb_thres_val_swb_s1; + if ((pos_calc_ds_fofb_thres_val_swb_s2 = '0') and (pos_calc_ds_fofb_thres_val_swb_s1 = '1')) then + pos_calc_ds_fofb_thres_val_o <= pos_calc_ds_fofb_thres_val_int; + end if; + end if; + end process; + + + -- Reserved + -- Config Divisor Threshold Monit. + -- asynchronous std_logic_vector register : Config Divisor Threshold Monit. (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_ds_monit_thres_val_swb_s0 <= '0'; + pos_calc_ds_monit_thres_val_swb_s1 <= '0'; + pos_calc_ds_monit_thres_val_swb_s2 <= '0'; + pos_calc_ds_monit_thres_val_o <= "00000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_ds_monit_thres_val_swb_s0 <= pos_calc_ds_monit_thres_val_swb; + pos_calc_ds_monit_thres_val_swb_s1 <= pos_calc_ds_monit_thres_val_swb_s0; + pos_calc_ds_monit_thres_val_swb_s2 <= pos_calc_ds_monit_thres_val_swb_s1; + if ((pos_calc_ds_monit_thres_val_swb_s2 = '0') and (pos_calc_ds_monit_thres_val_swb_s1 = '1')) then + pos_calc_ds_monit_thres_val_o <= pos_calc_ds_monit_thres_val_int; + end if; + end if; + end process; + + + -- Reserved + -- BPM sensitivity (X axis) parameter register + -- asynchronous std_logic_vector register : BPM sensitivity (X axis) parameter register (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_kx_val_swb_s0 <= '0'; + pos_calc_kx_val_swb_s1 <= '0'; + pos_calc_kx_val_swb_s2 <= '0'; + pos_calc_kx_val_o <= "0000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_kx_val_swb_s0 <= pos_calc_kx_val_swb; + pos_calc_kx_val_swb_s1 <= pos_calc_kx_val_swb_s0; + pos_calc_kx_val_swb_s2 <= pos_calc_kx_val_swb_s1; + if ((pos_calc_kx_val_swb_s2 = '0') and (pos_calc_kx_val_swb_s1 = '1')) then + pos_calc_kx_val_o <= pos_calc_kx_val_int; + end if; + end if; + end process; + + + -- Reserved + -- BPM sensitivity (Y axis) parameter register + -- asynchronous std_logic_vector register : BPM sensitivity (Y axis) parameter register (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_ky_val_swb_s0 <= '0'; + pos_calc_ky_val_swb_s1 <= '0'; + pos_calc_ky_val_swb_s2 <= '0'; + pos_calc_ky_val_o <= "0000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_ky_val_swb_s0 <= pos_calc_ky_val_swb; + pos_calc_ky_val_swb_s1 <= pos_calc_ky_val_swb_s0; + pos_calc_ky_val_swb_s2 <= pos_calc_ky_val_swb_s1; + if ((pos_calc_ky_val_swb_s2 = '0') and (pos_calc_ky_val_swb_s1 = '1')) then + pos_calc_ky_val_o <= pos_calc_ky_val_int; + end if; + end if; + end process; + + + -- Reserved + -- BPM sensitivity (Sum) parameter register + -- asynchronous std_logic_vector register : BPM sensitivity (Sum) parameter register (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_ksum_val_swb_s0 <= '0'; + pos_calc_ksum_val_swb_s1 <= '0'; + pos_calc_ksum_val_swb_s2 <= '0'; + pos_calc_ksum_val_o <= "0000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_ksum_val_swb_s0 <= pos_calc_ksum_val_swb; + pos_calc_ksum_val_swb_s1 <= pos_calc_ksum_val_swb_s0; + pos_calc_ksum_val_swb_s2 <= pos_calc_ksum_val_swb_s1; + if ((pos_calc_ksum_val_swb_s2 = '0') and (pos_calc_ksum_val_swb_s1 = '1')) then + pos_calc_ksum_val_o <= pos_calc_ksum_val_int; + end if; + end if; + end process; + + + -- Reserved + -- TBT incorrect counter for channels 0/1 (multiplexed) + -- asynchronous std_logic_vector register : TBT incorrect counter for channels 0/1 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_ctnr_tbt_ch01_lwb_s0 <= '0'; + pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 <= '0'; + pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 <= '0'; + pos_calc_dsp_ctnr_tbt_ch01_int <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_ctnr_tbt_ch01_lwb_s0 <= pos_calc_dsp_ctnr_tbt_ch01_lwb; + pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 <= pos_calc_dsp_ctnr_tbt_ch01_lwb_s0; + pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 <= pos_calc_dsp_ctnr_tbt_ch01_lwb_s1; + if ((pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 = '1') and (pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 = '0')) then + pos_calc_dsp_ctnr_tbt_ch01_int <= pos_calc_dsp_ctnr_tbt_ch01_i; + end if; + end if; + end process; + + + -- TBT incorrect counter for channels 2/3 (multiplexed) + -- asynchronous std_logic_vector register : TBT incorrect counter for channels 2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_ctnr_tbt_ch23_lwb_s0 <= '0'; + pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 <= '0'; + pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 <= '0'; + pos_calc_dsp_ctnr_tbt_ch23_int <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_ctnr_tbt_ch23_lwb_s0 <= pos_calc_dsp_ctnr_tbt_ch23_lwb; + pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 <= pos_calc_dsp_ctnr_tbt_ch23_lwb_s0; + pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 <= pos_calc_dsp_ctnr_tbt_ch23_lwb_s1; + if ((pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 = '1') and (pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 = '0')) then + pos_calc_dsp_ctnr_tbt_ch23_int <= pos_calc_dsp_ctnr_tbt_ch23_i; + end if; + end if; + end process; + + + -- FOFB incorrect counter for channels 0/1 (multiplexed) + -- asynchronous std_logic_vector register : FOFB incorrect counter for channels 0/1 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_ctnr_fofb_ch01_lwb_s0 <= '0'; + pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 <= '0'; + pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 <= '0'; + pos_calc_dsp_ctnr_fofb_ch01_int <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_ctnr_fofb_ch01_lwb_s0 <= pos_calc_dsp_ctnr_fofb_ch01_lwb; + pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 <= pos_calc_dsp_ctnr_fofb_ch01_lwb_s0; + pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 <= pos_calc_dsp_ctnr_fofb_ch01_lwb_s1; + if ((pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 = '1') and (pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 = '0')) then + pos_calc_dsp_ctnr_fofb_ch01_int <= pos_calc_dsp_ctnr_fofb_ch01_i; + end if; + end if; + end process; + + + -- FOFB incorrect counter for channels 2/3 (multiplexed) + -- asynchronous std_logic_vector register : FOFB incorrect counter for channels 2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_ctnr_fofb_ch23_lwb_s0 <= '0'; + pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 <= '0'; + pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 <= '0'; + pos_calc_dsp_ctnr_fofb_ch23_int <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_ctnr_fofb_ch23_lwb_s0 <= pos_calc_dsp_ctnr_fofb_ch23_lwb; + pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 <= pos_calc_dsp_ctnr_fofb_ch23_lwb_s0; + pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 <= pos_calc_dsp_ctnr_fofb_ch23_lwb_s1; + if ((pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 = '1') and (pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 = '0')) then + pos_calc_dsp_ctnr_fofb_ch23_int <= pos_calc_dsp_ctnr_fofb_ch23_i; + end if; + end if; + end process; + + + -- Monit. CIC incorrect counter for channels 0/1/2/3 (multiplexed) + -- asynchronous std_logic_vector register : Monit. CIC incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_ctnr1_monit_cic_lwb_s0 <= '0'; + pos_calc_dsp_ctnr1_monit_cic_lwb_s1 <= '0'; + pos_calc_dsp_ctnr1_monit_cic_lwb_s2 <= '0'; + pos_calc_dsp_ctnr1_monit_cic_int <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_ctnr1_monit_cic_lwb_s0 <= pos_calc_dsp_ctnr1_monit_cic_lwb; + pos_calc_dsp_ctnr1_monit_cic_lwb_s1 <= pos_calc_dsp_ctnr1_monit_cic_lwb_s0; + pos_calc_dsp_ctnr1_monit_cic_lwb_s2 <= pos_calc_dsp_ctnr1_monit_cic_lwb_s1; + if ((pos_calc_dsp_ctnr1_monit_cic_lwb_s1 = '1') and (pos_calc_dsp_ctnr1_monit_cic_lwb_s2 = '0')) then + pos_calc_dsp_ctnr1_monit_cic_int <= pos_calc_dsp_ctnr1_monit_cic_i; + end if; + end if; + end process; + + + -- Monit. CFIR incorrect counter for channels 0/1/2/3 (multiplexed) + -- asynchronous std_logic_vector register : Monit. CFIR incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_ctnr1_monit_cfir_lwb_s0 <= '0'; + pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 <= '0'; + pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 <= '0'; + pos_calc_dsp_ctnr1_monit_cfir_int <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_ctnr1_monit_cfir_lwb_s0 <= pos_calc_dsp_ctnr1_monit_cfir_lwb; + pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 <= pos_calc_dsp_ctnr1_monit_cfir_lwb_s0; + pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 <= pos_calc_dsp_ctnr1_monit_cfir_lwb_s1; + if ((pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 = '1') and (pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 = '0')) then + pos_calc_dsp_ctnr1_monit_cfir_int <= pos_calc_dsp_ctnr1_monit_cfir_i; + end if; + end if; + end process; + + + -- Monit. PFIR incorrect counter for channels 0/1/2/3 (multiplexed) + -- asynchronous std_logic_vector register : Monit. PFIR incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_ctnr2_monit_pfir_lwb_s0 <= '0'; + pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 <= '0'; + pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 <= '0'; + pos_calc_dsp_ctnr2_monit_pfir_int <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_ctnr2_monit_pfir_lwb_s0 <= pos_calc_dsp_ctnr2_monit_pfir_lwb; + pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 <= pos_calc_dsp_ctnr2_monit_pfir_lwb_s0; + pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 <= pos_calc_dsp_ctnr2_monit_pfir_lwb_s1; + if ((pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 = '1') and (pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 = '0')) then + pos_calc_dsp_ctnr2_monit_pfir_int <= pos_calc_dsp_ctnr2_monit_pfir_i; + end if; + end if; + end process; + + + -- Monit. 0.1 Hz incorrect counter for channels 0/1/2/3 (multiplexed) + -- asynchronous std_logic_vector register : Monit. 0.1 Hz incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0 <= '0'; + pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 <= '0'; + pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 <= '0'; + pos_calc_dsp_ctnr2_monit_fir_01_int <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0 <= pos_calc_dsp_ctnr2_monit_fir_01_lwb; + pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 <= pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0; + pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 <= pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1; + if ((pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 = '1') and (pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 = '0')) then + pos_calc_dsp_ctnr2_monit_fir_01_int <= pos_calc_dsp_ctnr2_monit_fir_01_i; + end if; + end if; + end process; + + + -- Clear TBT error counters + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_err_clr_tbt_o <= '0'; + pos_calc_dsp_err_clr_tbt_sync0 <= '0'; + pos_calc_dsp_err_clr_tbt_sync1 <= '0'; + pos_calc_dsp_err_clr_tbt_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_err_clr_tbt_sync0 <= pos_calc_dsp_err_clr_tbt_int; + pos_calc_dsp_err_clr_tbt_sync1 <= pos_calc_dsp_err_clr_tbt_sync0; + pos_calc_dsp_err_clr_tbt_sync2 <= pos_calc_dsp_err_clr_tbt_sync1; + pos_calc_dsp_err_clr_tbt_o <= pos_calc_dsp_err_clr_tbt_sync2 and (not pos_calc_dsp_err_clr_tbt_sync1); + end if; + end process; + + + -- Clear FOFB error counters + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_err_clr_fofb_o <= '0'; + pos_calc_dsp_err_clr_fofb_sync0 <= '0'; + pos_calc_dsp_err_clr_fofb_sync1 <= '0'; + pos_calc_dsp_err_clr_fofb_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_err_clr_fofb_sync0 <= pos_calc_dsp_err_clr_fofb_int; + pos_calc_dsp_err_clr_fofb_sync1 <= pos_calc_dsp_err_clr_fofb_sync0; + pos_calc_dsp_err_clr_fofb_sync2 <= pos_calc_dsp_err_clr_fofb_sync1; + pos_calc_dsp_err_clr_fofb_o <= pos_calc_dsp_err_clr_fofb_sync2 and (not pos_calc_dsp_err_clr_fofb_sync1); + end if; + end process; + + + -- Clear Monit. CIC and CFIR error counters + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_err_clr_monit_part1_o <= '0'; + pos_calc_dsp_err_clr_monit_part1_sync0 <= '0'; + pos_calc_dsp_err_clr_monit_part1_sync1 <= '0'; + pos_calc_dsp_err_clr_monit_part1_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_err_clr_monit_part1_sync0 <= pos_calc_dsp_err_clr_monit_part1_int; + pos_calc_dsp_err_clr_monit_part1_sync1 <= pos_calc_dsp_err_clr_monit_part1_sync0; + pos_calc_dsp_err_clr_monit_part1_sync2 <= pos_calc_dsp_err_clr_monit_part1_sync1; + pos_calc_dsp_err_clr_monit_part1_o <= pos_calc_dsp_err_clr_monit_part1_sync2 and (not pos_calc_dsp_err_clr_monit_part1_sync1); + end if; + end process; + + + -- Clear Monit. PFIR and Monit. 0.1 error counters + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dsp_err_clr_monit_part2_o <= '0'; + pos_calc_dsp_err_clr_monit_part2_sync0 <= '0'; + pos_calc_dsp_err_clr_monit_part2_sync1 <= '0'; + pos_calc_dsp_err_clr_monit_part2_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dsp_err_clr_monit_part2_sync0 <= pos_calc_dsp_err_clr_monit_part2_int; + pos_calc_dsp_err_clr_monit_part2_sync1 <= pos_calc_dsp_err_clr_monit_part2_sync0; + pos_calc_dsp_err_clr_monit_part2_sync2 <= pos_calc_dsp_err_clr_monit_part2_sync1; + pos_calc_dsp_err_clr_monit_part2_o <= pos_calc_dsp_err_clr_monit_part2_sync2 and (not pos_calc_dsp_err_clr_monit_part2_sync1); + end if; + end process; + + + -- Valid signal for channel 0 DDS + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_cfg_valid_ch0_o <= '0'; + pos_calc_dds_cfg_valid_ch0_sync0 <= '0'; + pos_calc_dds_cfg_valid_ch0_sync1 <= '0'; + pos_calc_dds_cfg_valid_ch0_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_cfg_valid_ch0_sync0 <= pos_calc_dds_cfg_valid_ch0_int; + pos_calc_dds_cfg_valid_ch0_sync1 <= pos_calc_dds_cfg_valid_ch0_sync0; + pos_calc_dds_cfg_valid_ch0_sync2 <= pos_calc_dds_cfg_valid_ch0_sync1; + pos_calc_dds_cfg_valid_ch0_o <= pos_calc_dds_cfg_valid_ch0_sync2 and (not pos_calc_dds_cfg_valid_ch0_sync1); + end if; + end process; + + + -- Test data counter for all channels + -- synchronizer chain for field : Test data counter for all channels (type RW/RO, clk_sys_i <-> fs_clk2x_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_cfg_test_data_o <= '0'; + pos_calc_dds_cfg_test_data_sync0 <= '0'; + pos_calc_dds_cfg_test_data_sync1 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_cfg_test_data_sync0 <= pos_calc_dds_cfg_test_data_int; + pos_calc_dds_cfg_test_data_sync1 <= pos_calc_dds_cfg_test_data_sync0; + pos_calc_dds_cfg_test_data_o <= pos_calc_dds_cfg_test_data_sync1; + end if; + end process; + + + -- Reserved + -- Valid signal for channel 1 DDS + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_cfg_valid_ch1_o <= '0'; + pos_calc_dds_cfg_valid_ch1_sync0 <= '0'; + pos_calc_dds_cfg_valid_ch1_sync1 <= '0'; + pos_calc_dds_cfg_valid_ch1_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_cfg_valid_ch1_sync0 <= pos_calc_dds_cfg_valid_ch1_int; + pos_calc_dds_cfg_valid_ch1_sync1 <= pos_calc_dds_cfg_valid_ch1_sync0; + pos_calc_dds_cfg_valid_ch1_sync2 <= pos_calc_dds_cfg_valid_ch1_sync1; + pos_calc_dds_cfg_valid_ch1_o <= pos_calc_dds_cfg_valid_ch1_sync2 and (not pos_calc_dds_cfg_valid_ch1_sync1); + end if; + end process; + + + -- Reserved + -- Valid signal for channel 2 DDS + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_cfg_valid_ch2_o <= '0'; + pos_calc_dds_cfg_valid_ch2_sync0 <= '0'; + pos_calc_dds_cfg_valid_ch2_sync1 <= '0'; + pos_calc_dds_cfg_valid_ch2_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_cfg_valid_ch2_sync0 <= pos_calc_dds_cfg_valid_ch2_int; + pos_calc_dds_cfg_valid_ch2_sync1 <= pos_calc_dds_cfg_valid_ch2_sync0; + pos_calc_dds_cfg_valid_ch2_sync2 <= pos_calc_dds_cfg_valid_ch2_sync1; + pos_calc_dds_cfg_valid_ch2_o <= pos_calc_dds_cfg_valid_ch2_sync2 and (not pos_calc_dds_cfg_valid_ch2_sync1); + end if; + end process; + + + -- Reserved + -- Valid signal for channel 3 DDS + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_cfg_valid_ch3_o <= '0'; + pos_calc_dds_cfg_valid_ch3_sync0 <= '0'; + pos_calc_dds_cfg_valid_ch3_sync1 <= '0'; + pos_calc_dds_cfg_valid_ch3_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_cfg_valid_ch3_sync0 <= pos_calc_dds_cfg_valid_ch3_int; + pos_calc_dds_cfg_valid_ch3_sync1 <= pos_calc_dds_cfg_valid_ch3_sync0; + pos_calc_dds_cfg_valid_ch3_sync2 <= pos_calc_dds_cfg_valid_ch3_sync1; + pos_calc_dds_cfg_valid_ch3_o <= pos_calc_dds_cfg_valid_ch3_sync2 and (not pos_calc_dds_cfg_valid_ch3_sync1); + end if; + end process; + + + -- Reserved + -- DDS phase increment parameter register for channel 0 + -- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 0 (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_pinc_ch0_val_swb_s0 <= '0'; + pos_calc_dds_pinc_ch0_val_swb_s1 <= '0'; + pos_calc_dds_pinc_ch0_val_swb_s2 <= '0'; + pos_calc_dds_pinc_ch0_val_o <= "000000000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_pinc_ch0_val_swb_s0 <= pos_calc_dds_pinc_ch0_val_swb; + pos_calc_dds_pinc_ch0_val_swb_s1 <= pos_calc_dds_pinc_ch0_val_swb_s0; + pos_calc_dds_pinc_ch0_val_swb_s2 <= pos_calc_dds_pinc_ch0_val_swb_s1; + if ((pos_calc_dds_pinc_ch0_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch0_val_swb_s1 = '1')) then + pos_calc_dds_pinc_ch0_val_o <= pos_calc_dds_pinc_ch0_val_int; + end if; + end if; + end process; + + + -- Reserved + -- DDS phase increment parameter register for channel 1 + -- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 1 (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_pinc_ch1_val_swb_s0 <= '0'; + pos_calc_dds_pinc_ch1_val_swb_s1 <= '0'; + pos_calc_dds_pinc_ch1_val_swb_s2 <= '0'; + pos_calc_dds_pinc_ch1_val_o <= "000000000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_pinc_ch1_val_swb_s0 <= pos_calc_dds_pinc_ch1_val_swb; + pos_calc_dds_pinc_ch1_val_swb_s1 <= pos_calc_dds_pinc_ch1_val_swb_s0; + pos_calc_dds_pinc_ch1_val_swb_s2 <= pos_calc_dds_pinc_ch1_val_swb_s1; + if ((pos_calc_dds_pinc_ch1_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch1_val_swb_s1 = '1')) then + pos_calc_dds_pinc_ch1_val_o <= pos_calc_dds_pinc_ch1_val_int; + end if; + end if; + end process; + + + -- Reserved + -- DDS phase increment parameter register for channel 2 + -- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 2 (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_pinc_ch2_val_swb_s0 <= '0'; + pos_calc_dds_pinc_ch2_val_swb_s1 <= '0'; + pos_calc_dds_pinc_ch2_val_swb_s2 <= '0'; + pos_calc_dds_pinc_ch2_val_o <= "000000000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_pinc_ch2_val_swb_s0 <= pos_calc_dds_pinc_ch2_val_swb; + pos_calc_dds_pinc_ch2_val_swb_s1 <= pos_calc_dds_pinc_ch2_val_swb_s0; + pos_calc_dds_pinc_ch2_val_swb_s2 <= pos_calc_dds_pinc_ch2_val_swb_s1; + if ((pos_calc_dds_pinc_ch2_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch2_val_swb_s1 = '1')) then + pos_calc_dds_pinc_ch2_val_o <= pos_calc_dds_pinc_ch2_val_int; + end if; + end if; + end process; + + + -- Reserved + -- DDS phase increment parameter register for channel 3 + -- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 3 (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_pinc_ch3_val_swb_s0 <= '0'; + pos_calc_dds_pinc_ch3_val_swb_s1 <= '0'; + pos_calc_dds_pinc_ch3_val_swb_s2 <= '0'; + pos_calc_dds_pinc_ch3_val_o <= "000000000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_pinc_ch3_val_swb_s0 <= pos_calc_dds_pinc_ch3_val_swb; + pos_calc_dds_pinc_ch3_val_swb_s1 <= pos_calc_dds_pinc_ch3_val_swb_s0; + pos_calc_dds_pinc_ch3_val_swb_s2 <= pos_calc_dds_pinc_ch3_val_swb_s1; + if ((pos_calc_dds_pinc_ch3_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch3_val_swb_s1 = '1')) then + pos_calc_dds_pinc_ch3_val_o <= pos_calc_dds_pinc_ch3_val_int; + end if; + end if; + end process; + + + -- Reserved + -- DDS phase offset parameter register for channel 0 + -- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 0 (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_poff_ch0_val_swb_s0 <= '0'; + pos_calc_dds_poff_ch0_val_swb_s1 <= '0'; + pos_calc_dds_poff_ch0_val_swb_s2 <= '0'; + pos_calc_dds_poff_ch0_val_o <= "000000000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_poff_ch0_val_swb_s0 <= pos_calc_dds_poff_ch0_val_swb; + pos_calc_dds_poff_ch0_val_swb_s1 <= pos_calc_dds_poff_ch0_val_swb_s0; + pos_calc_dds_poff_ch0_val_swb_s2 <= pos_calc_dds_poff_ch0_val_swb_s1; + if ((pos_calc_dds_poff_ch0_val_swb_s2 = '0') and (pos_calc_dds_poff_ch0_val_swb_s1 = '1')) then + pos_calc_dds_poff_ch0_val_o <= pos_calc_dds_poff_ch0_val_int; + end if; + end if; + end process; + + + -- Reserved + -- DDS phase offset parameter register for channel 1 + -- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 1 (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_poff_ch1_val_swb_s0 <= '0'; + pos_calc_dds_poff_ch1_val_swb_s1 <= '0'; + pos_calc_dds_poff_ch1_val_swb_s2 <= '0'; + pos_calc_dds_poff_ch1_val_o <= "000000000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_poff_ch1_val_swb_s0 <= pos_calc_dds_poff_ch1_val_swb; + pos_calc_dds_poff_ch1_val_swb_s1 <= pos_calc_dds_poff_ch1_val_swb_s0; + pos_calc_dds_poff_ch1_val_swb_s2 <= pos_calc_dds_poff_ch1_val_swb_s1; + if ((pos_calc_dds_poff_ch1_val_swb_s2 = '0') and (pos_calc_dds_poff_ch1_val_swb_s1 = '1')) then + pos_calc_dds_poff_ch1_val_o <= pos_calc_dds_poff_ch1_val_int; + end if; + end if; + end process; + + + -- Reserved + -- DDS phase offset parameter register for channel 2 + -- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 2 (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_poff_ch2_val_swb_s0 <= '0'; + pos_calc_dds_poff_ch2_val_swb_s1 <= '0'; + pos_calc_dds_poff_ch2_val_swb_s2 <= '0'; + pos_calc_dds_poff_ch2_val_o <= "000000000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_poff_ch2_val_swb_s0 <= pos_calc_dds_poff_ch2_val_swb; + pos_calc_dds_poff_ch2_val_swb_s1 <= pos_calc_dds_poff_ch2_val_swb_s0; + pos_calc_dds_poff_ch2_val_swb_s2 <= pos_calc_dds_poff_ch2_val_swb_s1; + if ((pos_calc_dds_poff_ch2_val_swb_s2 = '0') and (pos_calc_dds_poff_ch2_val_swb_s1 = '1')) then + pos_calc_dds_poff_ch2_val_o <= pos_calc_dds_poff_ch2_val_int; + end if; + end if; + end process; + + + -- Reserved + -- DDS phase offset parameter register for channel 3 + -- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 3 (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_dds_poff_ch3_val_swb_s0 <= '0'; + pos_calc_dds_poff_ch3_val_swb_s1 <= '0'; + pos_calc_dds_poff_ch3_val_swb_s2 <= '0'; + pos_calc_dds_poff_ch3_val_o <= "000000000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_dds_poff_ch3_val_swb_s0 <= pos_calc_dds_poff_ch3_val_swb; + pos_calc_dds_poff_ch3_val_swb_s1 <= pos_calc_dds_poff_ch3_val_swb_s0; + pos_calc_dds_poff_ch3_val_swb_s2 <= pos_calc_dds_poff_ch3_val_swb_s1; + if ((pos_calc_dds_poff_ch3_val_swb_s2 = '0') and (pos_calc_dds_poff_ch3_val_swb_s1 = '1')) then + pos_calc_dds_poff_ch3_val_o <= pos_calc_dds_poff_ch3_val_int; + end if; + end if; + end process; + + + -- Reserved + -- Monit. Amplitude Value for channel 0 + -- Monit. Amplitude Value for channel 1 + -- Monit. Amplitude Value for channel 2 + -- Monit. Amplitude Value for channel 3 + -- Monit. X Position Value + -- Monit. Y Position Value + -- Monit. Q Position Value + -- Monit. Sum Position Value + -- Monit. Amp/Pos Update (ignore on read) + -- pass-through field: Monit. Amp/Pos Update (ignore on read) in register: Monit. Amp/Pos update trigger + pos_calc_dsp_monit_updt_o <= wrdata_reg(31 downto 0); + -- Monit. 1 Amplitude Value for channel 0 + -- Monit. 1 Amplitude Value for channel 1 + -- Monit. 1 Amplitude Value for channel 2 + -- Monit. 1 Amplitude Value for channel 3 + -- Monit. 1 X Position Value + -- Monit. 1 Y Position Value + -- Monit. 1 Q Position Value + -- Monit. 1 Sum Position Value + -- Monit. 1 Amp/Pos Update (ignore on read) + -- pass-through field: Monit. 1 Amp/Pos Update (ignore on read) in register: Monit. 1 Amp/Pos update trigger + pos_calc_dsp_monit1_updt_o <= wrdata_reg(31 downto 0); + -- extra code for reg/fifo/mem: AMP FIFO Monitoring + pos_calc_ampfifo_monit_in_int(31 downto 0) <= pos_calc_ampfifo_monit_amp_ch0_i; + pos_calc_ampfifo_monit_in_int(63 downto 32) <= pos_calc_ampfifo_monit_amp_ch1_i; + pos_calc_ampfifo_monit_in_int(95 downto 64) <= pos_calc_ampfifo_monit_amp_ch2_i; + pos_calc_ampfifo_monit_in_int(127 downto 96) <= pos_calc_ampfifo_monit_amp_ch3_i; + pos_calc_ampfifo_monit_rst_n <= rst_n_i; + pos_calc_ampfifo_monit_INST: wbgen2_fifo_sync + generic map ( + g_size => 16, + g_width => 128, + g_usedw_size => 4 + ) + port map ( + wr_req_i => pos_calc_ampfifo_monit_wr_req_i, + wr_full_o => pos_calc_ampfifo_monit_wr_full_o, + wr_empty_o => pos_calc_ampfifo_monit_wr_empty_o, + wr_usedw_o => pos_calc_ampfifo_monit_wr_usedw_o, + rd_full_o => pos_calc_ampfifo_monit_full_int, + rd_empty_o => pos_calc_ampfifo_monit_empty_int, + rd_usedw_o => pos_calc_ampfifo_monit_usedw_int, + rd_req_i => pos_calc_ampfifo_monit_rdreq_int, + rst_n_i => pos_calc_ampfifo_monit_rst_n, + clk_i => clk_sys_i, + wr_data_i => pos_calc_ampfifo_monit_in_int, + rd_data_o => pos_calc_ampfifo_monit_out_int + ); + + -- extra code for reg/fifo/mem: POS FIFO Monitoring + pos_calc_posfifo_monit_in_int(31 downto 0) <= pos_calc_posfifo_monit_pos_x_i; + pos_calc_posfifo_monit_in_int(63 downto 32) <= pos_calc_posfifo_monit_pos_y_i; + pos_calc_posfifo_monit_in_int(95 downto 64) <= pos_calc_posfifo_monit_pos_q_i; + pos_calc_posfifo_monit_in_int(127 downto 96) <= pos_calc_posfifo_monit_pos_sum_i; + pos_calc_posfifo_monit_rst_n <= rst_n_i; + pos_calc_posfifo_monit_INST: wbgen2_fifo_sync + generic map ( + g_size => 16, + g_width => 128, + g_usedw_size => 4 + ) + port map ( + wr_req_i => pos_calc_posfifo_monit_wr_req_i, + wr_full_o => pos_calc_posfifo_monit_wr_full_o, + wr_empty_o => pos_calc_posfifo_monit_wr_empty_o, + wr_usedw_o => pos_calc_posfifo_monit_wr_usedw_o, + rd_full_o => pos_calc_posfifo_monit_full_int, + rd_empty_o => pos_calc_posfifo_monit_empty_int, + rd_usedw_o => pos_calc_posfifo_monit_usedw_int, + rd_req_i => pos_calc_posfifo_monit_rdreq_int, + rst_n_i => pos_calc_posfifo_monit_rst_n, + clk_i => clk_sys_i, + wr_data_i => pos_calc_posfifo_monit_in_int, + rd_data_o => pos_calc_posfifo_monit_out_int + ); + + -- extra code for reg/fifo/mem: AMP FIFO Monitoring 1 + pos_calc_ampfifo_monit1_in_int(31 downto 0) <= pos_calc_ampfifo_monit1_amp_ch0_i; + pos_calc_ampfifo_monit1_in_int(63 downto 32) <= pos_calc_ampfifo_monit1_amp_ch1_i; + pos_calc_ampfifo_monit1_in_int(95 downto 64) <= pos_calc_ampfifo_monit1_amp_ch2_i; + pos_calc_ampfifo_monit1_in_int(127 downto 96) <= pos_calc_ampfifo_monit1_amp_ch3_i; + pos_calc_ampfifo_monit1_rst_n <= rst_n_i; + pos_calc_ampfifo_monit1_INST: wbgen2_fifo_sync + generic map ( + g_size => 16, + g_width => 128, + g_usedw_size => 4 + ) + port map ( + wr_req_i => pos_calc_ampfifo_monit1_wr_req_i, + wr_full_o => pos_calc_ampfifo_monit1_wr_full_o, + wr_empty_o => pos_calc_ampfifo_monit1_wr_empty_o, + wr_usedw_o => pos_calc_ampfifo_monit1_wr_usedw_o, + rd_full_o => pos_calc_ampfifo_monit1_full_int, + rd_empty_o => pos_calc_ampfifo_monit1_empty_int, + rd_usedw_o => pos_calc_ampfifo_monit1_usedw_int, + rd_req_i => pos_calc_ampfifo_monit1_rdreq_int, + rst_n_i => pos_calc_ampfifo_monit1_rst_n, + clk_i => clk_sys_i, + wr_data_i => pos_calc_ampfifo_monit1_in_int, + rd_data_o => pos_calc_ampfifo_monit1_out_int + ); + + -- extra code for reg/fifo/mem: POS FIFO Monitoring 1 + pos_calc_posfifo_monit1_in_int(31 downto 0) <= pos_calc_posfifo_monit1_pos_x_i; + pos_calc_posfifo_monit1_in_int(63 downto 32) <= pos_calc_posfifo_monit1_pos_y_i; + pos_calc_posfifo_monit1_in_int(95 downto 64) <= pos_calc_posfifo_monit1_pos_q_i; + pos_calc_posfifo_monit1_in_int(127 downto 96) <= pos_calc_posfifo_monit1_pos_sum_i; + pos_calc_posfifo_monit1_rst_n <= rst_n_i; + pos_calc_posfifo_monit1_INST: wbgen2_fifo_sync + generic map ( + g_size => 16, + g_width => 128, + g_usedw_size => 4 + ) + port map ( + wr_req_i => pos_calc_posfifo_monit1_wr_req_i, + wr_full_o => pos_calc_posfifo_monit1_wr_full_o, + wr_empty_o => pos_calc_posfifo_monit1_wr_empty_o, + wr_usedw_o => pos_calc_posfifo_monit1_wr_usedw_o, + rd_full_o => pos_calc_posfifo_monit1_full_int, + rd_empty_o => pos_calc_posfifo_monit1_empty_int, + rd_usedw_o => pos_calc_posfifo_monit1_usedw_int, + rd_req_i => pos_calc_posfifo_monit1_rdreq_int, + rst_n_i => pos_calc_posfifo_monit1_rst_n, + clk_i => clk_sys_i, + wr_data_i => pos_calc_posfifo_monit1_in_int, + rd_data_o => pos_calc_posfifo_monit1_out_int + ); + + -- Tag Synchronization Enable + -- synchronizer chain for field : Tag Synchronization Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_sw_tag_en_o <= '0'; + pos_calc_sw_tag_en_sync0 <= '0'; + pos_calc_sw_tag_en_sync1 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_sw_tag_en_sync0 <= pos_calc_sw_tag_en_int; + pos_calc_sw_tag_en_sync1 <= pos_calc_sw_tag_en_sync0; + pos_calc_sw_tag_en_o <= pos_calc_sw_tag_en_sync1; + end if; + end process; + + + -- Switching Desynchronization Counter Reset + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_sw_tag_desync_cnt_rst_o <= '0'; + pos_calc_sw_tag_desync_cnt_rst_sync0 <= '0'; + pos_calc_sw_tag_desync_cnt_rst_sync1 <= '0'; + pos_calc_sw_tag_desync_cnt_rst_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_sw_tag_desync_cnt_rst_sync0 <= pos_calc_sw_tag_desync_cnt_rst_int; + pos_calc_sw_tag_desync_cnt_rst_sync1 <= pos_calc_sw_tag_desync_cnt_rst_sync0; + pos_calc_sw_tag_desync_cnt_rst_sync2 <= pos_calc_sw_tag_desync_cnt_rst_sync1; + pos_calc_sw_tag_desync_cnt_rst_o <= pos_calc_sw_tag_desync_cnt_rst_sync2 and (not pos_calc_sw_tag_desync_cnt_rst_sync1); + end if; + end process; + + + -- Switching Desynchronization Counter + -- asynchronous std_logic_vector register : Switching Desynchronization Counter (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_sw_tag_desync_cnt_lwb_s0 <= '0'; + pos_calc_sw_tag_desync_cnt_lwb_s1 <= '0'; + pos_calc_sw_tag_desync_cnt_lwb_s2 <= '0'; + pos_calc_sw_tag_desync_cnt_int <= "00000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_sw_tag_desync_cnt_lwb_s0 <= pos_calc_sw_tag_desync_cnt_lwb; + pos_calc_sw_tag_desync_cnt_lwb_s1 <= pos_calc_sw_tag_desync_cnt_lwb_s0; + pos_calc_sw_tag_desync_cnt_lwb_s2 <= pos_calc_sw_tag_desync_cnt_lwb_s1; + if ((pos_calc_sw_tag_desync_cnt_lwb_s1 = '1') and (pos_calc_sw_tag_desync_cnt_lwb_s2 = '0')) then + pos_calc_sw_tag_desync_cnt_int <= pos_calc_sw_tag_desync_cnt_i; + end if; + end if; + end process; + + + -- Switching Data Mask Enable + -- synchronizer chain for field : Switching Data Mask Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_sw_data_mask_en_o <= '0'; + pos_calc_sw_data_mask_en_sync0 <= '0'; + pos_calc_sw_data_mask_en_sync1 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_sw_data_mask_en_sync0 <= pos_calc_sw_data_mask_en_int; + pos_calc_sw_data_mask_en_sync1 <= pos_calc_sw_data_mask_en_sync0; + pos_calc_sw_data_mask_en_o <= pos_calc_sw_data_mask_en_sync1; + end if; + end process; + + + -- Switching Data Mask Samples + -- asynchronous std_logic_vector register : Switching Data Mask Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_sw_data_mask_samples_swb_s0 <= '0'; + pos_calc_sw_data_mask_samples_swb_s1 <= '0'; + pos_calc_sw_data_mask_samples_swb_s2 <= '0'; + pos_calc_sw_data_mask_samples_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_sw_data_mask_samples_swb_s0 <= pos_calc_sw_data_mask_samples_swb; + pos_calc_sw_data_mask_samples_swb_s1 <= pos_calc_sw_data_mask_samples_swb_s0; + pos_calc_sw_data_mask_samples_swb_s2 <= pos_calc_sw_data_mask_samples_swb_s1; + if ((pos_calc_sw_data_mask_samples_swb_s2 = '0') and (pos_calc_sw_data_mask_samples_swb_s1 = '1')) then + pos_calc_sw_data_mask_samples_o <= pos_calc_sw_data_mask_samples_int; + end if; + end if; + end process; + + + -- TbT Synchronizing Trigger Enable + -- synchronizer chain for field : TbT Synchronizing Trigger Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_tbt_tag_en_o <= '0'; + pos_calc_tbt_tag_en_sync0 <= '0'; + pos_calc_tbt_tag_en_sync1 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_tbt_tag_en_sync0 <= pos_calc_tbt_tag_en_int; + pos_calc_tbt_tag_en_sync1 <= pos_calc_tbt_tag_en_sync0; + pos_calc_tbt_tag_en_o <= pos_calc_tbt_tag_en_sync1; + end if; + end process; + + + -- TbT Synchronizing Trigger Delay + -- asynchronous std_logic_vector register : TbT Synchronizing Trigger Delay (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_tbt_tag_dly_swb_s0 <= '0'; + pos_calc_tbt_tag_dly_swb_s1 <= '0'; + pos_calc_tbt_tag_dly_swb_s2 <= '0'; + pos_calc_tbt_tag_dly_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_tbt_tag_dly_swb_s0 <= pos_calc_tbt_tag_dly_swb; + pos_calc_tbt_tag_dly_swb_s1 <= pos_calc_tbt_tag_dly_swb_s0; + pos_calc_tbt_tag_dly_swb_s2 <= pos_calc_tbt_tag_dly_swb_s1; + if ((pos_calc_tbt_tag_dly_swb_s2 = '0') and (pos_calc_tbt_tag_dly_swb_s1 = '1')) then + pos_calc_tbt_tag_dly_o <= pos_calc_tbt_tag_dly_int; + end if; + end if; + end process; + + + -- TbT Desynchronization Counter Reset + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_tbt_tag_desync_cnt_rst_o <= '0'; + pos_calc_tbt_tag_desync_cnt_rst_sync0 <= '0'; + pos_calc_tbt_tag_desync_cnt_rst_sync1 <= '0'; + pos_calc_tbt_tag_desync_cnt_rst_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_tbt_tag_desync_cnt_rst_sync0 <= pos_calc_tbt_tag_desync_cnt_rst_int; + pos_calc_tbt_tag_desync_cnt_rst_sync1 <= pos_calc_tbt_tag_desync_cnt_rst_sync0; + pos_calc_tbt_tag_desync_cnt_rst_sync2 <= pos_calc_tbt_tag_desync_cnt_rst_sync1; + pos_calc_tbt_tag_desync_cnt_rst_o <= pos_calc_tbt_tag_desync_cnt_rst_sync2 and (not pos_calc_tbt_tag_desync_cnt_rst_sync1); + end if; + end process; + + + -- TbT Desynchronization Counter + -- asynchronous std_logic_vector register : TbT Desynchronization Counter (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_tbt_tag_desync_cnt_lwb_s0 <= '0'; + pos_calc_tbt_tag_desync_cnt_lwb_s1 <= '0'; + pos_calc_tbt_tag_desync_cnt_lwb_s2 <= '0'; + pos_calc_tbt_tag_desync_cnt_int <= "00000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_tbt_tag_desync_cnt_lwb_s0 <= pos_calc_tbt_tag_desync_cnt_lwb; + pos_calc_tbt_tag_desync_cnt_lwb_s1 <= pos_calc_tbt_tag_desync_cnt_lwb_s0; + pos_calc_tbt_tag_desync_cnt_lwb_s2 <= pos_calc_tbt_tag_desync_cnt_lwb_s1; + if ((pos_calc_tbt_tag_desync_cnt_lwb_s1 = '1') and (pos_calc_tbt_tag_desync_cnt_lwb_s2 = '0')) then + pos_calc_tbt_tag_desync_cnt_int <= pos_calc_tbt_tag_desync_cnt_i; + end if; + end if; + end process; + + + -- TbT Masking Enable + -- synchronizer chain for field : TbT Masking Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_tbt_data_mask_ctl_en_o <= '0'; + pos_calc_tbt_data_mask_ctl_en_sync0 <= '0'; + pos_calc_tbt_data_mask_ctl_en_sync1 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_tbt_data_mask_ctl_en_sync0 <= pos_calc_tbt_data_mask_ctl_en_int; + pos_calc_tbt_data_mask_ctl_en_sync1 <= pos_calc_tbt_data_mask_ctl_en_sync0; + pos_calc_tbt_data_mask_ctl_en_o <= pos_calc_tbt_data_mask_ctl_en_sync1; + end if; + end process; + + + -- TbT Beginning Data Masking Samples + -- asynchronous std_logic_vector register : TbT Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_tbt_data_mask_samples_beg_swb_s0 <= '0'; + pos_calc_tbt_data_mask_samples_beg_swb_s1 <= '0'; + pos_calc_tbt_data_mask_samples_beg_swb_s2 <= '0'; + pos_calc_tbt_data_mask_samples_beg_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_tbt_data_mask_samples_beg_swb_s0 <= pos_calc_tbt_data_mask_samples_beg_swb; + pos_calc_tbt_data_mask_samples_beg_swb_s1 <= pos_calc_tbt_data_mask_samples_beg_swb_s0; + pos_calc_tbt_data_mask_samples_beg_swb_s2 <= pos_calc_tbt_data_mask_samples_beg_swb_s1; + if ((pos_calc_tbt_data_mask_samples_beg_swb_s2 = '0') and (pos_calc_tbt_data_mask_samples_beg_swb_s1 = '1')) then + pos_calc_tbt_data_mask_samples_beg_o <= pos_calc_tbt_data_mask_samples_beg_int; + end if; + end if; + end process; + + + -- TbT Beginning Data Masking Samples + -- asynchronous std_logic_vector register : TbT Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_tbt_data_mask_samples_end_swb_s0 <= '0'; + pos_calc_tbt_data_mask_samples_end_swb_s1 <= '0'; + pos_calc_tbt_data_mask_samples_end_swb_s2 <= '0'; + pos_calc_tbt_data_mask_samples_end_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_tbt_data_mask_samples_end_swb_s0 <= pos_calc_tbt_data_mask_samples_end_swb; + pos_calc_tbt_data_mask_samples_end_swb_s1 <= pos_calc_tbt_data_mask_samples_end_swb_s0; + pos_calc_tbt_data_mask_samples_end_swb_s2 <= pos_calc_tbt_data_mask_samples_end_swb_s1; + if ((pos_calc_tbt_data_mask_samples_end_swb_s2 = '0') and (pos_calc_tbt_data_mask_samples_end_swb_s1 = '1')) then + pos_calc_tbt_data_mask_samples_end_o <= pos_calc_tbt_data_mask_samples_end_int; + end if; + end if; + end process; + + + -- MONIT1 Synchronizing Trigger Enable + -- synchronizer chain for field : MONIT1 Synchronizing Trigger Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit1_tag_en_o <= '0'; + pos_calc_monit1_tag_en_sync0 <= '0'; + pos_calc_monit1_tag_en_sync1 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit1_tag_en_sync0 <= pos_calc_monit1_tag_en_int; + pos_calc_monit1_tag_en_sync1 <= pos_calc_monit1_tag_en_sync0; + pos_calc_monit1_tag_en_o <= pos_calc_monit1_tag_en_sync1; + end if; + end process; + + + -- MONIT1 Synchronizing Trigger Delay + -- asynchronous std_logic_vector register : MONIT1 Synchronizing Trigger Delay (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit1_tag_dly_swb_s0 <= '0'; + pos_calc_monit1_tag_dly_swb_s1 <= '0'; + pos_calc_monit1_tag_dly_swb_s2 <= '0'; + pos_calc_monit1_tag_dly_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit1_tag_dly_swb_s0 <= pos_calc_monit1_tag_dly_swb; + pos_calc_monit1_tag_dly_swb_s1 <= pos_calc_monit1_tag_dly_swb_s0; + pos_calc_monit1_tag_dly_swb_s2 <= pos_calc_monit1_tag_dly_swb_s1; + if ((pos_calc_monit1_tag_dly_swb_s2 = '0') and (pos_calc_monit1_tag_dly_swb_s1 = '1')) then + pos_calc_monit1_tag_dly_o <= pos_calc_monit1_tag_dly_int; + end if; + end if; + end process; + + + -- MONIT1 Desynchronization Counter Reset + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit1_tag_desync_cnt_rst_o <= '0'; + pos_calc_monit1_tag_desync_cnt_rst_sync0 <= '0'; + pos_calc_monit1_tag_desync_cnt_rst_sync1 <= '0'; + pos_calc_monit1_tag_desync_cnt_rst_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit1_tag_desync_cnt_rst_sync0 <= pos_calc_monit1_tag_desync_cnt_rst_int; + pos_calc_monit1_tag_desync_cnt_rst_sync1 <= pos_calc_monit1_tag_desync_cnt_rst_sync0; + pos_calc_monit1_tag_desync_cnt_rst_sync2 <= pos_calc_monit1_tag_desync_cnt_rst_sync1; + pos_calc_monit1_tag_desync_cnt_rst_o <= pos_calc_monit1_tag_desync_cnt_rst_sync2 and (not pos_calc_monit1_tag_desync_cnt_rst_sync1); + end if; + end process; + + + -- MONIT1 Desynchronization Counter + -- asynchronous std_logic_vector register : MONIT1 Desynchronization Counter (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit1_tag_desync_cnt_lwb_s0 <= '0'; + pos_calc_monit1_tag_desync_cnt_lwb_s1 <= '0'; + pos_calc_monit1_tag_desync_cnt_lwb_s2 <= '0'; + pos_calc_monit1_tag_desync_cnt_int <= "00000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit1_tag_desync_cnt_lwb_s0 <= pos_calc_monit1_tag_desync_cnt_lwb; + pos_calc_monit1_tag_desync_cnt_lwb_s1 <= pos_calc_monit1_tag_desync_cnt_lwb_s0; + pos_calc_monit1_tag_desync_cnt_lwb_s2 <= pos_calc_monit1_tag_desync_cnt_lwb_s1; + if ((pos_calc_monit1_tag_desync_cnt_lwb_s1 = '1') and (pos_calc_monit1_tag_desync_cnt_lwb_s2 = '0')) then + pos_calc_monit1_tag_desync_cnt_int <= pos_calc_monit1_tag_desync_cnt_i; + end if; + end if; + end process; + + + -- MONIT1 Masking Enable + -- synchronizer chain for field : MONIT1 Masking Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit1_data_mask_ctl_en_o <= '0'; + pos_calc_monit1_data_mask_ctl_en_sync0 <= '0'; + pos_calc_monit1_data_mask_ctl_en_sync1 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit1_data_mask_ctl_en_sync0 <= pos_calc_monit1_data_mask_ctl_en_int; + pos_calc_monit1_data_mask_ctl_en_sync1 <= pos_calc_monit1_data_mask_ctl_en_sync0; + pos_calc_monit1_data_mask_ctl_en_o <= pos_calc_monit1_data_mask_ctl_en_sync1; + end if; + end process; + + + -- MONIT1 Beginning Data Masking Samples + -- asynchronous std_logic_vector register : MONIT1 Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit1_data_mask_samples_beg_swb_s0 <= '0'; + pos_calc_monit1_data_mask_samples_beg_swb_s1 <= '0'; + pos_calc_monit1_data_mask_samples_beg_swb_s2 <= '0'; + pos_calc_monit1_data_mask_samples_beg_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit1_data_mask_samples_beg_swb_s0 <= pos_calc_monit1_data_mask_samples_beg_swb; + pos_calc_monit1_data_mask_samples_beg_swb_s1 <= pos_calc_monit1_data_mask_samples_beg_swb_s0; + pos_calc_monit1_data_mask_samples_beg_swb_s2 <= pos_calc_monit1_data_mask_samples_beg_swb_s1; + if ((pos_calc_monit1_data_mask_samples_beg_swb_s2 = '0') and (pos_calc_monit1_data_mask_samples_beg_swb_s1 = '1')) then + pos_calc_monit1_data_mask_samples_beg_o <= pos_calc_monit1_data_mask_samples_beg_int; + end if; + end if; + end process; + + + -- MONIT1 Beginning Data Masking Samples + -- asynchronous std_logic_vector register : MONIT1 Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit1_data_mask_samples_end_swb_s0 <= '0'; + pos_calc_monit1_data_mask_samples_end_swb_s1 <= '0'; + pos_calc_monit1_data_mask_samples_end_swb_s2 <= '0'; + pos_calc_monit1_data_mask_samples_end_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit1_data_mask_samples_end_swb_s0 <= pos_calc_monit1_data_mask_samples_end_swb; + pos_calc_monit1_data_mask_samples_end_swb_s1 <= pos_calc_monit1_data_mask_samples_end_swb_s0; + pos_calc_monit1_data_mask_samples_end_swb_s2 <= pos_calc_monit1_data_mask_samples_end_swb_s1; + if ((pos_calc_monit1_data_mask_samples_end_swb_s2 = '0') and (pos_calc_monit1_data_mask_samples_end_swb_s1 = '1')) then + pos_calc_monit1_data_mask_samples_end_o <= pos_calc_monit1_data_mask_samples_end_int; + end if; + end if; + end process; + + + -- MONIT Synchronizing Trigger Enable + -- synchronizer chain for field : MONIT Synchronizing Trigger Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit_tag_en_o <= '0'; + pos_calc_monit_tag_en_sync0 <= '0'; + pos_calc_monit_tag_en_sync1 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit_tag_en_sync0 <= pos_calc_monit_tag_en_int; + pos_calc_monit_tag_en_sync1 <= pos_calc_monit_tag_en_sync0; + pos_calc_monit_tag_en_o <= pos_calc_monit_tag_en_sync1; + end if; + end process; + + + -- MONIT Synchronizing Trigger Delay + -- asynchronous std_logic_vector register : MONIT Synchronizing Trigger Delay (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit_tag_dly_swb_s0 <= '0'; + pos_calc_monit_tag_dly_swb_s1 <= '0'; + pos_calc_monit_tag_dly_swb_s2 <= '0'; + pos_calc_monit_tag_dly_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit_tag_dly_swb_s0 <= pos_calc_monit_tag_dly_swb; + pos_calc_monit_tag_dly_swb_s1 <= pos_calc_monit_tag_dly_swb_s0; + pos_calc_monit_tag_dly_swb_s2 <= pos_calc_monit_tag_dly_swb_s1; + if ((pos_calc_monit_tag_dly_swb_s2 = '0') and (pos_calc_monit_tag_dly_swb_s1 = '1')) then + pos_calc_monit_tag_dly_o <= pos_calc_monit_tag_dly_int; + end if; + end if; + end process; + + + -- MONIT Desynchronization Counter Reset + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit_tag_desync_cnt_rst_o <= '0'; + pos_calc_monit_tag_desync_cnt_rst_sync0 <= '0'; + pos_calc_monit_tag_desync_cnt_rst_sync1 <= '0'; + pos_calc_monit_tag_desync_cnt_rst_sync2 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit_tag_desync_cnt_rst_sync0 <= pos_calc_monit_tag_desync_cnt_rst_int; + pos_calc_monit_tag_desync_cnt_rst_sync1 <= pos_calc_monit_tag_desync_cnt_rst_sync0; + pos_calc_monit_tag_desync_cnt_rst_sync2 <= pos_calc_monit_tag_desync_cnt_rst_sync1; + pos_calc_monit_tag_desync_cnt_rst_o <= pos_calc_monit_tag_desync_cnt_rst_sync2 and (not pos_calc_monit_tag_desync_cnt_rst_sync1); + end if; + end process; + + + -- MONIT Desynchronization Counter + -- asynchronous std_logic_vector register : MONIT Desynchronization Counter (type RO/WO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit_tag_desync_cnt_lwb_s0 <= '0'; + pos_calc_monit_tag_desync_cnt_lwb_s1 <= '0'; + pos_calc_monit_tag_desync_cnt_lwb_s2 <= '0'; + pos_calc_monit_tag_desync_cnt_int <= "00000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit_tag_desync_cnt_lwb_s0 <= pos_calc_monit_tag_desync_cnt_lwb; + pos_calc_monit_tag_desync_cnt_lwb_s1 <= pos_calc_monit_tag_desync_cnt_lwb_s0; + pos_calc_monit_tag_desync_cnt_lwb_s2 <= pos_calc_monit_tag_desync_cnt_lwb_s1; + if ((pos_calc_monit_tag_desync_cnt_lwb_s1 = '1') and (pos_calc_monit_tag_desync_cnt_lwb_s2 = '0')) then + pos_calc_monit_tag_desync_cnt_int <= pos_calc_monit_tag_desync_cnt_i; + end if; + end if; + end process; + + + -- MONIT Masking Enable + -- synchronizer chain for field : MONIT Masking Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit_data_mask_ctl_en_o <= '0'; + pos_calc_monit_data_mask_ctl_en_sync0 <= '0'; + pos_calc_monit_data_mask_ctl_en_sync1 <= '0'; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit_data_mask_ctl_en_sync0 <= pos_calc_monit_data_mask_ctl_en_int; + pos_calc_monit_data_mask_ctl_en_sync1 <= pos_calc_monit_data_mask_ctl_en_sync0; + pos_calc_monit_data_mask_ctl_en_o <= pos_calc_monit_data_mask_ctl_en_sync1; + end if; + end process; + + + -- MONIT Beginning Data Masking Samples + -- asynchronous std_logic_vector register : MONIT Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit_data_mask_samples_beg_swb_s0 <= '0'; + pos_calc_monit_data_mask_samples_beg_swb_s1 <= '0'; + pos_calc_monit_data_mask_samples_beg_swb_s2 <= '0'; + pos_calc_monit_data_mask_samples_beg_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit_data_mask_samples_beg_swb_s0 <= pos_calc_monit_data_mask_samples_beg_swb; + pos_calc_monit_data_mask_samples_beg_swb_s1 <= pos_calc_monit_data_mask_samples_beg_swb_s0; + pos_calc_monit_data_mask_samples_beg_swb_s2 <= pos_calc_monit_data_mask_samples_beg_swb_s1; + if ((pos_calc_monit_data_mask_samples_beg_swb_s2 = '0') and (pos_calc_monit_data_mask_samples_beg_swb_s1 = '1')) then + pos_calc_monit_data_mask_samples_beg_o <= pos_calc_monit_data_mask_samples_beg_int; + end if; + end if; + end process; + + + -- MONIT Beginning Data Masking Samples + -- asynchronous std_logic_vector register : MONIT Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_monit_data_mask_samples_end_swb_s0 <= '0'; + pos_calc_monit_data_mask_samples_end_swb_s1 <= '0'; + pos_calc_monit_data_mask_samples_end_swb_s2 <= '0'; + pos_calc_monit_data_mask_samples_end_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_monit_data_mask_samples_end_swb_s0 <= pos_calc_monit_data_mask_samples_end_swb; + pos_calc_monit_data_mask_samples_end_swb_s1 <= pos_calc_monit_data_mask_samples_end_swb_s0; + pos_calc_monit_data_mask_samples_end_swb_s2 <= pos_calc_monit_data_mask_samples_end_swb_s1; + if ((pos_calc_monit_data_mask_samples_end_swb_s2 = '0') and (pos_calc_monit_data_mask_samples_end_swb_s1 = '1')) then + pos_calc_monit_data_mask_samples_end_o <= pos_calc_monit_data_mask_samples_end_int; + end if; + end if; + end process; + + + -- BPM X position offset + -- asynchronous std_logic_vector register : BPM X position offset (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_offset_x_swb_s0 <= '0'; + pos_calc_offset_x_swb_s1 <= '0'; + pos_calc_offset_x_swb_s2 <= '0'; + pos_calc_offset_x_o <= "00000000000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_offset_x_swb_s0 <= pos_calc_offset_x_swb; + pos_calc_offset_x_swb_s1 <= pos_calc_offset_x_swb_s0; + pos_calc_offset_x_swb_s2 <= pos_calc_offset_x_swb_s1; + if ((pos_calc_offset_x_swb_s2 = '0') and (pos_calc_offset_x_swb_s1 = '1')) then + pos_calc_offset_x_o <= pos_calc_offset_x_int; + end if; + end if; + end process; + + + -- BPM Y position offset + -- asynchronous std_logic_vector register : BPM Y position offset (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_offset_y_swb_s0 <= '0'; + pos_calc_offset_y_swb_s1 <= '0'; + pos_calc_offset_y_swb_s2 <= '0'; + pos_calc_offset_y_o <= "00000000000000000000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_offset_y_swb_s0 <= pos_calc_offset_y_swb; + pos_calc_offset_y_swb_s1 <= pos_calc_offset_y_swb_s0; + pos_calc_offset_y_swb_s2 <= pos_calc_offset_y_swb_s1; + if ((pos_calc_offset_y_swb_s2 = '0') and (pos_calc_offset_y_swb_s1 = '1')) then + pos_calc_offset_y_o <= pos_calc_offset_y_int; + end if; + end if; + end process; + + + -- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring' data output register 0 + process (clk_sys_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_ampfifo_monit_rdreq_int_d0 <= '0'; + elsif rising_edge(clk_sys_i) then + pos_calc_ampfifo_monit_rdreq_int_d0 <= pos_calc_ampfifo_monit_rdreq_int; + end if; + end process; + + + -- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring' data output register 1 + -- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring' data output register 2 + -- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring' data output register 3 + -- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring' data output register 0 + process (clk_sys_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_posfifo_monit_rdreq_int_d0 <= '0'; + elsif rising_edge(clk_sys_i) then + pos_calc_posfifo_monit_rdreq_int_d0 <= pos_calc_posfifo_monit_rdreq_int; + end if; + end process; + + + -- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring' data output register 1 + -- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring' data output register 2 + -- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring' data output register 3 + -- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring 1' data output register 0 + process (clk_sys_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_ampfifo_monit1_rdreq_int_d0 <= '0'; + elsif rising_edge(clk_sys_i) then + pos_calc_ampfifo_monit1_rdreq_int_d0 <= pos_calc_ampfifo_monit1_rdreq_int; + end if; + end process; + + + -- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring 1' data output register 1 + -- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring 1' data output register 2 + -- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring 1' data output register 3 + -- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring 1' data output register 0 + process (clk_sys_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_posfifo_monit1_rdreq_int_d0 <= '0'; + elsif rising_edge(clk_sys_i) then + pos_calc_posfifo_monit1_rdreq_int_d0 <= pos_calc_posfifo_monit1_rdreq_int; + end if; + end process; + + + -- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring 1' data output register 1 + -- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring 1' data output register 2 + -- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring 1' data output register 3 + rwaddr_reg <= wb_adr_i; + wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); + -- ACK signal generation. Just pass the LSB of ACK counter. + wb_ack_o <= ack_sreg(0); +end syn; diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs_pkg.vhd b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs_pkg.vhd new file mode 100644 index 00000000..e7e895b0 --- /dev/null +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs_pkg.vhd @@ -0,0 +1,183 @@ +package pos_calc_Consts is + constant POS_CALC_SIZE : Natural := 276; + constant ADDR_POS_CALC_DS_TBT_THRES : Natural := 16#0#; + constant POS_CALC_DS_TBT_THRES_VAL_OFFSET : Natural := 0; + constant POS_CALC_DS_TBT_THRES_RESERVED_OFFSET : Natural := 26; + constant ADDR_POS_CALC_DS_FOFB_THRES : Natural := 16#4#; + constant POS_CALC_DS_FOFB_THRES_VAL_OFFSET : Natural := 0; + constant POS_CALC_DS_FOFB_THRES_RESERVED_OFFSET : Natural := 26; + constant ADDR_POS_CALC_DS_MONIT_THRES : Natural := 16#8#; + constant POS_CALC_DS_MONIT_THRES_VAL_OFFSET : Natural := 0; + constant POS_CALC_DS_MONIT_THRES_RESERVED_OFFSET : Natural := 26; + constant ADDR_POS_CALC_KX : Natural := 16#c#; + constant POS_CALC_KX_VAL_OFFSET : Natural := 0; + constant POS_CALC_KX_RESERVED_OFFSET : Natural := 25; + constant ADDR_POS_CALC_KY : Natural := 16#10#; + constant POS_CALC_KY_VAL_OFFSET : Natural := 0; + constant POS_CALC_KY_RESERVED_OFFSET : Natural := 25; + constant ADDR_POS_CALC_KSUM : Natural := 16#14#; + constant POS_CALC_KSUM_VAL_OFFSET : Natural := 0; + constant POS_CALC_KSUM_RESERVED_OFFSET : Natural := 25; + constant ADDR_POS_CALC_DSP_CTNR_TBT : Natural := 16#18#; + constant POS_CALC_DSP_CTNR_TBT_CH01_OFFSET : Natural := 0; + constant POS_CALC_DSP_CTNR_TBT_CH23_OFFSET : Natural := 16; + constant ADDR_POS_CALC_DSP_CTNR_FOFB : Natural := 16#1c#; + constant POS_CALC_DSP_CTNR_FOFB_CH01_OFFSET : Natural := 0; + constant POS_CALC_DSP_CTNR_FOFB_CH23_OFFSET : Natural := 16; + constant ADDR_POS_CALC_DSP_CTNR1_MONIT : Natural := 16#20#; + constant POS_CALC_DSP_CTNR1_MONIT_CIC_OFFSET : Natural := 0; + constant POS_CALC_DSP_CTNR1_MONIT_CFIR_OFFSET : Natural := 16; + constant ADDR_POS_CALC_DSP_CTNR2_MONIT : Natural := 16#24#; + constant POS_CALC_DSP_CTNR2_MONIT_PFIR_OFFSET : Natural := 0; + constant POS_CALC_DSP_CTNR2_MONIT_FIR_01_OFFSET : Natural := 16; + constant ADDR_POS_CALC_DSP_ERR_CLR : Natural := 16#28#; + constant POS_CALC_DSP_ERR_CLR_TBT_OFFSET : Natural := 0; + constant POS_CALC_DSP_ERR_CLR_FOFB_OFFSET : Natural := 1; + constant POS_CALC_DSP_ERR_CLR_MONIT_PART1_OFFSET : Natural := 2; + constant POS_CALC_DSP_ERR_CLR_MONIT_PART2_OFFSET : Natural := 3; + constant ADDR_POS_CALC_DDS_CFG : Natural := 16#2c#; + constant POS_CALC_DDS_CFG_VALID_CH0_OFFSET : Natural := 0; + constant POS_CALC_DDS_CFG_TEST_DATA_OFFSET : Natural := 1; + constant POS_CALC_DDS_CFG_RESERVED_CH0_OFFSET : Natural := 2; + constant POS_CALC_DDS_CFG_VALID_CH1_OFFSET : Natural := 8; + constant POS_CALC_DDS_CFG_RESERVED_CH1_OFFSET : Natural := 9; + constant POS_CALC_DDS_CFG_VALID_CH2_OFFSET : Natural := 16; + constant POS_CALC_DDS_CFG_RESERVED_CH2_OFFSET : Natural := 17; + constant POS_CALC_DDS_CFG_VALID_CH3_OFFSET : Natural := 24; + constant POS_CALC_DDS_CFG_RESERVED_CH3_OFFSET : Natural := 25; + constant ADDR_POS_CALC_DDS_PINC_CH0 : Natural := 16#30#; + constant POS_CALC_DDS_PINC_CH0_VAL_OFFSET : Natural := 0; + constant POS_CALC_DDS_PINC_CH0_RESERVED_OFFSET : Natural := 30; + constant ADDR_POS_CALC_DDS_PINC_CH1 : Natural := 16#34#; + constant POS_CALC_DDS_PINC_CH1_VAL_OFFSET : Natural := 0; + constant POS_CALC_DDS_PINC_CH1_RESERVED_OFFSET : Natural := 30; + constant ADDR_POS_CALC_DDS_PINC_CH2 : Natural := 16#38#; + constant POS_CALC_DDS_PINC_CH2_VAL_OFFSET : Natural := 0; + constant POS_CALC_DDS_PINC_CH2_RESERVED_OFFSET : Natural := 30; + constant ADDR_POS_CALC_DDS_PINC_CH3 : Natural := 16#3c#; + constant POS_CALC_DDS_PINC_CH3_VAL_OFFSET : Natural := 0; + constant POS_CALC_DDS_PINC_CH3_RESERVED_OFFSET : Natural := 30; + constant ADDR_POS_CALC_DDS_POFF_CH0 : Natural := 16#40#; + constant POS_CALC_DDS_POFF_CH0_VAL_OFFSET : Natural := 0; + constant POS_CALC_DDS_POFF_CH0_RESERVED_OFFSET : Natural := 30; + constant ADDR_POS_CALC_DDS_POFF_CH1 : Natural := 16#44#; + constant POS_CALC_DDS_POFF_CH1_VAL_OFFSET : Natural := 0; + constant POS_CALC_DDS_POFF_CH1_RESERVED_OFFSET : Natural := 30; + constant ADDR_POS_CALC_DDS_POFF_CH2 : Natural := 16#48#; + constant POS_CALC_DDS_POFF_CH2_VAL_OFFSET : Natural := 0; + constant POS_CALC_DDS_POFF_CH2_RESERVED_OFFSET : Natural := 30; + constant ADDR_POS_CALC_DDS_POFF_CH3 : Natural := 16#4c#; + constant POS_CALC_DDS_POFF_CH3_VAL_OFFSET : Natural := 0; + constant POS_CALC_DDS_POFF_CH3_RESERVED_OFFSET : Natural := 30; + constant ADDR_POS_CALC_DSP_MONIT_AMP_CH0 : Natural := 16#50#; + constant ADDR_POS_CALC_DSP_MONIT_AMP_CH1 : Natural := 16#54#; + constant ADDR_POS_CALC_DSP_MONIT_AMP_CH2 : Natural := 16#58#; + constant ADDR_POS_CALC_DSP_MONIT_AMP_CH3 : Natural := 16#5c#; + constant ADDR_POS_CALC_DSP_MONIT_POS_X : Natural := 16#60#; + constant ADDR_POS_CALC_DSP_MONIT_POS_Y : Natural := 16#64#; + constant ADDR_POS_CALC_DSP_MONIT_POS_Q : Natural := 16#68#; + constant ADDR_POS_CALC_DSP_MONIT_POS_SUM : Natural := 16#6c#; + constant ADDR_POS_CALC_DSP_MONIT_UPDT : Natural := 16#70#; + constant ADDR_POS_CALC_DSP_MONIT1_AMP_CH0 : Natural := 16#74#; + constant ADDR_POS_CALC_DSP_MONIT1_AMP_CH1 : Natural := 16#78#; + constant ADDR_POS_CALC_DSP_MONIT1_AMP_CH2 : Natural := 16#7c#; + constant ADDR_POS_CALC_DSP_MONIT1_AMP_CH3 : Natural := 16#80#; + constant ADDR_POS_CALC_DSP_MONIT1_POS_X : Natural := 16#84#; + constant ADDR_POS_CALC_DSP_MONIT1_POS_Y : Natural := 16#88#; + constant ADDR_POS_CALC_DSP_MONIT1_POS_Q : Natural := 16#8c#; + constant ADDR_POS_CALC_DSP_MONIT1_POS_SUM : Natural := 16#90#; + constant ADDR_POS_CALC_DSP_MONIT1_UPDT : Natural := 16#94#; + constant ADDR_POS_CALC_AMPFIFO_MONIT : Natural := 16#98#; + constant POS_CALC_AMPFIFO_MONIT_SIZE : Natural := 20; + constant ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0 : Natural := 16#98#; + constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0_AMP_CH0_OFFSET : Natural := 0; + constant ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1 : Natural := 16#9c#; + constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1_AMP_CH1_OFFSET : Natural := 0; + constant ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2 : Natural := 16#a0#; + constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2_AMP_CH2_OFFSET : Natural := 0; + constant ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3 : Natural := 16#a4#; + constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3_AMP_CH3_OFFSET : Natural := 0; + constant ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR : Natural := 16#a8#; + constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_FULL_OFFSET : Natural := 16; + constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_EMPTY_OFFSET : Natural := 17; + constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_COUNT_OFFSET : Natural := 0; + constant ADDR_POS_CALC_POSFIFO_MONIT : Natural := 16#ac#; + constant POS_CALC_POSFIFO_MONIT_SIZE : Natural := 20; + constant ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0 : Natural := 16#ac#; + constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0_POS_X_OFFSET : Natural := 0; + constant ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1 : Natural := 16#b0#; + constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1_POS_Y_OFFSET : Natural := 0; + constant ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2 : Natural := 16#b4#; + constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2_POS_Q_OFFSET : Natural := 0; + constant ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3 : Natural := 16#b8#; + constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3_POS_SUM_OFFSET : Natural := 0; + constant ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR : Natural := 16#bc#; + constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_FULL_OFFSET : Natural := 16; + constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_EMPTY_OFFSET : Natural := 17; + constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_COUNT_OFFSET : Natural := 0; + constant ADDR_POS_CALC_AMPFIFO_MONIT1 : Natural := 16#c0#; + constant POS_CALC_AMPFIFO_MONIT1_SIZE : Natural := 20; + constant ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0 : Natural := 16#c0#; + constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0_AMP_CH0_OFFSET : Natural := 0; + constant ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1 : Natural := 16#c4#; + constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1_AMP_CH1_OFFSET : Natural := 0; + constant ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2 : Natural := 16#c8#; + constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2_AMP_CH2_OFFSET : Natural := 0; + constant ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3 : Natural := 16#cc#; + constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3_AMP_CH3_OFFSET : Natural := 0; + constant ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR : Natural := 16#d0#; + constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_FULL_OFFSET : Natural := 16; + constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_EMPTY_OFFSET : Natural := 17; + constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_COUNT_OFFSET : Natural := 0; + constant ADDR_POS_CALC_POSFIFO_MONIT1 : Natural := 16#d4#; + constant POS_CALC_POSFIFO_MONIT1_SIZE : Natural := 20; + constant ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0 : Natural := 16#d4#; + constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0_POS_X_OFFSET : Natural := 0; + constant ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1 : Natural := 16#d8#; + constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1_POS_Y_OFFSET : Natural := 0; + constant ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2 : Natural := 16#dc#; + constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2_POS_Q_OFFSET : Natural := 0; + constant ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3 : Natural := 16#e0#; + constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3_POS_SUM_OFFSET : Natural := 0; + constant ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR : Natural := 16#e4#; + constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_FULL_OFFSET : Natural := 16; + constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_EMPTY_OFFSET : Natural := 17; + constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_COUNT_OFFSET : Natural := 0; + constant ADDR_POS_CALC_SW_TAG : Natural := 16#e8#; + constant POS_CALC_SW_TAG_EN_OFFSET : Natural := 0; + constant POS_CALC_SW_TAG_DESYNC_CNT_RST_OFFSET : Natural := 8; + constant POS_CALC_SW_TAG_DESYNC_CNT_OFFSET : Natural := 9; + constant ADDR_POS_CALC_SW_DATA_MASK : Natural := 16#ec#; + constant POS_CALC_SW_DATA_MASK_EN_OFFSET : Natural := 0; + constant POS_CALC_SW_DATA_MASK_SAMPLES_OFFSET : Natural := 1; + constant ADDR_POS_CALC_TBT_TAG : Natural := 16#f0#; + constant POS_CALC_TBT_TAG_EN_OFFSET : Natural := 0; + constant POS_CALC_TBT_TAG_DLY_OFFSET : Natural := 1; + constant POS_CALC_TBT_TAG_DESYNC_CNT_RST_OFFSET : Natural := 17; + constant POS_CALC_TBT_TAG_DESYNC_CNT_OFFSET : Natural := 18; + constant ADDR_POS_CALC_TBT_DATA_MASK_CTL : Natural := 16#f4#; + constant POS_CALC_TBT_DATA_MASK_CTL_EN_OFFSET : Natural := 0; + constant ADDR_POS_CALC_TBT_DATA_MASK_SAMPLES : Natural := 16#f8#; + constant POS_CALC_TBT_DATA_MASK_SAMPLES_BEG_OFFSET : Natural := 0; + constant POS_CALC_TBT_DATA_MASK_SAMPLES_END_OFFSET : Natural := 16; + constant ADDR_POS_CALC_MONIT1_TAG : Natural := 16#fc#; + constant POS_CALC_MONIT1_TAG_EN_OFFSET : Natural := 0; + constant POS_CALC_MONIT1_TAG_DLY_OFFSET : Natural := 1; + constant POS_CALC_MONIT1_TAG_DESYNC_CNT_RST_OFFSET : Natural := 17; + constant POS_CALC_MONIT1_TAG_DESYNC_CNT_OFFSET : Natural := 18; + constant ADDR_POS_CALC_MONIT1_DATA_MASK_CTL : Natural := 16#100#; + constant POS_CALC_MONIT1_DATA_MASK_CTL_EN_OFFSET : Natural := 0; + constant ADDR_POS_CALC_MONIT1_DATA_MASK_SAMPLES : Natural := 16#104#; + constant POS_CALC_MONIT1_DATA_MASK_SAMPLES_BEG_OFFSET : Natural := 0; + constant POS_CALC_MONIT1_DATA_MASK_SAMPLES_END_OFFSET : Natural := 16; + constant ADDR_POS_CALC_MONIT_TAG : Natural := 16#108#; + constant POS_CALC_MONIT_TAG_EN_OFFSET : Natural := 0; + constant POS_CALC_MONIT_TAG_DLY_OFFSET : Natural := 1; + constant POS_CALC_MONIT_TAG_DESYNC_CNT_RST_OFFSET : Natural := 17; + constant POS_CALC_MONIT_TAG_DESYNC_CNT_OFFSET : Natural := 18; + constant ADDR_POS_CALC_MONIT_DATA_MASK_CTL : Natural := 16#10c#; + constant POS_CALC_MONIT_DATA_MASK_CTL_EN_OFFSET : Natural := 0; + constant ADDR_POS_CALC_MONIT_DATA_MASK_SAMPLES : Natural := 16#110#; + constant POS_CALC_MONIT_DATA_MASK_SAMPLES_BEG_OFFSET : Natural := 0; + constant POS_CALC_MONIT_DATA_MASK_SAMPLES_END_OFFSET : Natural := 16; +end package pos_calc_Consts; diff --git a/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd b/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd old mode 100755 new mode 100644 diff --git a/hdl/modules/wb_position_calc/position_calc_core_pkg.vhd b/hdl/modules/wb_position_calc/position_calc_core_pkg.vhd old mode 100755 new mode 100644 diff --git a/hdl/modules/wb_position_calc/wb_position_calc_core.vhd b/hdl/modules/wb_position_calc/wb_position_calc_core.vhd old mode 100755 new mode 100644 index b11fd186..23185d13 --- a/hdl/modules/wb_position_calc/wb_position_calc_core.vhd +++ b/hdl/modules/wb_position_calc/wb_position_calc_core.vhd @@ -31,10 +31,6 @@ use work.bpm_cores_pkg.all; use work.position_calc_core_pkg.all; -- Counter Generator Definitions use work.counters_gen_pkg.all; --- WB registers -use work.pos_calc_wbgen2_pkg.all; --- Common Cores -use work.ifc_common_pkg.all; entity wb_position_calc_core is generic @@ -91,7 +87,10 @@ generic g_fofb_cordic_ratio : positive := 4; -- width of K constants - g_k_width : natural := 16; + g_k_width : natural := 25; + + -- width of offset constants + g_offset_width : natural := 32; --width for IQ output g_IQ_width : natural := 32; @@ -340,7 +339,9 @@ architecture rtl of wb_position_calc_core is constant c_monit1_ratio_log2 : natural := f_log2_size(c_monit1_ratio+1); constant c_monit2_ratio_log2 : natural := f_log2_size(c_monit2_ratio+1); - constant c_k_width : natural := 24; + -- This must not exceed the width determined at the register file + constant c_k_width : natural := g_k_width; + constant c_offset_width : natural := g_offset_width; constant c_cnt_width_raw : natural := g_adc_ratio; constant c_cnt_width_mix : natural := g_IQ_width; @@ -405,8 +406,135 @@ architecture rtl of wb_position_calc_core is signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0); -- Register interface signals - signal regs_out : t_pos_calc_out_registers; - signal regs_in : t_pos_calc_in_registers; + signal regs_ds_tbt_thres_val_o : std_logic_vector(25 downto 0); + signal regs_ds_tbt_thres_reserved_i : std_logic_vector(5 downto 0) := (others => '0'); + signal regs_ds_fofb_thres_val_o : std_logic_vector(25 downto 0); + signal regs_ds_fofb_thres_reserved_i : std_logic_vector(5 downto 0) := (others => '0'); + signal regs_ds_monit_thres_val_o : std_logic_vector(25 downto 0); + signal regs_ds_monit_thres_reserved_i : std_logic_vector(5 downto 0) := (others => '0'); + signal regs_kx_val_o : std_logic_vector(24 downto 0); + signal regs_kx_reserved_i : std_logic_vector(6 downto 0) := (others => '0'); + signal regs_ky_val_o : std_logic_vector(24 downto 0); + signal regs_ky_reserved_i : std_logic_vector(6 downto 0) := (others => '0'); + signal regs_ksum_val_o : std_logic_vector(24 downto 0); + signal regs_ksum_reserved_i : std_logic_vector(6 downto 0) := (others => '0'); + signal regs_dsp_ctnr_tbt_ch01_i : std_logic_vector(15 downto 0) := (others => '0'); + signal regs_dsp_ctnr_tbt_ch23_i : std_logic_vector(15 downto 0) := (others => '0'); + signal regs_dsp_ctnr_fofb_ch01_i : std_logic_vector(15 downto 0) := (others => '0'); + signal regs_dsp_ctnr_fofb_ch23_i : std_logic_vector(15 downto 0) := (others => '0'); + signal regs_dsp_ctnr1_monit_cic_i : std_logic_vector(15 downto 0) := (others => '0'); + signal regs_dsp_ctnr1_monit_cfir_i : std_logic_vector(15 downto 0) := (others => '0'); + signal regs_dsp_ctnr2_monit_pfir_i : std_logic_vector(15 downto 0) := (others => '0'); + signal regs_dsp_ctnr2_monit_fir_01_i : std_logic_vector(15 downto 0) := (others => '0'); + signal regs_dsp_err_clr_tbt_o : std_logic; + signal regs_dsp_err_clr_fofb_o : std_logic; + signal regs_dsp_err_clr_monit_part1_o : std_logic; + signal regs_dsp_err_clr_monit_part2_o : std_logic; + signal regs_dds_cfg_valid_ch0_o : std_logic; + signal regs_dds_cfg_test_data_o : std_logic; + signal regs_dds_cfg_reserved_ch0_i : std_logic_vector(5 downto 0) := (others => '0'); + signal regs_dds_cfg_valid_ch1_o : std_logic; + signal regs_dds_cfg_reserved_ch1_i : std_logic_vector(6 downto 0) := (others => '0'); + signal regs_dds_cfg_valid_ch2_o : std_logic; + signal regs_dds_cfg_reserved_ch2_i : std_logic_vector(6 downto 0) := (others => '0'); + signal regs_dds_cfg_valid_ch3_o : std_logic; + signal regs_dds_cfg_reserved_ch3_i : std_logic_vector(6 downto 0) := (others => '0'); + signal regs_dds_pinc_ch0_val_o : std_logic_vector(29 downto 0); + signal regs_dds_pinc_ch0_reserved_i : std_logic_vector(1 downto 0) := (others => '0'); + signal regs_dds_pinc_ch1_val_o : std_logic_vector(29 downto 0); + signal regs_dds_pinc_ch1_reserved_i : std_logic_vector(1 downto 0) := (others => '0'); + signal regs_dds_pinc_ch2_val_o : std_logic_vector(29 downto 0); + signal regs_dds_pinc_ch2_reserved_i : std_logic_vector(1 downto 0) := (others => '0'); + signal regs_dds_pinc_ch3_val_o : std_logic_vector(29 downto 0); + signal regs_dds_pinc_ch3_reserved_i : std_logic_vector(1 downto 0) := (others => '0'); + signal regs_dds_poff_ch0_val_o : std_logic_vector(29 downto 0); + signal regs_dds_poff_ch0_reserved_i : std_logic_vector(1 downto 0) := (others => '0'); + signal regs_dds_poff_ch1_val_o : std_logic_vector(29 downto 0); + signal regs_dds_poff_ch1_reserved_i : std_logic_vector(1 downto 0) := (others => '0'); + signal regs_dds_poff_ch2_val_o : std_logic_vector(29 downto 0); + signal regs_dds_poff_ch2_reserved_i : std_logic_vector(1 downto 0) := (others => '0'); + signal regs_dds_poff_ch3_val_o : std_logic_vector(29 downto 0); + signal regs_dds_poff_ch3_reserved_i : std_logic_vector(1 downto 0) := (others => '0'); + signal regs_dsp_monit_amp_ch0_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit_amp_ch1_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit_amp_ch2_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit_amp_ch3_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit_pos_x_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit_pos_y_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit_pos_q_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit_pos_sum_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit_updt_o : std_logic_vector(31 downto 0); + signal regs_dsp_monit_updt_wr_o : std_logic; + signal regs_dsp_monit1_amp_ch0_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit1_amp_ch1_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit1_amp_ch2_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit1_amp_ch3_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit1_pos_x_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit1_pos_y_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit1_pos_q_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit1_pos_sum_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_dsp_monit1_updt_o : std_logic_vector(31 downto 0); + signal regs_dsp_monit1_updt_wr_o : std_logic; + signal regs_ampfifo_monit_wr_req_i : std_logic := '0'; + signal regs_ampfifo_monit_wr_full_o : std_logic; + signal regs_ampfifo_monit_wr_empty_o : std_logic; + signal regs_ampfifo_monit_wr_usedw_o : std_logic_vector(3 downto 0); + signal regs_ampfifo_monit_amp_ch0_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_ampfifo_monit_amp_ch1_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_ampfifo_monit_amp_ch2_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_ampfifo_monit_amp_ch3_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_posfifo_monit_wr_req_i : std_logic := '0'; + signal regs_posfifo_monit_wr_full_o : std_logic; + signal regs_posfifo_monit_wr_empty_o : std_logic; + signal regs_posfifo_monit_wr_usedw_o : std_logic_vector(3 downto 0); + signal regs_posfifo_monit_pos_x_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_posfifo_monit_pos_y_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_posfifo_monit_pos_q_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_posfifo_monit_pos_sum_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_ampfifo_monit1_wr_req_i : std_logic := '0'; + signal regs_ampfifo_monit1_wr_full_o : std_logic; + signal regs_ampfifo_monit1_wr_empty_o : std_logic; + signal regs_ampfifo_monit1_wr_usedw_o : std_logic_vector(3 downto 0); + signal regs_ampfifo_monit1_amp_ch0_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_ampfifo_monit1_amp_ch1_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_ampfifo_monit1_amp_ch2_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_ampfifo_monit1_amp_ch3_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_posfifo_monit1_wr_req_i : std_logic := '0'; + signal regs_posfifo_monit1_wr_full_o : std_logic; + signal regs_posfifo_monit1_wr_empty_o : std_logic; + signal regs_posfifo_monit1_wr_usedw_o : std_logic_vector(3 downto 0); + signal regs_posfifo_monit1_pos_x_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_posfifo_monit1_pos_y_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_posfifo_monit1_pos_q_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_posfifo_monit1_pos_sum_i : std_logic_vector(31 downto 0) := (others => '0'); + signal regs_sw_tag_en_o : std_logic; + signal regs_sw_tag_desync_cnt_rst_o : std_logic; + signal regs_sw_tag_desync_cnt_i : std_logic_vector(13 downto 0) := (others => '0'); + signal regs_sw_data_mask_en_o : std_logic; + signal regs_sw_data_mask_samples_o : std_logic_vector(15 downto 0); + signal regs_tbt_tag_en_o : std_logic; + signal regs_tbt_tag_dly_o : std_logic_vector(15 downto 0); + signal regs_tbt_tag_desync_cnt_rst_o : std_logic; + signal regs_tbt_tag_desync_cnt_i : std_logic_vector(13 downto 0) := (others => '0'); + signal regs_tbt_data_mask_ctl_en_o : std_logic; + signal regs_tbt_data_mask_samples_beg_o : std_logic_vector(15 downto 0); + signal regs_tbt_data_mask_samples_end_o : std_logic_vector(15 downto 0); + signal regs_monit1_tag_en_o : std_logic; + signal regs_monit1_tag_dly_o : std_logic_vector(15 downto 0); + signal regs_monit1_tag_desync_cnt_rst_o : std_logic; + signal regs_monit1_tag_desync_cnt_i : std_logic_vector(13 downto 0) := (others => '0'); + signal regs_monit1_data_mask_ctl_en_o : std_logic; + signal regs_monit1_data_mask_samples_beg_o : std_logic_vector(15 downto 0); + signal regs_monit1_data_mask_samples_end_o : std_logic_vector(15 downto 0); + signal regs_monit_tag_en_o : std_logic; + signal regs_monit_tag_dly_o : std_logic_vector(15 downto 0); + signal regs_monit_tag_desync_cnt_rst_o : std_logic; + signal regs_monit_tag_desync_cnt_i : std_logic_vector(13 downto 0) := (others => '0'); + signal regs_monit_data_mask_ctl_en_o : std_logic; + signal regs_monit_data_mask_samples_beg_o : std_logic_vector(15 downto 0); + signal regs_monit_data_mask_samples_end_o : std_logic_vector(15 downto 0); + signal regs_pos_calc_offset_x_o : std_logic_vector(31 downto 0); + signal regs_pos_calc_offset_y_o : std_logic_vector(31 downto 0); ----------------------------- -- Wishbone crossbar signals @@ -718,22 +846,148 @@ architecture rtl of wb_position_calc_core is component wb_pos_calc_regs is port ( - rst_n_i : in std_logic; - clk_sys_i : in std_logic; - wb_adr_i : in std_logic_vector(6 downto 0); - wb_dat_i : in std_logic_vector(31 downto 0); - wb_dat_o : out std_logic_vector(31 downto 0); - wb_cyc_i : in std_logic; - wb_sel_i : in std_logic_vector(3 downto 0); - wb_stb_i : in std_logic; - wb_we_i : in std_logic; - wb_ack_o : out std_logic; - wb_err_o : out std_logic; - wb_rty_o : out std_logic; - wb_stall_o : out std_logic; - fs_clk2x_i : in std_logic; - regs_i : in t_pos_calc_in_registers; - regs_o : out t_pos_calc_out_registers); + rst_n_i : in std_logic; + clk_sys_i : in std_logic; + wb_adr_i : in std_logic_vector(6 downto 0); + wb_dat_i : in std_logic_vector(31 downto 0); + wb_dat_o : out std_logic_vector(31 downto 0); + wb_cyc_i : in std_logic; + wb_sel_i : in std_logic_vector(3 downto 0); + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_ack_o : out std_logic; + wb_stall_o : out std_logic; + fs_clk2x_i : in std_logic; + pos_calc_ds_tbt_thres_val_o : out std_logic_vector(25 downto 0); + pos_calc_ds_tbt_thres_reserved_i : in std_logic_vector(5 downto 0); + pos_calc_ds_fofb_thres_val_o : out std_logic_vector(25 downto 0); + pos_calc_ds_fofb_thres_reserved_i : in std_logic_vector(5 downto 0); + pos_calc_ds_monit_thres_val_o : out std_logic_vector(25 downto 0); + pos_calc_ds_monit_thres_reserved_i : in std_logic_vector(5 downto 0); + pos_calc_kx_val_o : out std_logic_vector(24 downto 0); + pos_calc_kx_reserved_i : in std_logic_vector(6 downto 0); + pos_calc_ky_val_o : out std_logic_vector(24 downto 0); + pos_calc_ky_reserved_i : in std_logic_vector(6 downto 0); + pos_calc_ksum_val_o : out std_logic_vector(24 downto 0); + pos_calc_ksum_reserved_i : in std_logic_vector(6 downto 0); + pos_calc_dsp_ctnr_tbt_ch01_i : in std_logic_vector(15 downto 0); + pos_calc_dsp_ctnr_tbt_ch23_i : in std_logic_vector(15 downto 0); + pos_calc_dsp_ctnr_fofb_ch01_i : in std_logic_vector(15 downto 0); + pos_calc_dsp_ctnr_fofb_ch23_i : in std_logic_vector(15 downto 0); + pos_calc_dsp_ctnr1_monit_cic_i : in std_logic_vector(15 downto 0); + pos_calc_dsp_ctnr1_monit_cfir_i : in std_logic_vector(15 downto 0); + pos_calc_dsp_ctnr2_monit_pfir_i : in std_logic_vector(15 downto 0); + pos_calc_dsp_ctnr2_monit_fir_01_i : in std_logic_vector(15 downto 0); + pos_calc_dsp_err_clr_tbt_o : out std_logic; + pos_calc_dsp_err_clr_fofb_o : out std_logic; + pos_calc_dsp_err_clr_monit_part1_o : out std_logic; + pos_calc_dsp_err_clr_monit_part2_o : out std_logic; + pos_calc_dds_cfg_valid_ch0_o : out std_logic; + pos_calc_dds_cfg_test_data_o : out std_logic; + pos_calc_dds_cfg_reserved_ch0_i : in std_logic_vector(5 downto 0); + pos_calc_dds_cfg_valid_ch1_o : out std_logic; + pos_calc_dds_cfg_reserved_ch1_i : in std_logic_vector(6 downto 0); + pos_calc_dds_cfg_valid_ch2_o : out std_logic; + pos_calc_dds_cfg_reserved_ch2_i : in std_logic_vector(6 downto 0); + pos_calc_dds_cfg_valid_ch3_o : out std_logic; + pos_calc_dds_cfg_reserved_ch3_i : in std_logic_vector(6 downto 0); + pos_calc_dds_pinc_ch0_val_o : out std_logic_vector(29 downto 0); + pos_calc_dds_pinc_ch0_reserved_i : in std_logic_vector(1 downto 0); + pos_calc_dds_pinc_ch1_val_o : out std_logic_vector(29 downto 0); + pos_calc_dds_pinc_ch1_reserved_i : in std_logic_vector(1 downto 0); + pos_calc_dds_pinc_ch2_val_o : out std_logic_vector(29 downto 0); + pos_calc_dds_pinc_ch2_reserved_i : in std_logic_vector(1 downto 0); + pos_calc_dds_pinc_ch3_val_o : out std_logic_vector(29 downto 0); + pos_calc_dds_pinc_ch3_reserved_i : in std_logic_vector(1 downto 0); + pos_calc_dds_poff_ch0_val_o : out std_logic_vector(29 downto 0); + pos_calc_dds_poff_ch0_reserved_i : in std_logic_vector(1 downto 0); + pos_calc_dds_poff_ch1_val_o : out std_logic_vector(29 downto 0); + pos_calc_dds_poff_ch1_reserved_i : in std_logic_vector(1 downto 0); + pos_calc_dds_poff_ch2_val_o : out std_logic_vector(29 downto 0); + pos_calc_dds_poff_ch2_reserved_i : in std_logic_vector(1 downto 0); + pos_calc_dds_poff_ch3_val_o : out std_logic_vector(29 downto 0); + pos_calc_dds_poff_ch3_reserved_i : in std_logic_vector(1 downto 0); + pos_calc_dsp_monit_amp_ch0_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit_amp_ch1_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit_amp_ch2_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit_amp_ch3_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit_pos_x_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit_pos_y_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit_pos_q_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit_pos_sum_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit_updt_o : out std_logic_vector(31 downto 0); + pos_calc_dsp_monit_updt_wr_o : out std_logic; + pos_calc_dsp_monit1_amp_ch0_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit1_amp_ch1_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit1_amp_ch2_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit1_amp_ch3_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit1_pos_x_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit1_pos_y_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit1_pos_q_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit1_pos_sum_i : in std_logic_vector(31 downto 0); + pos_calc_dsp_monit1_updt_o : out std_logic_vector(31 downto 0); + pos_calc_dsp_monit1_updt_wr_o : out std_logic; + pos_calc_ampfifo_monit_wr_req_i : in std_logic; + pos_calc_ampfifo_monit_wr_full_o : out std_logic; + pos_calc_ampfifo_monit_wr_empty_o : out std_logic; + pos_calc_ampfifo_monit_wr_usedw_o : out std_logic_vector(3 downto 0); + pos_calc_ampfifo_monit_amp_ch0_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit_amp_ch1_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit_amp_ch2_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit_amp_ch3_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit_wr_req_i : in std_logic; + pos_calc_posfifo_monit_wr_full_o : out std_logic; + pos_calc_posfifo_monit_wr_empty_o : out std_logic; + pos_calc_posfifo_monit_wr_usedw_o : out std_logic_vector(3 downto 0); + pos_calc_posfifo_monit_pos_x_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit_pos_y_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit_pos_q_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit_pos_sum_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit1_wr_req_i : in std_logic; + pos_calc_ampfifo_monit1_wr_full_o : out std_logic; + pos_calc_ampfifo_monit1_wr_empty_o : out std_logic; + pos_calc_ampfifo_monit1_wr_usedw_o : out std_logic_vector(3 downto 0); + pos_calc_ampfifo_monit1_amp_ch0_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit1_amp_ch1_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit1_amp_ch2_i : in std_logic_vector(31 downto 0); + pos_calc_ampfifo_monit1_amp_ch3_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit1_wr_req_i : in std_logic; + pos_calc_posfifo_monit1_wr_full_o : out std_logic; + pos_calc_posfifo_monit1_wr_empty_o : out std_logic; + pos_calc_posfifo_monit1_wr_usedw_o : out std_logic_vector(3 downto 0); + pos_calc_posfifo_monit1_pos_x_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit1_pos_y_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit1_pos_q_i : in std_logic_vector(31 downto 0); + pos_calc_posfifo_monit1_pos_sum_i : in std_logic_vector(31 downto 0); + pos_calc_sw_tag_en_o : out std_logic; + pos_calc_sw_tag_desync_cnt_rst_o : out std_logic; + pos_calc_sw_tag_desync_cnt_i : in std_logic_vector(13 downto 0); + pos_calc_sw_data_mask_en_o : out std_logic; + pos_calc_sw_data_mask_samples_o : out std_logic_vector(15 downto 0); + pos_calc_tbt_tag_en_o : out std_logic; + pos_calc_tbt_tag_dly_o : out std_logic_vector(15 downto 0); + pos_calc_tbt_tag_desync_cnt_rst_o : out std_logic; + pos_calc_tbt_tag_desync_cnt_i : in std_logic_vector(13 downto 0); + pos_calc_tbt_data_mask_ctl_en_o : out std_logic; + pos_calc_tbt_data_mask_samples_beg_o : out std_logic_vector(15 downto 0); + pos_calc_tbt_data_mask_samples_end_o : out std_logic_vector(15 downto 0); + pos_calc_monit1_tag_en_o : out std_logic; + pos_calc_monit1_tag_dly_o : out std_logic_vector(15 downto 0); + pos_calc_monit1_tag_desync_cnt_rst_o : out std_logic; + pos_calc_monit1_tag_desync_cnt_i : in std_logic_vector(13 downto 0); + pos_calc_monit1_data_mask_ctl_en_o : out std_logic; + pos_calc_monit1_data_mask_samples_beg_o : out std_logic_vector(15 downto 0); + pos_calc_monit1_data_mask_samples_end_o : out std_logic_vector(15 downto 0); + pos_calc_monit_tag_en_o : out std_logic; + pos_calc_monit_tag_dly_o : out std_logic_vector(15 downto 0); + pos_calc_monit_tag_desync_cnt_rst_o : out std_logic; + pos_calc_monit_tag_desync_cnt_i : in std_logic_vector(13 downto 0); + pos_calc_monit_data_mask_ctl_en_o : out std_logic; + pos_calc_monit_data_mask_samples_beg_o : out std_logic_vector(15 downto 0); + pos_calc_monit_data_mask_samples_end_o : out std_logic_vector(15 downto 0); + pos_calc_offset_x_o : out std_logic_vector(31 downto 0); + pos_calc_offset_y_o : out std_logic_vector(31 downto 0) + ); end component wb_pos_calc_regs; begin @@ -869,8 +1123,135 @@ begin wb_ack_o => wb_slv_adp_in.ack, wb_stall_o => wb_slv_adp_in.stall, fs_clk2x_i => fs_clk_i, - regs_i => regs_in, - regs_o => regs_out + pos_calc_ds_tbt_thres_val_o => regs_ds_tbt_thres_val_o, + pos_calc_ds_tbt_thres_reserved_i => regs_ds_tbt_thres_reserved_i, + pos_calc_ds_fofb_thres_val_o => regs_ds_fofb_thres_val_o, + pos_calc_ds_fofb_thres_reserved_i => regs_ds_fofb_thres_reserved_i, + pos_calc_ds_monit_thres_val_o => regs_ds_monit_thres_val_o, + pos_calc_ds_monit_thres_reserved_i => regs_ds_monit_thres_reserved_i, + pos_calc_kx_val_o => regs_kx_val_o, + pos_calc_kx_reserved_i => regs_kx_reserved_i, + pos_calc_ky_val_o => regs_ky_val_o, + pos_calc_ky_reserved_i => regs_ky_reserved_i, + pos_calc_ksum_val_o => regs_ksum_val_o, + pos_calc_ksum_reserved_i => regs_ksum_reserved_i, + pos_calc_dsp_ctnr_tbt_ch01_i => regs_dsp_ctnr_tbt_ch01_i, + pos_calc_dsp_ctnr_tbt_ch23_i => regs_dsp_ctnr_tbt_ch23_i, + pos_calc_dsp_ctnr_fofb_ch01_i => regs_dsp_ctnr_fofb_ch01_i, + pos_calc_dsp_ctnr_fofb_ch23_i => regs_dsp_ctnr_fofb_ch23_i, + pos_calc_dsp_ctnr1_monit_cic_i => regs_dsp_ctnr1_monit_cic_i, + pos_calc_dsp_ctnr1_monit_cfir_i => regs_dsp_ctnr1_monit_cfir_i, + pos_calc_dsp_ctnr2_monit_pfir_i => regs_dsp_ctnr2_monit_pfir_i, + pos_calc_dsp_ctnr2_monit_fir_01_i => regs_dsp_ctnr2_monit_fir_01_i, + pos_calc_dsp_err_clr_tbt_o => regs_dsp_err_clr_tbt_o, + pos_calc_dsp_err_clr_fofb_o => regs_dsp_err_clr_fofb_o, + pos_calc_dsp_err_clr_monit_part1_o => regs_dsp_err_clr_monit_part1_o, + pos_calc_dsp_err_clr_monit_part2_o => regs_dsp_err_clr_monit_part2_o, + pos_calc_dds_cfg_valid_ch0_o => regs_dds_cfg_valid_ch0_o, + pos_calc_dds_cfg_test_data_o => regs_dds_cfg_test_data_o, + pos_calc_dds_cfg_reserved_ch0_i => regs_dds_cfg_reserved_ch0_i, + pos_calc_dds_cfg_valid_ch1_o => regs_dds_cfg_valid_ch1_o, + pos_calc_dds_cfg_reserved_ch1_i => regs_dds_cfg_reserved_ch1_i, + pos_calc_dds_cfg_valid_ch2_o => regs_dds_cfg_valid_ch2_o, + pos_calc_dds_cfg_reserved_ch2_i => regs_dds_cfg_reserved_ch2_i, + pos_calc_dds_cfg_valid_ch3_o => regs_dds_cfg_valid_ch3_o, + pos_calc_dds_cfg_reserved_ch3_i => regs_dds_cfg_reserved_ch3_i, + pos_calc_dds_pinc_ch0_val_o => regs_dds_pinc_ch0_val_o, + pos_calc_dds_pinc_ch0_reserved_i => regs_dds_pinc_ch0_reserved_i, + pos_calc_dds_pinc_ch1_val_o => regs_dds_pinc_ch1_val_o, + pos_calc_dds_pinc_ch1_reserved_i => regs_dds_pinc_ch1_reserved_i, + pos_calc_dds_pinc_ch2_val_o => regs_dds_pinc_ch2_val_o, + pos_calc_dds_pinc_ch2_reserved_i => regs_dds_pinc_ch2_reserved_i, + pos_calc_dds_pinc_ch3_val_o => regs_dds_pinc_ch3_val_o, + pos_calc_dds_pinc_ch3_reserved_i => regs_dds_pinc_ch3_reserved_i, + pos_calc_dds_poff_ch0_val_o => regs_dds_poff_ch0_val_o, + pos_calc_dds_poff_ch0_reserved_i => regs_dds_poff_ch0_reserved_i, + pos_calc_dds_poff_ch1_val_o => regs_dds_poff_ch1_val_o, + pos_calc_dds_poff_ch1_reserved_i => regs_dds_poff_ch1_reserved_i, + pos_calc_dds_poff_ch2_val_o => regs_dds_poff_ch2_val_o, + pos_calc_dds_poff_ch2_reserved_i => regs_dds_poff_ch2_reserved_i, + pos_calc_dds_poff_ch3_val_o => regs_dds_poff_ch3_val_o, + pos_calc_dds_poff_ch3_reserved_i => regs_dds_poff_ch3_reserved_i, + pos_calc_dsp_monit_amp_ch0_i => regs_dsp_monit_amp_ch0_i, + pos_calc_dsp_monit_amp_ch1_i => regs_dsp_monit_amp_ch1_i, + pos_calc_dsp_monit_amp_ch2_i => regs_dsp_monit_amp_ch2_i, + pos_calc_dsp_monit_amp_ch3_i => regs_dsp_monit_amp_ch3_i, + pos_calc_dsp_monit_pos_x_i => regs_dsp_monit_pos_x_i, + pos_calc_dsp_monit_pos_y_i => regs_dsp_monit_pos_y_i, + pos_calc_dsp_monit_pos_q_i => regs_dsp_monit_pos_q_i, + pos_calc_dsp_monit_pos_sum_i => regs_dsp_monit_pos_sum_i, + pos_calc_dsp_monit_updt_o => regs_dsp_monit_updt_o, + pos_calc_dsp_monit_updt_wr_o => regs_dsp_monit_updt_wr_o, + pos_calc_dsp_monit1_amp_ch0_i => regs_dsp_monit1_amp_ch0_i, + pos_calc_dsp_monit1_amp_ch1_i => regs_dsp_monit1_amp_ch1_i, + pos_calc_dsp_monit1_amp_ch2_i => regs_dsp_monit1_amp_ch2_i, + pos_calc_dsp_monit1_amp_ch3_i => regs_dsp_monit1_amp_ch3_i, + pos_calc_dsp_monit1_pos_x_i => regs_dsp_monit1_pos_x_i, + pos_calc_dsp_monit1_pos_y_i => regs_dsp_monit1_pos_y_i, + pos_calc_dsp_monit1_pos_q_i => regs_dsp_monit1_pos_q_i, + pos_calc_dsp_monit1_pos_sum_i => regs_dsp_monit1_pos_sum_i, + pos_calc_dsp_monit1_updt_o => regs_dsp_monit1_updt_o, + pos_calc_dsp_monit1_updt_wr_o => regs_dsp_monit1_updt_wr_o, + pos_calc_ampfifo_monit_wr_req_i => regs_ampfifo_monit_wr_req_i, + pos_calc_ampfifo_monit_wr_full_o => regs_ampfifo_monit_wr_full_o, + pos_calc_ampfifo_monit_wr_empty_o => regs_ampfifo_monit_wr_empty_o, + pos_calc_ampfifo_monit_wr_usedw_o => regs_ampfifo_monit_wr_usedw_o, + pos_calc_ampfifo_monit_amp_ch0_i => regs_ampfifo_monit_amp_ch0_i, + pos_calc_ampfifo_monit_amp_ch1_i => regs_ampfifo_monit_amp_ch1_i, + pos_calc_ampfifo_monit_amp_ch2_i => regs_ampfifo_monit_amp_ch2_i, + pos_calc_ampfifo_monit_amp_ch3_i => regs_ampfifo_monit_amp_ch3_i, + pos_calc_posfifo_monit_wr_req_i => regs_posfifo_monit_wr_req_i, + pos_calc_posfifo_monit_wr_full_o => regs_posfifo_monit_wr_full_o, + pos_calc_posfifo_monit_wr_empty_o => regs_posfifo_monit_wr_empty_o, + pos_calc_posfifo_monit_wr_usedw_o => regs_posfifo_monit_wr_usedw_o, + pos_calc_posfifo_monit_pos_x_i => regs_posfifo_monit_pos_x_i, + pos_calc_posfifo_monit_pos_y_i => regs_posfifo_monit_pos_y_i, + pos_calc_posfifo_monit_pos_q_i => regs_posfifo_monit_pos_q_i, + pos_calc_posfifo_monit_pos_sum_i => regs_posfifo_monit_pos_sum_i, + pos_calc_ampfifo_monit1_wr_req_i => regs_ampfifo_monit1_wr_req_i, + pos_calc_ampfifo_monit1_wr_full_o => regs_ampfifo_monit1_wr_full_o, + pos_calc_ampfifo_monit1_wr_empty_o => regs_ampfifo_monit1_wr_empty_o, + pos_calc_ampfifo_monit1_wr_usedw_o => regs_ampfifo_monit1_wr_usedw_o, + pos_calc_ampfifo_monit1_amp_ch0_i => regs_ampfifo_monit1_amp_ch0_i, + pos_calc_ampfifo_monit1_amp_ch1_i => regs_ampfifo_monit1_amp_ch1_i, + pos_calc_ampfifo_monit1_amp_ch2_i => regs_ampfifo_monit1_amp_ch2_i, + pos_calc_ampfifo_monit1_amp_ch3_i => regs_ampfifo_monit1_amp_ch3_i, + pos_calc_posfifo_monit1_wr_req_i => regs_posfifo_monit1_wr_req_i, + pos_calc_posfifo_monit1_wr_full_o => regs_posfifo_monit1_wr_full_o, + pos_calc_posfifo_monit1_wr_empty_o => regs_posfifo_monit1_wr_empty_o, + pos_calc_posfifo_monit1_wr_usedw_o => regs_posfifo_monit1_wr_usedw_o, + pos_calc_posfifo_monit1_pos_x_i => regs_posfifo_monit1_pos_x_i, + pos_calc_posfifo_monit1_pos_y_i => regs_posfifo_monit1_pos_y_i, + pos_calc_posfifo_monit1_pos_q_i => regs_posfifo_monit1_pos_q_i, + pos_calc_posfifo_monit1_pos_sum_i => regs_posfifo_monit1_pos_sum_i, + pos_calc_sw_tag_en_o => regs_sw_tag_en_o, + pos_calc_sw_tag_desync_cnt_rst_o => regs_sw_tag_desync_cnt_rst_o, + pos_calc_sw_tag_desync_cnt_i => regs_sw_tag_desync_cnt_i, + pos_calc_sw_data_mask_en_o => regs_sw_data_mask_en_o, + pos_calc_sw_data_mask_samples_o => regs_sw_data_mask_samples_o, + pos_calc_tbt_tag_en_o => regs_tbt_tag_en_o, + pos_calc_tbt_tag_dly_o => regs_tbt_tag_dly_o, + pos_calc_tbt_tag_desync_cnt_rst_o => regs_tbt_tag_desync_cnt_rst_o, + pos_calc_tbt_tag_desync_cnt_i => regs_tbt_tag_desync_cnt_i, + pos_calc_tbt_data_mask_ctl_en_o => regs_tbt_data_mask_ctl_en_o, + pos_calc_tbt_data_mask_samples_beg_o => regs_tbt_data_mask_samples_beg_o, + pos_calc_tbt_data_mask_samples_end_o => regs_tbt_data_mask_samples_end_o, + pos_calc_monit1_tag_en_o => regs_monit1_tag_en_o, + pos_calc_monit1_tag_dly_o => regs_monit1_tag_dly_o, + pos_calc_monit1_tag_desync_cnt_rst_o => regs_monit1_tag_desync_cnt_rst_o, + pos_calc_monit1_tag_desync_cnt_i => regs_monit1_tag_desync_cnt_i, + pos_calc_monit1_data_mask_ctl_en_o => regs_monit1_data_mask_ctl_en_o, + pos_calc_monit1_data_mask_samples_beg_o => regs_monit1_data_mask_samples_beg_o, + pos_calc_monit1_data_mask_samples_end_o => regs_monit1_data_mask_samples_end_o, + pos_calc_monit_tag_en_o => regs_monit_tag_en_o, + pos_calc_monit_tag_dly_o => regs_monit_tag_dly_o, + pos_calc_monit_tag_desync_cnt_rst_o => regs_monit_tag_desync_cnt_rst_o, + pos_calc_monit_tag_desync_cnt_i => regs_monit_tag_desync_cnt_i, + pos_calc_monit_data_mask_ctl_en_o => regs_monit_data_mask_ctl_en_o, + pos_calc_monit_data_mask_samples_beg_o => regs_monit_data_mask_samples_beg_o, + pos_calc_monit_data_mask_samples_end_o => regs_monit_data_mask_samples_end_o, + pos_calc_offset_x_o => regs_pos_calc_offset_x_o, + pos_calc_offset_y_o => regs_pos_calc_offset_y_o ); -- Unused wishbone signals @@ -878,24 +1259,24 @@ begin wb_slv_adp_in.rty <= '0'; -- Registers fixed assignments - regs_in.ds_tbt_thres_reserved_i <= (others => '0'); - regs_in.ds_fofb_thres_reserved_i <= (others => '0'); - regs_in.ds_monit_thres_reserved_i <= (others => '0'); - regs_in.kx_reserved_i <= (others => '0'); - regs_in.ky_reserved_i <= (others => '0'); - regs_in.ksum_reserved_i <= (others => '0'); - regs_in.dds_cfg_reserved_ch0_i <= (others => '0'); - regs_in.dds_cfg_reserved_ch1_i <= (others => '0'); - regs_in.dds_cfg_reserved_ch2_i <= (others => '0'); - regs_in.dds_cfg_reserved_ch3_i <= (others => '0'); - regs_in.dds_pinc_ch0_reserved_i <= (others => '0'); - regs_in.dds_pinc_ch1_reserved_i <= (others => '0'); - regs_in.dds_pinc_ch2_reserved_i <= (others => '0'); - regs_in.dds_pinc_ch3_reserved_i <= (others => '0'); - regs_in.dds_poff_ch0_reserved_i <= (others => '0'); - regs_in.dds_poff_ch1_reserved_i <= (others => '0'); - regs_in.dds_poff_ch2_reserved_i <= (others => '0'); - regs_in.dds_poff_ch3_reserved_i <= (others => '0'); + regs_ds_tbt_thres_reserved_i <= (others => '0'); + regs_ds_fofb_thres_reserved_i <= (others => '0'); + regs_ds_monit_thres_reserved_i <= (others => '0'); + regs_kx_reserved_i <= (others => '0'); + regs_ky_reserved_i <= (others => '0'); + regs_ksum_reserved_i <= (others => '0'); + regs_dds_cfg_reserved_ch0_i <= (others => '0'); + regs_dds_cfg_reserved_ch1_i <= (others => '0'); + regs_dds_cfg_reserved_ch2_i <= (others => '0'); + regs_dds_cfg_reserved_ch3_i <= (others => '0'); + regs_dds_pinc_ch0_reserved_i <= (others => '0'); + regs_dds_pinc_ch1_reserved_i <= (others => '0'); + regs_dds_pinc_ch2_reserved_i <= (others => '0'); + regs_dds_pinc_ch3_reserved_i <= (others => '0'); + regs_dds_poff_ch0_reserved_i <= (others => '0'); + regs_dds_poff_ch1_reserved_i <= (others => '0'); + regs_dds_poff_ch2_reserved_i <= (others => '0'); + regs_dds_poff_ch3_reserved_i <= (others => '0'); -------------------------------------------------------------------------------- -- This is the old interface for acquiring data from Monit. It goes like this: @@ -909,54 +1290,54 @@ begin ------------------------------------ -- Sync with clk_i - regs_in.dsp_monit1_amp_ch0_i <= - std_logic_vector(resize(signed(monit1_amp_ch0_wb_sync), regs_in.dsp_monit1_amp_ch0_i'length)); - regs_in.dsp_monit1_amp_ch1_i <= - std_logic_vector(resize(signed(monit1_amp_ch1_wb_sync), regs_in.dsp_monit1_amp_ch1_i'length)); - regs_in.dsp_monit1_amp_ch2_i <= - std_logic_vector(resize(signed(monit1_amp_ch2_wb_sync), regs_in.dsp_monit1_amp_ch2_i'length)); - regs_in.dsp_monit1_amp_ch3_i <= - std_logic_vector(resize(signed(monit1_amp_ch3_wb_sync), regs_in.dsp_monit1_amp_ch3_i'length)); + regs_dsp_monit1_amp_ch0_i <= + std_logic_vector(resize(signed(monit1_amp_ch0_wb_sync), regs_dsp_monit1_amp_ch0_i'length)); + regs_dsp_monit1_amp_ch1_i <= + std_logic_vector(resize(signed(monit1_amp_ch1_wb_sync), regs_dsp_monit1_amp_ch1_i'length)); + regs_dsp_monit1_amp_ch2_i <= + std_logic_vector(resize(signed(monit1_amp_ch2_wb_sync), regs_dsp_monit1_amp_ch2_i'length)); + regs_dsp_monit1_amp_ch3_i <= + std_logic_vector(resize(signed(monit1_amp_ch3_wb_sync), regs_dsp_monit1_amp_ch3_i'length)); -- Sync with clk_i - regs_in.dsp_monit1_pos_x_i <= - std_logic_vector(resize(signed(monit1_pos_x_wb_sync), regs_in.dsp_monit1_pos_x_i'length)); - regs_in.dsp_monit1_pos_y_i <= - std_logic_vector(resize(signed(monit1_pos_y_wb_sync), regs_in.dsp_monit1_pos_y_i'length)); - regs_in.dsp_monit1_pos_q_i <= - std_logic_vector(resize(signed(monit1_pos_q_wb_sync), regs_in.dsp_monit1_pos_q_i'length)); - regs_in.dsp_monit1_pos_sum_i <= - std_logic_vector(resize(signed(monit1_pos_sum_wb_sync), regs_in.dsp_monit1_pos_sum_i'length)); + regs_dsp_monit1_pos_x_i <= + std_logic_vector(resize(signed(monit1_pos_x_wb_sync), regs_dsp_monit1_pos_x_i'length)); + regs_dsp_monit1_pos_y_i <= + std_logic_vector(resize(signed(monit1_pos_y_wb_sync), regs_dsp_monit1_pos_y_i'length)); + regs_dsp_monit1_pos_q_i <= + std_logic_vector(resize(signed(monit1_pos_q_wb_sync), regs_dsp_monit1_pos_q_i'length)); + regs_dsp_monit1_pos_sum_i <= + std_logic_vector(resize(signed(monit1_pos_sum_wb_sync), regs_dsp_monit1_pos_sum_i'length)); -- Sync with clk_i - dsp_monit1_updt <= regs_out.dsp_monit1_updt_wr_o; + dsp_monit1_updt <= regs_dsp_monit1_updt_wr_o; ------------------------------------ -- Monit ------------------------------------ -- Sync with clk_i - regs_in.dsp_monit_amp_ch0_i <= - std_logic_vector(resize(signed(monit_amp_ch0_wb_sync), regs_in.dsp_monit_amp_ch0_i'length)); - regs_in.dsp_monit_amp_ch1_i <= - std_logic_vector(resize(signed(monit_amp_ch1_wb_sync), regs_in.dsp_monit_amp_ch1_i'length)); - regs_in.dsp_monit_amp_ch2_i <= - std_logic_vector(resize(signed(monit_amp_ch2_wb_sync), regs_in.dsp_monit_amp_ch2_i'length)); - regs_in.dsp_monit_amp_ch3_i <= - std_logic_vector(resize(signed(monit_amp_ch3_wb_sync), regs_in.dsp_monit_amp_ch3_i'length)); + regs_dsp_monit_amp_ch0_i <= + std_logic_vector(resize(signed(monit_amp_ch0_wb_sync), regs_dsp_monit_amp_ch0_i'length)); + regs_dsp_monit_amp_ch1_i <= + std_logic_vector(resize(signed(monit_amp_ch1_wb_sync), regs_dsp_monit_amp_ch1_i'length)); + regs_dsp_monit_amp_ch2_i <= + std_logic_vector(resize(signed(monit_amp_ch2_wb_sync), regs_dsp_monit_amp_ch2_i'length)); + regs_dsp_monit_amp_ch3_i <= + std_logic_vector(resize(signed(monit_amp_ch3_wb_sync), regs_dsp_monit_amp_ch3_i'length)); -- Sync with clk_i - regs_in.dsp_monit_pos_x_i <= - std_logic_vector(resize(signed(monit_pos_x_wb_sync), regs_in.dsp_monit_pos_x_i'length)); - regs_in.dsp_monit_pos_y_i <= - std_logic_vector(resize(signed(monit_pos_y_wb_sync), regs_in.dsp_monit_pos_y_i'length)); - regs_in.dsp_monit_pos_q_i <= - std_logic_vector(resize(signed(monit_pos_q_wb_sync), regs_in.dsp_monit_pos_q_i'length)); - regs_in.dsp_monit_pos_sum_i <= - std_logic_vector(resize(signed(monit_pos_sum_wb_sync), regs_in.dsp_monit_pos_sum_i'length)); + regs_dsp_monit_pos_x_i <= + std_logic_vector(resize(signed(monit_pos_x_wb_sync), regs_dsp_monit_pos_x_i'length)); + regs_dsp_monit_pos_y_i <= + std_logic_vector(resize(signed(monit_pos_y_wb_sync), regs_dsp_monit_pos_y_i'length)); + regs_dsp_monit_pos_q_i <= + std_logic_vector(resize(signed(monit_pos_q_wb_sync), regs_dsp_monit_pos_q_i'length)); + regs_dsp_monit_pos_sum_i <= + std_logic_vector(resize(signed(monit_pos_sum_wb_sync), regs_dsp_monit_pos_sum_i'length)); -- Sync with clk_i - dsp_monit_updt <= regs_out.dsp_monit_updt_wr_o; + dsp_monit_updt <= regs_dsp_monit_updt_wr_o; -------------------------------------------------------------------------------- -- This is the new interface for acquiring data from Monit. It goes like this: @@ -968,56 +1349,56 @@ begin -- Monit 1 ------------------------------------ - regs_in.ampfifo_monit1_wr_req_i <= monit1_amp_valid_out_wb_sync when - regs_out.ampfifo_monit1_wr_full_o = '0' else '0'; - regs_in.ampfifo_monit1_amp_ch0_i <= - std_logic_vector(resize(signed(monit1_amp_ch0_out_wb_sync), regs_in.ampfifo_monit1_amp_ch0_i'length)); - regs_in.ampfifo_monit1_amp_ch1_i <= - std_logic_vector(resize(signed(monit1_amp_ch1_out_wb_sync), regs_in.ampfifo_monit1_amp_ch1_i'length)); - regs_in.ampfifo_monit1_amp_ch2_i <= - std_logic_vector(resize(signed(monit1_amp_ch2_out_wb_sync), regs_in.ampfifo_monit1_amp_ch2_i'length)); - regs_in.ampfifo_monit1_amp_ch3_i <= - std_logic_vector(resize(signed(monit1_amp_ch3_out_wb_sync), regs_in.ampfifo_monit1_amp_ch3_i'length)); - - regs_in.posfifo_monit1_wr_req_i <= monit1_pos_valid_out_wb_sync when - regs_out.posfifo_monit1_wr_full_o = '0' else '0'; - regs_in.posfifo_monit1_pos_x_i <= - std_logic_vector(resize(signed(monit1_pos_x_out_wb_sync), regs_in.posfifo_monit1_pos_x_i'length)); - regs_in.posfifo_monit1_pos_y_i <= - std_logic_vector(resize(signed(monit1_pos_y_out_wb_sync), regs_in.posfifo_monit1_pos_y_i'length)); - regs_in.posfifo_monit1_pos_q_i <= - std_logic_vector(resize(signed(monit1_pos_q_out_wb_sync), regs_in.posfifo_monit1_pos_q_i'length)); - regs_in.posfifo_monit1_pos_sum_i <= - std_logic_vector(resize(signed(monit1_pos_sum_out_wb_sync), regs_in.posfifo_monit1_pos_sum_i'length)); + regs_ampfifo_monit1_wr_req_i <= monit1_amp_valid_out_wb_sync when + regs_ampfifo_monit1_wr_full_o = '0' else '0'; + regs_ampfifo_monit1_amp_ch0_i <= + std_logic_vector(resize(signed(monit1_amp_ch0_out_wb_sync), regs_ampfifo_monit1_amp_ch0_i'length)); + regs_ampfifo_monit1_amp_ch1_i <= + std_logic_vector(resize(signed(monit1_amp_ch1_out_wb_sync), regs_ampfifo_monit1_amp_ch1_i'length)); + regs_ampfifo_monit1_amp_ch2_i <= + std_logic_vector(resize(signed(monit1_amp_ch2_out_wb_sync), regs_ampfifo_monit1_amp_ch2_i'length)); + regs_ampfifo_monit1_amp_ch3_i <= + std_logic_vector(resize(signed(monit1_amp_ch3_out_wb_sync), regs_ampfifo_monit1_amp_ch3_i'length)); + + regs_posfifo_monit1_wr_req_i <= monit1_pos_valid_out_wb_sync when + regs_posfifo_monit1_wr_full_o = '0' else '0'; + regs_posfifo_monit1_pos_x_i <= + std_logic_vector(resize(signed(monit1_pos_x_out_wb_sync), regs_posfifo_monit1_pos_x_i'length)); + regs_posfifo_monit1_pos_y_i <= + std_logic_vector(resize(signed(monit1_pos_y_out_wb_sync), regs_posfifo_monit1_pos_y_i'length)); + regs_posfifo_monit1_pos_q_i <= + std_logic_vector(resize(signed(monit1_pos_q_out_wb_sync), regs_posfifo_monit1_pos_q_i'length)); + regs_posfifo_monit1_pos_sum_i <= + std_logic_vector(resize(signed(monit1_pos_sum_out_wb_sync), regs_posfifo_monit1_pos_sum_i'length)); ------------------------------------ -- Monit ------------------------------------ - regs_in.ampfifo_monit_wr_req_i <= monit_amp_valid_out_wb_sync when - regs_out.ampfifo_monit_wr_full_o = '0' else '0'; - regs_in.ampfifo_monit_amp_ch0_i <= - std_logic_vector(resize(signed(monit_amp_ch0_out_wb_sync), regs_in.ampfifo_monit_amp_ch0_i'length)); - regs_in.ampfifo_monit_amp_ch1_i <= - std_logic_vector(resize(signed(monit_amp_ch1_out_wb_sync), regs_in.ampfifo_monit_amp_ch1_i'length)); - regs_in.ampfifo_monit_amp_ch2_i <= - std_logic_vector(resize(signed(monit_amp_ch2_out_wb_sync), regs_in.ampfifo_monit_amp_ch2_i'length)); - regs_in.ampfifo_monit_amp_ch3_i <= - std_logic_vector(resize(signed(monit_amp_ch3_out_wb_sync), regs_in.ampfifo_monit_amp_ch3_i'length)); - - regs_in.posfifo_monit_wr_req_i <= monit_pos_valid_out_wb_sync when - regs_out.posfifo_monit_wr_full_o = '0' else '0'; - regs_in.posfifo_monit_pos_x_i <= - std_logic_vector(resize(signed(monit_pos_x_out_wb_sync), regs_in.posfifo_monit_pos_x_i'length)); - regs_in.posfifo_monit_pos_y_i <= - std_logic_vector(resize(signed(monit_pos_y_out_wb_sync), regs_in.posfifo_monit_pos_y_i'length)); - regs_in.posfifo_monit_pos_q_i <= - std_logic_vector(resize(signed(monit_pos_q_out_wb_sync), regs_in.posfifo_monit_pos_q_i'length)); - regs_in.posfifo_monit_pos_sum_i <= - std_logic_vector(resize(signed(monit_pos_sum_out_wb_sync), regs_in.posfifo_monit_pos_sum_i'length)); + regs_ampfifo_monit_wr_req_i <= monit_amp_valid_out_wb_sync when + regs_ampfifo_monit_wr_full_o = '0' else '0'; + regs_ampfifo_monit_amp_ch0_i <= + std_logic_vector(resize(signed(monit_amp_ch0_out_wb_sync), regs_ampfifo_monit_amp_ch0_i'length)); + regs_ampfifo_monit_amp_ch1_i <= + std_logic_vector(resize(signed(monit_amp_ch1_out_wb_sync), regs_ampfifo_monit_amp_ch1_i'length)); + regs_ampfifo_monit_amp_ch2_i <= + std_logic_vector(resize(signed(monit_amp_ch2_out_wb_sync), regs_ampfifo_monit_amp_ch2_i'length)); + regs_ampfifo_monit_amp_ch3_i <= + std_logic_vector(resize(signed(monit_amp_ch3_out_wb_sync), regs_ampfifo_monit_amp_ch3_i'length)); + + regs_posfifo_monit_wr_req_i <= monit_pos_valid_out_wb_sync when + regs_posfifo_monit_wr_full_o = '0' else '0'; + regs_posfifo_monit_pos_x_i <= + std_logic_vector(resize(signed(monit_pos_x_out_wb_sync), regs_posfifo_monit_pos_x_i'length)); + regs_posfifo_monit_pos_y_i <= + std_logic_vector(resize(signed(monit_pos_y_out_wb_sync), regs_posfifo_monit_pos_y_i'length)); + regs_posfifo_monit_pos_q_i <= + std_logic_vector(resize(signed(monit_pos_q_out_wb_sync), regs_posfifo_monit_pos_q_i'length)); + regs_posfifo_monit_pos_sum_i <= + std_logic_vector(resize(signed(monit_pos_sum_out_wb_sync), regs_posfifo_monit_pos_sum_i'length)); -- Test data - test_data <= regs_out.dds_cfg_test_data_o; + test_data <= regs_dds_cfg_test_data_o; gen_with_downconv : if (g_with_downconv) generate @@ -1168,29 +1549,29 @@ begin dsp_chc <= adc_ch1_sp; dsp_chd <= adc_ch3_sp; dsp_ch_tag <= adc_tag_sp; - dsp_ch_tag_en <= regs_out.sw_tag_en_o; + dsp_ch_tag_en <= regs_sw_tag_en_o; dsp_ch_valid <= adc_valid_sp; - tbt_decim_tag_en <= regs_out.tbt_tag_en_o; - tbt_decim_tag_dly_c <= regs_out.tbt_tag_dly_o(c_tbt_decim_tag_dly_width-1 downto 0); - tbt_decim_mask_en <= regs_out.tbt_data_mask_ctl_en_o; - tbt_decim_mask_num_samples_beg <= unsigned(regs_out.tbt_data_mask_samples_beg_o(c_tbt_cic_mask_samples_width-1 downto 0)); - tbt_decim_mask_num_samples_end <= unsigned(regs_out.tbt_data_mask_samples_end_o(c_tbt_cic_mask_samples_width-1 downto 0)); + tbt_decim_tag_en <= regs_tbt_tag_en_o; + tbt_decim_tag_dly_c <= regs_tbt_tag_dly_o(c_tbt_decim_tag_dly_width-1 downto 0); + tbt_decim_mask_en <= regs_tbt_data_mask_ctl_en_o; + tbt_decim_mask_num_samples_beg <= unsigned(regs_tbt_data_mask_samples_beg_o(c_tbt_cic_mask_samples_width-1 downto 0)); + tbt_decim_mask_num_samples_end <= unsigned(regs_tbt_data_mask_samples_end_o(c_tbt_cic_mask_samples_width-1 downto 0)); - fofb_decim_mask_en <= regs_out.sw_data_mask_en_o; - fofb_decim_mask_num_samples <= unsigned(regs_out.sw_data_mask_samples_o); + fofb_decim_mask_en <= regs_sw_data_mask_en_o; + fofb_decim_mask_num_samples <= unsigned(regs_sw_data_mask_samples_o); - monit1_decim_tag_en <= regs_out.monit1_tag_en_o; - monit1_decim_tag_dly_c <= regs_out.monit1_tag_dly_o(c_monit1_decim_tag_dly_width-1 downto 0); - monit1_decim_mask_en <= regs_out.monit1_data_mask_ctl_en_o; - monit1_decim_mask_num_samples_beg <= unsigned(regs_out.monit1_data_mask_samples_beg_o(c_monit1_cic_mask_samples_width-1 downto 0)); - monit1_decim_mask_num_samples_end <= unsigned(regs_out.monit1_data_mask_samples_end_o(c_monit1_cic_mask_samples_width-1 downto 0)); + monit1_decim_tag_en <= regs_monit1_tag_en_o; + monit1_decim_tag_dly_c <= regs_monit1_tag_dly_o(c_monit1_decim_tag_dly_width-1 downto 0); + monit1_decim_mask_en <= regs_monit1_data_mask_ctl_en_o; + monit1_decim_mask_num_samples_beg <= unsigned(regs_monit1_data_mask_samples_beg_o(c_monit1_cic_mask_samples_width-1 downto 0)); + monit1_decim_mask_num_samples_end <= unsigned(regs_monit1_data_mask_samples_end_o(c_monit1_cic_mask_samples_width-1 downto 0)); - monit_decim_tag_en <= regs_out.monit_tag_en_o; - monit_decim_tag_dly_c <= regs_out.monit_tag_dly_o(c_monit2_decim_tag_dly_width-1 downto 0); - monit_decim_mask_en <= regs_out.monit_data_mask_ctl_en_o; - monit_decim_mask_num_samples_beg <= unsigned(regs_out.monit_data_mask_samples_beg_o(c_monit2_cic_mask_samples_width-1 downto 0)); - monit_decim_mask_num_samples_end <= unsigned(regs_out.monit_data_mask_samples_end_o(c_monit2_cic_mask_samples_width-1 downto 0)); + monit_decim_tag_en <= regs_monit_tag_en_o; + monit_decim_tag_dly_c <= regs_monit_tag_dly_o(c_monit2_decim_tag_dly_width-1 downto 0); + monit_decim_mask_en <= regs_monit_data_mask_ctl_en_o; + monit_decim_mask_num_samples_beg <= unsigned(regs_monit_data_mask_samples_beg_o(c_monit2_cic_mask_samples_width-1 downto 0)); + monit_decim_mask_num_samples_end <= unsigned(regs_monit_data_mask_samples_end_o(c_monit2_cic_mask_samples_width-1 downto 0)); ---------------------------------------------- -- Generate Triggers for all data rates @@ -1335,7 +1716,10 @@ begin g_fofb_cordic_ratio => g_fofb_cordic_ratio, -- width of K constants - g_k_width => g_k_width, + g_k_width => c_k_width, + + -- width of offset constants + g_offset_width => c_offset_width, --width for IQ output g_IQ_width => g_IQ_width @@ -1353,9 +1737,12 @@ begin clk_i => fs_clk_i, rst_i => fs_rst, - ksum_i => regs_out.ksum_val_o(c_k_width-1 downto 0), - kx_i => regs_out.kx_val_o(c_k_width-1 downto 0), - ky_i => regs_out.ky_val_o(c_k_width-1 downto 0), + ksum_i => regs_ksum_val_o(c_k_width-1 downto 0), + kx_i => regs_kx_val_o(c_k_width-1 downto 0), + ky_i => regs_ky_val_o(c_k_width-1 downto 0), + + offset_x_i => regs_pos_calc_offset_x_o(c_offset_width-1 downto 0), + offset_y_i => regs_pos_calc_offset_y_o(c_offset_width-1 downto 0), mix_ch0_i_o => mix_ch0_i, mix_ch0_q_o => mix_ch0_q, @@ -1371,8 +1758,8 @@ begin -- Synchronization trigger for TBT filter chain tbt_tag_i => tbt_decim_tag, tbt_tag_en_i => tbt_decim_tag_en, - tbt_tag_desync_cnt_rst_i => regs_out.tbt_tag_desync_cnt_rst_o, - tbt_tag_desync_cnt_o => regs_in.tbt_tag_desync_cnt_i, + tbt_tag_desync_cnt_rst_i => regs_tbt_tag_desync_cnt_rst_o, + tbt_tag_desync_cnt_o => regs_tbt_tag_desync_cnt_i, tbt_decim_mask_en_i => tbt_decim_mask_en, tbt_decim_mask_num_samples_beg_i => tbt_decim_mask_num_samples_beg, tbt_decim_mask_num_samples_end_i => tbt_decim_mask_num_samples_end, @@ -1401,8 +1788,8 @@ begin tbt_pha_valid_o => tbt_pha_valid, tbt_pha_ce_o => tbt_pha_ce, - fofb_decim_desync_cnt_rst_i => regs_out.sw_tag_desync_cnt_rst_o, - fofb_decim_desync_cnt_o => regs_in.sw_tag_desync_cnt_i, + fofb_decim_desync_cnt_rst_i => regs_sw_tag_desync_cnt_rst_o, + fofb_decim_desync_cnt_o => regs_sw_tag_desync_cnt_i, fofb_decim_mask_en_i => fofb_decim_mask_en, fofb_decim_mask_num_samples_i => fofb_decim_mask_num_samples, fofb_decim_ch0_i_o => fofb_decim_ch0_i, @@ -1433,8 +1820,8 @@ begin -- Synchronization trigger for TBT filter chain monit1_tag_i => monit1_decim_tag, monit1_tag_en_i => monit1_decim_tag_en, - monit1_tag_desync_cnt_rst_i => regs_out.monit1_tag_desync_cnt_rst_o, - monit1_tag_desync_cnt_o => regs_in.monit1_tag_desync_cnt_i, + monit1_tag_desync_cnt_rst_i => regs_monit1_tag_desync_cnt_rst_o, + monit1_tag_desync_cnt_o => regs_monit1_tag_desync_cnt_i, monit1_decim_mask_en_i => monit1_decim_mask_en, monit1_decim_mask_num_samples_beg_i => monit1_decim_mask_num_samples_beg, monit1_decim_mask_num_samples_end_i => monit1_decim_mask_num_samples_end, @@ -1448,8 +1835,8 @@ begin -- Synchronization trigger for TBT filter chain monit_tag_i => monit_decim_tag, monit_tag_en_i => monit_decim_tag_en, - monit_tag_desync_cnt_rst_i => regs_out.monit_tag_desync_cnt_rst_o, - monit_tag_desync_cnt_o => regs_in.monit_tag_desync_cnt_i, + monit_tag_desync_cnt_rst_i => regs_monit_tag_desync_cnt_rst_o, + monit_tag_desync_cnt_o => regs_monit_tag_desync_cnt_i, monit_decim_mask_en_i => monit_decim_mask_en, monit_decim_mask_num_samples_beg_i => monit_decim_mask_num_samples_beg, monit_decim_mask_num_samples_end_i => monit_decim_mask_num_samples_end, diff --git a/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.wb b/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.wb index fb855cc1..0435b019 100644 --- a/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.wb +++ b/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.wb @@ -892,88 +892,6 @@ peripheral { }; }; - ---------------------------------------------------------------------------- - -- Monit. Amplitude/Position Values New Interface - ---------------------------------------------------------------------------- - - fifo_reg { - size = 16; - direction = CORE_TO_BUS; - prefix = "ampfifo_monit"; - name = "AMP FIFO Monitoring"; - description = "This FIFO holds most recent amplitude values from DSP Monit. chain"; - flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; - flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; - - field { - name = "Channel 0 Amplitude"; - prefix = "amp_ch0"; - type = SLV; - size = 32; - }; - - field { - name = "Channel 1 Amplitude"; - prefix = "amp_ch1"; - type = SLV; - size = 32; - }; - - field { - name = "Channel 2 Amplitude"; - prefix = "amp_ch2"; - type = SLV; - size = 32; - }; - - field { - name = "Channel 3 Amplitude"; - prefix = "amp_ch3"; - type = SLV; - size = 32; - }; - - }; - - fifo_reg { - size = 16; - direction = CORE_TO_BUS; - prefix = "posfifo_monit"; - name = "POS FIFO Monitoring"; - description = "This FIFO holds most recent position values from DSP Monit. chain"; - flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; - flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; - - field { - name = "Channel X Position"; - prefix = "pos_x"; - type = SLV; - size = 32; - }; - - field { - name = "Channel Y Position"; - prefix = "pos_y"; - type = SLV; - size = 32; - }; - - field { - name = "Channel Q Position"; - prefix = "pos_q"; - type = SLV; - size = 32; - }; - - field { - name = "Channel Sum Position"; - prefix = "pos_sum"; - type = SLV; - size = 32; - }; - - }; - ---------------------------------------------------------------------------- -- Monit. 1 Amplitude Values ---------------------------------------------------------------------------- @@ -1130,6 +1048,88 @@ peripheral { }; }; + ---------------------------------------------------------------------------- + -- Monit. Amplitude/Position Values New Interface + ---------------------------------------------------------------------------- + + fifo_reg { + size = 16; + direction = CORE_TO_BUS; + prefix = "ampfifo_monit"; + name = "AMP FIFO Monitoring"; + description = "This FIFO holds most recent amplitude values from DSP Monit. chain"; + flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; + flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; + + field { + name = "Channel 0 Amplitude"; + prefix = "amp_ch0"; + type = SLV; + size = 32; + }; + + field { + name = "Channel 1 Amplitude"; + prefix = "amp_ch1"; + type = SLV; + size = 32; + }; + + field { + name = "Channel 2 Amplitude"; + prefix = "amp_ch2"; + type = SLV; + size = 32; + }; + + field { + name = "Channel 3 Amplitude"; + prefix = "amp_ch3"; + type = SLV; + size = 32; + }; + + }; + + fifo_reg { + size = 16; + direction = CORE_TO_BUS; + prefix = "posfifo_monit"; + name = "POS FIFO Monitoring"; + description = "This FIFO holds most recent position values from DSP Monit. chain"; + flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; + flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; + + field { + name = "Channel X Position"; + prefix = "pos_x"; + type = SLV; + size = 32; + }; + + field { + name = "Channel Y Position"; + prefix = "pos_y"; + type = SLV; + size = 32; + }; + + field { + name = "Channel Q Position"; + prefix = "pos_q"; + type = SLV; + size = 32; + }; + + field { + name = "Channel Sum Position"; + prefix = "pos_sum"; + type = SLV; + size = 32; + }; + + }; + ---------------------------------------------------------------------------- -- Monit. 1 Amplitude/Position Values New Interface ---------------------------------------------------------------------------- diff --git a/hdl/modules/wb_position_calc/xwb_position_calc_core.vhd b/hdl/modules/wb_position_calc/xwb_position_calc_core.vhd old mode 100755 new mode 100644 index 763dbc02..3da92f14 --- a/hdl/modules/wb_position_calc/xwb_position_calc_core.vhd +++ b/hdl/modules/wb_position_calc/xwb_position_calc_core.vhd @@ -86,7 +86,10 @@ generic g_fofb_cordic_ratio : positive := 4; -- width of K constants - g_k_width : natural := 16; + g_k_width : natural := 25; + + -- width of offset constants + g_offset_width : natural := 32; --width for IQ output g_IQ_width : natural := 32; diff --git a/hdl/sim/regs/wb_orbit_intlk_regs.vh b/hdl/sim/regs/wb_orbit_intlk_regs.vh index b4af00f8..c71f4863 100644 --- a/hdl/sim/regs/wb_orbit_intlk_regs.vh +++ b/hdl/sim/regs/wb_orbit_intlk_regs.vh @@ -1,4 +1,4 @@ -`define ADDR_ORBIT_INTLK_CTRL 5'h0 +`define ADDR_ORBIT_INTLK_CTRL 6'h0 `define ORBIT_INTLK_CTRL_EN_OFFSET 0 `define ORBIT_INTLK_CTRL_EN 32'h00000001 `define ORBIT_INTLK_CTRL_CLR_OFFSET 1 @@ -15,7 +15,7 @@ `define ORBIT_INTLK_CTRL_ANG_CLR 32'h00000040 `define ORBIT_INTLK_CTRL_RESERVED_OFFSET 7 `define ORBIT_INTLK_CTRL_RESERVED 32'h7fffff80 -`define ADDR_ORBIT_INTLK_STS 5'h4 +`define ADDR_ORBIT_INTLK_STS 6'h4 `define ORBIT_INTLK_STS_TRANS_BIGGER_X_OFFSET 0 `define ORBIT_INTLK_STS_TRANS_BIGGER_X 32'h00000001 `define ORBIT_INTLK_STS_TRANS_BIGGER_Y_OFFSET 1 @@ -44,14 +44,46 @@ `define ORBIT_INTLK_STS_ANG_BIGGER 32'h00001000 `define ORBIT_INTLK_STS_ANG_BIGGER_LTC_OFFSET 13 `define ORBIT_INTLK_STS_ANG_BIGGER_LTC 32'h00002000 -`define ORBIT_INTLK_STS_INTLK_BIGGER_OFFSET 14 -`define ORBIT_INTLK_STS_INTLK_BIGGER 32'h00004000 -`define ORBIT_INTLK_STS_INTLK_BIGGER_LTC_OFFSET 15 -`define ORBIT_INTLK_STS_INTLK_BIGGER_LTC 32'h00008000 -`define ORBIT_INTLK_STS_RESERVED_OFFSET 16 -`define ORBIT_INTLK_STS_RESERVED 32'hffff0000 -`define ADDR_ORBIT_INTLK_MIN_SUM 5'h8 -`define ADDR_ORBIT_INTLK_TRANS_MAX_X 5'hc -`define ADDR_ORBIT_INTLK_TRANS_MAX_Y 5'h10 -`define ADDR_ORBIT_INTLK_ANG_MAX_X 5'h14 -`define ADDR_ORBIT_INTLK_ANG_MAX_Y 5'h18 +`define ORBIT_INTLK_STS_INTLK_OFFSET 14 +`define ORBIT_INTLK_STS_INTLK 32'h00004000 +`define ORBIT_INTLK_STS_INTLK_LTC_OFFSET 15 +`define ORBIT_INTLK_STS_INTLK_LTC 32'h00008000 +`define ORBIT_INTLK_STS_TRANS_SMALLER_X_OFFSET 16 +`define ORBIT_INTLK_STS_TRANS_SMALLER_X 32'h00010000 +`define ORBIT_INTLK_STS_TRANS_SMALLER_Y_OFFSET 17 +`define ORBIT_INTLK_STS_TRANS_SMALLER_Y 32'h00020000 +`define ORBIT_INTLK_STS_TRANS_SMALLER_LTC_X_OFFSET 18 +`define ORBIT_INTLK_STS_TRANS_SMALLER_LTC_X 32'h00040000 +`define ORBIT_INTLK_STS_TRANS_SMALLER_LTC_Y_OFFSET 19 +`define ORBIT_INTLK_STS_TRANS_SMALLER_LTC_Y 32'h00080000 +`define ORBIT_INTLK_STS_TRANS_SMALLER_ANY_OFFSET 20 +`define ORBIT_INTLK_STS_TRANS_SMALLER_ANY 32'h00100000 +`define ORBIT_INTLK_STS_TRANS_SMALLER_OFFSET 21 +`define ORBIT_INTLK_STS_TRANS_SMALLER 32'h00200000 +`define ORBIT_INTLK_STS_TRANS_SMALLER_LTC_OFFSET 22 +`define ORBIT_INTLK_STS_TRANS_SMALLER_LTC 32'h00400000 +`define ORBIT_INTLK_STS_ANG_SMALLER_X_OFFSET 23 +`define ORBIT_INTLK_STS_ANG_SMALLER_X 32'h00800000 +`define ORBIT_INTLK_STS_ANG_SMALLER_Y_OFFSET 24 +`define ORBIT_INTLK_STS_ANG_SMALLER_Y 32'h01000000 +`define ORBIT_INTLK_STS_ANG_SMALLER_LTC_X_OFFSET 25 +`define ORBIT_INTLK_STS_ANG_SMALLER_LTC_X 32'h02000000 +`define ORBIT_INTLK_STS_ANG_SMALLER_LTC_Y_OFFSET 26 +`define ORBIT_INTLK_STS_ANG_SMALLER_LTC_Y 32'h04000000 +`define ORBIT_INTLK_STS_ANG_SMALLER_ANY_OFFSET 27 +`define ORBIT_INTLK_STS_ANG_SMALLER_ANY 32'h08000000 +`define ORBIT_INTLK_STS_ANG_SMALLER_OFFSET 28 +`define ORBIT_INTLK_STS_ANG_SMALLER 32'h10000000 +`define ORBIT_INTLK_STS_ANG_SMALLER_LTC_OFFSET 29 +`define ORBIT_INTLK_STS_ANG_SMALLER_LTC 32'h20000000 +`define ORBIT_INTLK_STS_RESERVED_OFFSET 30 +`define ORBIT_INTLK_STS_RESERVED 32'hc0000000 +`define ADDR_ORBIT_INTLK_MIN_SUM 6'h8 +`define ADDR_ORBIT_INTLK_TRANS_MAX_X 6'hc +`define ADDR_ORBIT_INTLK_TRANS_MAX_Y 6'h10 +`define ADDR_ORBIT_INTLK_ANG_MAX_X 6'h14 +`define ADDR_ORBIT_INTLK_ANG_MAX_Y 6'h18 +`define ADDR_ORBIT_INTLK_TRANS_MIN_X 6'h1c +`define ADDR_ORBIT_INTLK_TRANS_MIN_Y 6'h20 +`define ADDR_ORBIT_INTLK_ANG_MIN_X 6'h24 +`define ADDR_ORBIT_INTLK_ANG_MIN_Y 6'h28 diff --git a/hdl/sim/regs/wb_pos_calc_regs.vh b/hdl/sim/regs/wb_pos_calc_regs.vh index 879049a1..8db900d1 100644 --- a/hdl/sim/regs/wb_pos_calc_regs.vh +++ b/hdl/sim/regs/wb_pos_calc_regs.vh @@ -1,276 +1,286 @@ -`define ADDR_POS_CALC_DS_TBT_THRES 9'h0 +`define POS_CALC_SIZE 284 +`define ADDR_POS_CALC_DS_TBT_THRES 'h0 `define POS_CALC_DS_TBT_THRES_VAL_OFFSET 0 -`define POS_CALC_DS_TBT_THRES_VAL 32'h03ffffff +`define POS_CALC_DS_TBT_THRES_VAL 'h3ffffff `define POS_CALC_DS_TBT_THRES_RESERVED_OFFSET 26 -`define POS_CALC_DS_TBT_THRES_RESERVED 32'hfc000000 -`define ADDR_POS_CALC_DS_FOFB_THRES 9'h4 +`define POS_CALC_DS_TBT_THRES_RESERVED 'hfc000000 +`define ADDR_POS_CALC_DS_FOFB_THRES 'h4 `define POS_CALC_DS_FOFB_THRES_VAL_OFFSET 0 -`define POS_CALC_DS_FOFB_THRES_VAL 32'h03ffffff +`define POS_CALC_DS_FOFB_THRES_VAL 'h3ffffff `define POS_CALC_DS_FOFB_THRES_RESERVED_OFFSET 26 -`define POS_CALC_DS_FOFB_THRES_RESERVED 32'hfc000000 -`define ADDR_POS_CALC_DS_MONIT_THRES 9'h8 +`define POS_CALC_DS_FOFB_THRES_RESERVED 'hfc000000 +`define ADDR_POS_CALC_DS_MONIT_THRES 'h8 `define POS_CALC_DS_MONIT_THRES_VAL_OFFSET 0 -`define POS_CALC_DS_MONIT_THRES_VAL 32'h03ffffff +`define POS_CALC_DS_MONIT_THRES_VAL 'h3ffffff `define POS_CALC_DS_MONIT_THRES_RESERVED_OFFSET 26 -`define POS_CALC_DS_MONIT_THRES_RESERVED 32'hfc000000 -`define ADDR_POS_CALC_KX 9'hc +`define POS_CALC_DS_MONIT_THRES_RESERVED 'hfc000000 +`define ADDR_POS_CALC_KX 'hc `define POS_CALC_KX_VAL_OFFSET 0 -`define POS_CALC_KX_VAL 32'h01ffffff +`define POS_CALC_KX_VAL 'h1ffffff `define POS_CALC_KX_RESERVED_OFFSET 25 -`define POS_CALC_KX_RESERVED 32'hfe000000 -`define ADDR_POS_CALC_KY 9'h10 +`define POS_CALC_KX_RESERVED 'hfe000000 +`define ADDR_POS_CALC_KY 'h10 `define POS_CALC_KY_VAL_OFFSET 0 -`define POS_CALC_KY_VAL 32'h01ffffff +`define POS_CALC_KY_VAL 'h1ffffff `define POS_CALC_KY_RESERVED_OFFSET 25 -`define POS_CALC_KY_RESERVED 32'hfe000000 -`define ADDR_POS_CALC_KSUM 9'h14 +`define POS_CALC_KY_RESERVED 'hfe000000 +`define ADDR_POS_CALC_KSUM 'h14 `define POS_CALC_KSUM_VAL_OFFSET 0 -`define POS_CALC_KSUM_VAL 32'h01ffffff +`define POS_CALC_KSUM_VAL 'h1ffffff `define POS_CALC_KSUM_RESERVED_OFFSET 25 -`define POS_CALC_KSUM_RESERVED 32'hfe000000 -`define ADDR_POS_CALC_DSP_CTNR_TBT 9'h18 +`define POS_CALC_KSUM_RESERVED 'hfe000000 +`define ADDR_POS_CALC_DSP_CTNR_TBT 'h18 `define POS_CALC_DSP_CTNR_TBT_CH01_OFFSET 0 -`define POS_CALC_DSP_CTNR_TBT_CH01 32'h0000ffff +`define POS_CALC_DSP_CTNR_TBT_CH01 'hffff `define POS_CALC_DSP_CTNR_TBT_CH23_OFFSET 16 -`define POS_CALC_DSP_CTNR_TBT_CH23 32'hffff0000 -`define ADDR_POS_CALC_DSP_CTNR_FOFB 9'h1c +`define POS_CALC_DSP_CTNR_TBT_CH23 'hffff0000 +`define ADDR_POS_CALC_DSP_CTNR_FOFB 'h1c `define POS_CALC_DSP_CTNR_FOFB_CH01_OFFSET 0 -`define POS_CALC_DSP_CTNR_FOFB_CH01 32'h0000ffff +`define POS_CALC_DSP_CTNR_FOFB_CH01 'hffff `define POS_CALC_DSP_CTNR_FOFB_CH23_OFFSET 16 -`define POS_CALC_DSP_CTNR_FOFB_CH23 32'hffff0000 -`define ADDR_POS_CALC_DSP_CTNR1_MONIT 9'h20 +`define POS_CALC_DSP_CTNR_FOFB_CH23 'hffff0000 +`define ADDR_POS_CALC_DSP_CTNR1_MONIT 'h20 `define POS_CALC_DSP_CTNR1_MONIT_CIC_OFFSET 0 -`define POS_CALC_DSP_CTNR1_MONIT_CIC 32'h0000ffff +`define POS_CALC_DSP_CTNR1_MONIT_CIC 'hffff `define POS_CALC_DSP_CTNR1_MONIT_CFIR_OFFSET 16 -`define POS_CALC_DSP_CTNR1_MONIT_CFIR 32'hffff0000 -`define ADDR_POS_CALC_DSP_CTNR2_MONIT 9'h24 +`define POS_CALC_DSP_CTNR1_MONIT_CFIR 'hffff0000 +`define ADDR_POS_CALC_DSP_CTNR2_MONIT 'h24 `define POS_CALC_DSP_CTNR2_MONIT_PFIR_OFFSET 0 -`define POS_CALC_DSP_CTNR2_MONIT_PFIR 32'h0000ffff +`define POS_CALC_DSP_CTNR2_MONIT_PFIR 'hffff `define POS_CALC_DSP_CTNR2_MONIT_FIR_01_OFFSET 16 -`define POS_CALC_DSP_CTNR2_MONIT_FIR_01 32'hffff0000 -`define ADDR_POS_CALC_DSP_ERR_CLR 9'h28 +`define POS_CALC_DSP_CTNR2_MONIT_FIR_01 'hffff0000 +`define ADDR_POS_CALC_DSP_ERR_CLR 'h28 `define POS_CALC_DSP_ERR_CLR_TBT_OFFSET 0 -`define POS_CALC_DSP_ERR_CLR_TBT 32'h00000001 +`define POS_CALC_DSP_ERR_CLR_TBT 'h1 `define POS_CALC_DSP_ERR_CLR_FOFB_OFFSET 1 -`define POS_CALC_DSP_ERR_CLR_FOFB 32'h00000002 +`define POS_CALC_DSP_ERR_CLR_FOFB 'h2 `define POS_CALC_DSP_ERR_CLR_MONIT_PART1_OFFSET 2 -`define POS_CALC_DSP_ERR_CLR_MONIT_PART1 32'h00000004 +`define POS_CALC_DSP_ERR_CLR_MONIT_PART1 'h4 `define POS_CALC_DSP_ERR_CLR_MONIT_PART2_OFFSET 3 -`define POS_CALC_DSP_ERR_CLR_MONIT_PART2 32'h00000008 -`define ADDR_POS_CALC_DDS_CFG 9'h2c +`define POS_CALC_DSP_ERR_CLR_MONIT_PART2 'h8 +`define ADDR_POS_CALC_DDS_CFG 'h2c `define POS_CALC_DDS_CFG_VALID_CH0_OFFSET 0 -`define POS_CALC_DDS_CFG_VALID_CH0 32'h00000001 +`define POS_CALC_DDS_CFG_VALID_CH0 'h1 `define POS_CALC_DDS_CFG_TEST_DATA_OFFSET 1 -`define POS_CALC_DDS_CFG_TEST_DATA 32'h00000002 +`define POS_CALC_DDS_CFG_TEST_DATA 'h2 `define POS_CALC_DDS_CFG_RESERVED_CH0_OFFSET 2 -`define POS_CALC_DDS_CFG_RESERVED_CH0 32'h000000fc +`define POS_CALC_DDS_CFG_RESERVED_CH0 'hfc `define POS_CALC_DDS_CFG_VALID_CH1_OFFSET 8 -`define POS_CALC_DDS_CFG_VALID_CH1 32'h00000100 +`define POS_CALC_DDS_CFG_VALID_CH1 'h100 `define POS_CALC_DDS_CFG_RESERVED_CH1_OFFSET 9 -`define POS_CALC_DDS_CFG_RESERVED_CH1 32'h0000fe00 +`define POS_CALC_DDS_CFG_RESERVED_CH1 'hfe00 `define POS_CALC_DDS_CFG_VALID_CH2_OFFSET 16 -`define POS_CALC_DDS_CFG_VALID_CH2 32'h00010000 +`define POS_CALC_DDS_CFG_VALID_CH2 'h10000 `define POS_CALC_DDS_CFG_RESERVED_CH2_OFFSET 17 -`define POS_CALC_DDS_CFG_RESERVED_CH2 32'h00fe0000 +`define POS_CALC_DDS_CFG_RESERVED_CH2 'hfe0000 `define POS_CALC_DDS_CFG_VALID_CH3_OFFSET 24 -`define POS_CALC_DDS_CFG_VALID_CH3 32'h01000000 +`define POS_CALC_DDS_CFG_VALID_CH3 'h1000000 `define POS_CALC_DDS_CFG_RESERVED_CH3_OFFSET 25 -`define POS_CALC_DDS_CFG_RESERVED_CH3 32'hfe000000 -`define ADDR_POS_CALC_DDS_PINC_CH0 9'h30 +`define POS_CALC_DDS_CFG_RESERVED_CH3 'hfe000000 +`define ADDR_POS_CALC_DDS_PINC_CH0 'h30 `define POS_CALC_DDS_PINC_CH0_VAL_OFFSET 0 -`define POS_CALC_DDS_PINC_CH0_VAL 32'h3fffffff +`define POS_CALC_DDS_PINC_CH0_VAL 'h3fffffff `define POS_CALC_DDS_PINC_CH0_RESERVED_OFFSET 30 -`define POS_CALC_DDS_PINC_CH0_RESERVED 32'hc0000000 -`define ADDR_POS_CALC_DDS_PINC_CH1 9'h34 +`define POS_CALC_DDS_PINC_CH0_RESERVED 'hc0000000 +`define ADDR_POS_CALC_DDS_PINC_CH1 'h34 `define POS_CALC_DDS_PINC_CH1_VAL_OFFSET 0 -`define POS_CALC_DDS_PINC_CH1_VAL 32'h3fffffff +`define POS_CALC_DDS_PINC_CH1_VAL 'h3fffffff `define POS_CALC_DDS_PINC_CH1_RESERVED_OFFSET 30 -`define POS_CALC_DDS_PINC_CH1_RESERVED 32'hc0000000 -`define ADDR_POS_CALC_DDS_PINC_CH2 9'h38 +`define POS_CALC_DDS_PINC_CH1_RESERVED 'hc0000000 +`define ADDR_POS_CALC_DDS_PINC_CH2 'h38 `define POS_CALC_DDS_PINC_CH2_VAL_OFFSET 0 -`define POS_CALC_DDS_PINC_CH2_VAL 32'h3fffffff +`define POS_CALC_DDS_PINC_CH2_VAL 'h3fffffff `define POS_CALC_DDS_PINC_CH2_RESERVED_OFFSET 30 -`define POS_CALC_DDS_PINC_CH2_RESERVED 32'hc0000000 -`define ADDR_POS_CALC_DDS_PINC_CH3 9'h3c +`define POS_CALC_DDS_PINC_CH2_RESERVED 'hc0000000 +`define ADDR_POS_CALC_DDS_PINC_CH3 'h3c `define POS_CALC_DDS_PINC_CH3_VAL_OFFSET 0 -`define POS_CALC_DDS_PINC_CH3_VAL 32'h3fffffff +`define POS_CALC_DDS_PINC_CH3_VAL 'h3fffffff `define POS_CALC_DDS_PINC_CH3_RESERVED_OFFSET 30 -`define POS_CALC_DDS_PINC_CH3_RESERVED 32'hc0000000 -`define ADDR_POS_CALC_DDS_POFF_CH0 9'h40 +`define POS_CALC_DDS_PINC_CH3_RESERVED 'hc0000000 +`define ADDR_POS_CALC_DDS_POFF_CH0 'h40 `define POS_CALC_DDS_POFF_CH0_VAL_OFFSET 0 -`define POS_CALC_DDS_POFF_CH0_VAL 32'h3fffffff +`define POS_CALC_DDS_POFF_CH0_VAL 'h3fffffff `define POS_CALC_DDS_POFF_CH0_RESERVED_OFFSET 30 -`define POS_CALC_DDS_POFF_CH0_RESERVED 32'hc0000000 -`define ADDR_POS_CALC_DDS_POFF_CH1 9'h44 +`define POS_CALC_DDS_POFF_CH0_RESERVED 'hc0000000 +`define ADDR_POS_CALC_DDS_POFF_CH1 'h44 `define POS_CALC_DDS_POFF_CH1_VAL_OFFSET 0 -`define POS_CALC_DDS_POFF_CH1_VAL 32'h3fffffff +`define POS_CALC_DDS_POFF_CH1_VAL 'h3fffffff `define POS_CALC_DDS_POFF_CH1_RESERVED_OFFSET 30 -`define POS_CALC_DDS_POFF_CH1_RESERVED 32'hc0000000 -`define ADDR_POS_CALC_DDS_POFF_CH2 9'h48 +`define POS_CALC_DDS_POFF_CH1_RESERVED 'hc0000000 +`define ADDR_POS_CALC_DDS_POFF_CH2 'h48 `define POS_CALC_DDS_POFF_CH2_VAL_OFFSET 0 -`define POS_CALC_DDS_POFF_CH2_VAL 32'h3fffffff +`define POS_CALC_DDS_POFF_CH2_VAL 'h3fffffff `define POS_CALC_DDS_POFF_CH2_RESERVED_OFFSET 30 -`define POS_CALC_DDS_POFF_CH2_RESERVED 32'hc0000000 -`define ADDR_POS_CALC_DDS_POFF_CH3 9'h4c +`define POS_CALC_DDS_POFF_CH2_RESERVED 'hc0000000 +`define ADDR_POS_CALC_DDS_POFF_CH3 'h4c `define POS_CALC_DDS_POFF_CH3_VAL_OFFSET 0 -`define POS_CALC_DDS_POFF_CH3_VAL 32'h3fffffff +`define POS_CALC_DDS_POFF_CH3_VAL 'h3fffffff `define POS_CALC_DDS_POFF_CH3_RESERVED_OFFSET 30 -`define POS_CALC_DDS_POFF_CH3_RESERVED 32'hc0000000 -`define ADDR_POS_CALC_DSP_MONIT_AMP_CH0 9'h50 -`define ADDR_POS_CALC_DSP_MONIT_AMP_CH1 9'h54 -`define ADDR_POS_CALC_DSP_MONIT_AMP_CH2 9'h58 -`define ADDR_POS_CALC_DSP_MONIT_AMP_CH3 9'h5c -`define ADDR_POS_CALC_DSP_MONIT_POS_X 9'h60 -`define ADDR_POS_CALC_DSP_MONIT_POS_Y 9'h64 -`define ADDR_POS_CALC_DSP_MONIT_POS_Q 9'h68 -`define ADDR_POS_CALC_DSP_MONIT_POS_SUM 9'h6c -`define ADDR_POS_CALC_DSP_MONIT_UPDT 9'h70 -`define ADDR_POS_CALC_DSP_MONIT1_AMP_CH0 9'h74 -`define ADDR_POS_CALC_DSP_MONIT1_AMP_CH1 9'h78 -`define ADDR_POS_CALC_DSP_MONIT1_AMP_CH2 9'h7c -`define ADDR_POS_CALC_DSP_MONIT1_AMP_CH3 9'h80 -`define ADDR_POS_CALC_DSP_MONIT1_POS_X 9'h84 -`define ADDR_POS_CALC_DSP_MONIT1_POS_Y 9'h88 -`define ADDR_POS_CALC_DSP_MONIT1_POS_Q 9'h8c -`define ADDR_POS_CALC_DSP_MONIT1_POS_SUM 9'h90 -`define ADDR_POS_CALC_DSP_MONIT1_UPDT 9'h94 -`define ADDR_POS_CALC_AMPFIFO_MONIT_R0 9'h98 -`define POS_CALC_AMPFIFO_MONIT_R0_AMP_CH0_OFFSET 0 -`define POS_CALC_AMPFIFO_MONIT_R0_AMP_CH0 32'hffffffff -`define ADDR_POS_CALC_AMPFIFO_MONIT_R1 9'h9c -`define POS_CALC_AMPFIFO_MONIT_R1_AMP_CH1_OFFSET 0 -`define POS_CALC_AMPFIFO_MONIT_R1_AMP_CH1 32'hffffffff -`define ADDR_POS_CALC_AMPFIFO_MONIT_R2 9'ha0 -`define POS_CALC_AMPFIFO_MONIT_R2_AMP_CH2_OFFSET 0 -`define POS_CALC_AMPFIFO_MONIT_R2_AMP_CH2 32'hffffffff -`define ADDR_POS_CALC_AMPFIFO_MONIT_R3 9'ha4 -`define POS_CALC_AMPFIFO_MONIT_R3_AMP_CH3_OFFSET 0 -`define POS_CALC_AMPFIFO_MONIT_R3_AMP_CH3 32'hffffffff -`define ADDR_POS_CALC_AMPFIFO_MONIT_CSR 9'ha8 -`define POS_CALC_AMPFIFO_MONIT_CSR_FULL_OFFSET 16 -`define POS_CALC_AMPFIFO_MONIT_CSR_FULL 32'h00010000 -`define POS_CALC_AMPFIFO_MONIT_CSR_EMPTY_OFFSET 17 -`define POS_CALC_AMPFIFO_MONIT_CSR_EMPTY 32'h00020000 -`define POS_CALC_AMPFIFO_MONIT_CSR_USEDW_OFFSET 0 -`define POS_CALC_AMPFIFO_MONIT_CSR_USEDW 32'h0000000f -`define ADDR_POS_CALC_POSFIFO_MONIT_R0 9'hd8 -`define POS_CALC_POSFIFO_MONIT_R0_POS_X_OFFSET 0 -`define POS_CALC_POSFIFO_MONIT_R0_POS_X 32'hffffffff -`define ADDR_POS_CALC_POSFIFO_MONIT_R1 9'hb0 -`define POS_CALC_POSFIFO_MONIT_R1_POS_Y_OFFSET 0 -`define POS_CALC_POSFIFO_MONIT_R1_POS_Y 32'hffffffff -`define ADDR_POS_CALC_POSFIFO_MONIT_R2 9'hb4 -`define POS_CALC_POSFIFO_MONIT_R2_POS_Q_OFFSET 0 -`define POS_CALC_POSFIFO_MONIT_R2_POS_Q 32'hffffffff -`define ADDR_POS_CALC_POSFIFO_MONIT_R3 9'hb8 -`define POS_CALC_POSFIFO_MONIT_R3_POS_SUM_OFFSET 0 -`define POS_CALC_POSFIFO_MONIT_R3_POS_SUM 32'hffffffff -`define ADDR_POS_CALC_POSFIFO_MONIT_CSR 9'hbc -`define POS_CALC_POSFIFO_MONIT_CSR_FULL_OFFSET 16 -`define POS_CALC_POSFIFO_MONIT_CSR_FULL 32'h00010000 -`define POS_CALC_POSFIFO_MONIT_CSR_EMPTY_OFFSET 17 -`define POS_CALC_POSFIFO_MONIT_CSR_EMPTY 32'h00020000 -`define POS_CALC_POSFIFO_MONIT_CSR_USEDW_OFFSET 0 -`define POS_CALC_POSFIFO_MONIT_CSR_USEDW 32'h0000000f -`define ADDR_POS_CALC_AMPFIFO_MONIT1_R0 9'hc0 -`define POS_CALC_AMPFIFO_MONIT1_R0_AMP_CH0_OFFSET 0 -`define POS_CALC_AMPFIFO_MONIT1_R0_AMP_CH0 32'hffffffff -`define ADDR_POS_CALC_AMPFIFO_MONIT1_R1 9'hc4 -`define POS_CALC_AMPFIFO_MONIT1_R1_AMP_CH1_OFFSET 0 -`define POS_CALC_AMPFIFO_MONIT1_R1_AMP_CH1 32'hffffffff -`define ADDR_POS_CALC_AMPFIFO_MONIT1_R2 9'hc8 -`define POS_CALC_AMPFIFO_MONIT1_R2_AMP_CH2_OFFSET 0 -`define POS_CALC_AMPFIFO_MONIT1_R2_AMP_CH2 32'hffffffff -`define ADDR_POS_CALC_AMPFIFO_MONIT1_R3 9'hcc -`define POS_CALC_AMPFIFO_MONIT1_R3_AMP_CH3_OFFSET 0 -`define POS_CALC_AMPFIFO_MONIT1_R3_AMP_CH3 32'hffffffff -`define ADDR_POS_CALC_AMPFIFO_MONIT1_CSR 9'hd0 -`define POS_CALC_AMPFIFO_MONIT1_CSR_FULL_OFFSET 16 -`define POS_CALC_AMPFIFO_MONIT1_CSR_FULL 32'h00010000 -`define POS_CALC_AMPFIFO_MONIT1_CSR_EMPTY_OFFSET 17 -`define POS_CALC_AMPFIFO_MONIT1_CSR_EMPTY 32'h00020000 -`define POS_CALC_AMPFIFO_MONIT1_CSR_USEDW_OFFSET 0 -`define POS_CALC_AMPFIFO_MONIT1_CSR_USEDW 32'h0000000f -`define ADDR_POS_CALC_POSFIFO_MONIT1_R0 9'hd4 -`define POS_CALC_POSFIFO_MONIT1_R0_POS_X_OFFSET 0 -`define POS_CALC_POSFIFO_MONIT1_R0_POS_X 32'hffffffff -`define ADDR_POS_CALC_POSFIFO_MONIT1_R1 9'hd8 -`define POS_CALC_POSFIFO_MONIT1_R1_POS_Y_OFFSET 0 -`define POS_CALC_POSFIFO_MONIT1_R1_POS_Y 32'hffffffff -`define ADDR_POS_CALC_POSFIFO_MONIT1_R2 9'hdc -`define POS_CALC_POSFIFO_MONIT1_R2_POS_Q_OFFSET 0 -`define POS_CALC_POSFIFO_MONIT1_R2_POS_Q 32'hffffffff -`define ADDR_POS_CALC_POSFIFO_MONIT1_R3 9'he0 -`define POS_CALC_POSFIFO_MONIT1_R3_POS_SUM_OFFSET 0 -`define POS_CALC_POSFIFO_MONIT1_R3_POS_SUM 32'hffffffff -`define ADDR_POS_CALC_POSFIFO_MONIT1_CSR 9'he4 -`define POS_CALC_POSFIFO_MONIT1_CSR_FULL_OFFSET 16 -`define POS_CALC_POSFIFO_MONIT1_CSR_FULL 32'h00010000 -`define POS_CALC_POSFIFO_MONIT1_CSR_EMPTY_OFFSET 17 -`define POS_CALC_POSFIFO_MONIT1_CSR_EMPTY 32'h00020000 -`define POS_CALC_POSFIFO_MONIT1_CSR_USEDW_OFFSET 0 -`define POS_CALC_POSFIFO_MONIT1_CSR_USEDW 32'h0000000f -`define ADDR_POS_CALC_SW_TAG 9'he8 +`define POS_CALC_DDS_POFF_CH3_RESERVED 'hc0000000 +`define ADDR_POS_CALC_DSP_MONIT_AMP_CH0 'h50 +`define ADDR_POS_CALC_DSP_MONIT_AMP_CH1 'h54 +`define ADDR_POS_CALC_DSP_MONIT_AMP_CH2 'h58 +`define ADDR_POS_CALC_DSP_MONIT_AMP_CH3 'h5c +`define ADDR_POS_CALC_DSP_MONIT_POS_X 'h60 +`define ADDR_POS_CALC_DSP_MONIT_POS_Y 'h64 +`define ADDR_POS_CALC_DSP_MONIT_POS_Q 'h68 +`define ADDR_POS_CALC_DSP_MONIT_POS_SUM 'h6c +`define ADDR_POS_CALC_DSP_MONIT_UPDT 'h70 +`define ADDR_POS_CALC_DSP_MONIT1_AMP_CH0 'h74 +`define ADDR_POS_CALC_DSP_MONIT1_AMP_CH1 'h78 +`define ADDR_POS_CALC_DSP_MONIT1_AMP_CH2 'h7c +`define ADDR_POS_CALC_DSP_MONIT1_AMP_CH3 'h80 +`define ADDR_POS_CALC_DSP_MONIT1_POS_X 'h84 +`define ADDR_POS_CALC_DSP_MONIT1_POS_Y 'h88 +`define ADDR_POS_CALC_DSP_MONIT1_POS_Q 'h8c +`define ADDR_POS_CALC_DSP_MONIT1_POS_SUM 'h90 +`define ADDR_POS_CALC_DSP_MONIT1_UPDT 'h94 +`define ADDR_POS_CALC_AMPFIFO_MONIT 'h98 +`define POS_CALC_AMPFIFO_MONIT_SIZE 20 +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0 'h98 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0_AMP_CH0_OFFSET 0 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0_AMP_CH0 'hffffffff +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1 'h9c +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1_AMP_CH1_OFFSET 0 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1_AMP_CH1 'hffffffff +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2 'ha0 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2_AMP_CH2_OFFSET 0 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2_AMP_CH2 'hffffffff +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3 'ha4 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3_AMP_CH3_OFFSET 0 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3_AMP_CH3 'hffffffff +`define ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR 'ha8 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_FULL_OFFSET 16 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_FULL 'h10000 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_EMPTY_OFFSET 17 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_EMPTY 'h20000 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_COUNT_OFFSET 0 +`define POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_COUNT 'hf +`define ADDR_POS_CALC_POSFIFO_MONIT 'hac +`define POS_CALC_POSFIFO_MONIT_SIZE 20 +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0 'hac +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0_POS_X_OFFSET 0 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0_POS_X 'hffffffff +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1 'hb0 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1_POS_Y_OFFSET 0 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1_POS_Y 'hffffffff +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2 'hb4 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2_POS_Q_OFFSET 0 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2_POS_Q 'hffffffff +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3 'hb8 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3_POS_SUM_OFFSET 0 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3_POS_SUM 'hffffffff +`define ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR 'hbc +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_FULL_OFFSET 16 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_FULL 'h10000 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_EMPTY_OFFSET 17 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_EMPTY 'h20000 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_COUNT_OFFSET 0 +`define POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_COUNT 'hf +`define ADDR_POS_CALC_AMPFIFO_MONIT1 'hc0 +`define POS_CALC_AMPFIFO_MONIT1_SIZE 20 +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0 'hc0 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0_AMP_CH0_OFFSET 0 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0_AMP_CH0 'hffffffff +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1 'hc4 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1_AMP_CH1_OFFSET 0 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1_AMP_CH1 'hffffffff +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2 'hc8 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2_AMP_CH2_OFFSET 0 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2_AMP_CH2 'hffffffff +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3 'hcc +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3_AMP_CH3_OFFSET 0 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3_AMP_CH3 'hffffffff +`define ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR 'hd0 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_FULL_OFFSET 16 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_FULL 'h10000 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_EMPTY_OFFSET 17 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_EMPTY 'h20000 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_COUNT_OFFSET 0 +`define POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_COUNT 'hf +`define ADDR_POS_CALC_POSFIFO_MONIT1 'hd4 +`define POS_CALC_POSFIFO_MONIT1_SIZE 20 +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0 'hd4 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0_POS_X_OFFSET 0 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0_POS_X 'hffffffff +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1 'hd8 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1_POS_Y_OFFSET 0 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1_POS_Y 'hffffffff +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2 'hdc +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2_POS_Q_OFFSET 0 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2_POS_Q 'hffffffff +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3 'he0 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3_POS_SUM_OFFSET 0 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3_POS_SUM 'hffffffff +`define ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR 'he4 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_FULL_OFFSET 16 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_FULL 'h10000 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_EMPTY_OFFSET 17 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_EMPTY 'h20000 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_COUNT_OFFSET 0 +`define POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_COUNT 'hf +`define ADDR_POS_CALC_SW_TAG 'he8 `define POS_CALC_SW_TAG_EN_OFFSET 0 -`define POS_CALC_SW_TAG_EN 32'h00000001 +`define POS_CALC_SW_TAG_EN 'h1 `define POS_CALC_SW_TAG_DESYNC_CNT_RST_OFFSET 8 -`define POS_CALC_SW_TAG_DESYNC_CNT_RST 32'h00000100 +`define POS_CALC_SW_TAG_DESYNC_CNT_RST 'h100 `define POS_CALC_SW_TAG_DESYNC_CNT_OFFSET 9 -`define POS_CALC_SW_TAG_DESYNC_CNT 32'h007ffe00 -`define ADDR_POS_CALC_SW_DATA_MASK 9'hec +`define POS_CALC_SW_TAG_DESYNC_CNT 'h7ffe00 +`define ADDR_POS_CALC_SW_DATA_MASK 'hec `define POS_CALC_SW_DATA_MASK_EN_OFFSET 0 -`define POS_CALC_SW_DATA_MASK_EN 32'h00000001 +`define POS_CALC_SW_DATA_MASK_EN 'h1 `define POS_CALC_SW_DATA_MASK_SAMPLES_OFFSET 1 -`define POS_CALC_SW_DATA_MASK_SAMPLES 32'h0001fffe -`define ADDR_POS_CALC_TBT_TAG 9'hf0 +`define POS_CALC_SW_DATA_MASK_SAMPLES 'h1fffe +`define ADDR_POS_CALC_TBT_TAG 'hf0 `define POS_CALC_TBT_TAG_EN_OFFSET 0 -`define POS_CALC_TBT_TAG_EN 32'h00000001 +`define POS_CALC_TBT_TAG_EN 'h1 `define POS_CALC_TBT_TAG_DLY_OFFSET 1 -`define POS_CALC_TBT_TAG_DLY 32'h0001fffe +`define POS_CALC_TBT_TAG_DLY 'h1fffe `define POS_CALC_TBT_TAG_DESYNC_CNT_RST_OFFSET 17 -`define POS_CALC_TBT_TAG_DESYNC_CNT_RST 32'h00020000 +`define POS_CALC_TBT_TAG_DESYNC_CNT_RST 'h20000 `define POS_CALC_TBT_TAG_DESYNC_CNT_OFFSET 18 -`define POS_CALC_TBT_TAG_DESYNC_CNT 32'hfffc0000 -`define ADDR_POS_CALC_TBT_DATA_MASK_CTL 9'hf4 +`define POS_CALC_TBT_TAG_DESYNC_CNT 'hfffc0000 +`define ADDR_POS_CALC_TBT_DATA_MASK_CTL 'hf4 `define POS_CALC_TBT_DATA_MASK_CTL_EN_OFFSET 0 -`define POS_CALC_TBT_DATA_MASK_CTL_EN 32'h00000001 -`define ADDR_POS_CALC_TBT_DATA_MASK_SAMPLES 9'hf8 +`define POS_CALC_TBT_DATA_MASK_CTL_EN 'h1 +`define ADDR_POS_CALC_TBT_DATA_MASK_SAMPLES 'hf8 `define POS_CALC_TBT_DATA_MASK_SAMPLES_BEG_OFFSET 0 -`define POS_CALC_TBT_DATA_MASK_SAMPLES_BEG 32'h0000ffff +`define POS_CALC_TBT_DATA_MASK_SAMPLES_BEG 'hffff `define POS_CALC_TBT_DATA_MASK_SAMPLES_END_OFFSET 16 -`define POS_CALC_TBT_DATA_MASK_SAMPLES_END 32'hffff0000 -`define ADDR_POS_CALC_MONIT1_TAG 9'hfc +`define POS_CALC_TBT_DATA_MASK_SAMPLES_END 'hffff0000 +`define ADDR_POS_CALC_MONIT1_TAG 'hfc `define POS_CALC_MONIT1_TAG_EN_OFFSET 0 -`define POS_CALC_MONIT1_TAG_EN 32'h00000001 +`define POS_CALC_MONIT1_TAG_EN 'h1 `define POS_CALC_MONIT1_TAG_DLY_OFFSET 1 -`define POS_CALC_MONIT1_TAG_DLY 32'h0001fffe +`define POS_CALC_MONIT1_TAG_DLY 'h1fffe `define POS_CALC_MONIT1_TAG_DESYNC_CNT_RST_OFFSET 17 -`define POS_CALC_MONIT1_TAG_DESYNC_CNT_RST 32'h00020000 +`define POS_CALC_MONIT1_TAG_DESYNC_CNT_RST 'h20000 `define POS_CALC_MONIT1_TAG_DESYNC_CNT_OFFSET 18 -`define POS_CALC_MONIT1_TAG_DESYNC_CNT 32'hfffc0000 -`define ADDR_POS_CALC_MONIT1_DATA_MASK_CTL 9'h100 +`define POS_CALC_MONIT1_TAG_DESYNC_CNT 'hfffc0000 +`define ADDR_POS_CALC_MONIT1_DATA_MASK_CTL 'h100 `define POS_CALC_MONIT1_DATA_MASK_CTL_EN_OFFSET 0 -`define POS_CALC_MONIT1_DATA_MASK_CTL_EN 32'h00000001 -`define ADDR_POS_CALC_MONIT1_DATA_MASK_SAMPLES 9'h104 +`define POS_CALC_MONIT1_DATA_MASK_CTL_EN 'h1 +`define ADDR_POS_CALC_MONIT1_DATA_MASK_SAMPLES 'h104 `define POS_CALC_MONIT1_DATA_MASK_SAMPLES_BEG_OFFSET 0 -`define POS_CALC_MONIT1_DATA_MASK_SAMPLES_BEG 32'h0000ffff +`define POS_CALC_MONIT1_DATA_MASK_SAMPLES_BEG 'hffff `define POS_CALC_MONIT1_DATA_MASK_SAMPLES_END_OFFSET 16 -`define POS_CALC_MONIT1_DATA_MASK_SAMPLES_END 32'hffff0000 -`define ADDR_POS_CALC_MONIT_TAG 9'h108 +`define POS_CALC_MONIT1_DATA_MASK_SAMPLES_END 'hffff0000 +`define ADDR_POS_CALC_MONIT_TAG 'h108 `define POS_CALC_MONIT_TAG_EN_OFFSET 0 -`define POS_CALC_MONIT_TAG_EN 32'h00000001 +`define POS_CALC_MONIT_TAG_EN 'h1 `define POS_CALC_MONIT_TAG_DLY_OFFSET 1 -`define POS_CALC_MONIT_TAG_DLY 32'h0001fffe +`define POS_CALC_MONIT_TAG_DLY 'h1fffe `define POS_CALC_MONIT_TAG_DESYNC_CNT_RST_OFFSET 17 -`define POS_CALC_MONIT_TAG_DESYNC_CNT_RST 32'h00020000 +`define POS_CALC_MONIT_TAG_DESYNC_CNT_RST 'h20000 `define POS_CALC_MONIT_TAG_DESYNC_CNT_OFFSET 18 -`define POS_CALC_MONIT_TAG_DESYNC_CNT 32'hfffc0000 -`define ADDR_POS_CALC_MONIT_DATA_MASK_CTL 9'h10c +`define POS_CALC_MONIT_TAG_DESYNC_CNT 'hfffc0000 +`define ADDR_POS_CALC_MONIT_DATA_MASK_CTL 'h10c `define POS_CALC_MONIT_DATA_MASK_CTL_EN_OFFSET 0 -`define POS_CALC_MONIT_DATA_MASK_CTL_EN 32'h00000001 -`define ADDR_POS_CALC_MONIT_DATA_MASK_SAMPLES 9'h110 +`define POS_CALC_MONIT_DATA_MASK_CTL_EN 'h1 +`define ADDR_POS_CALC_MONIT_DATA_MASK_SAMPLES 'h110 `define POS_CALC_MONIT_DATA_MASK_SAMPLES_BEG_OFFSET 0 -`define POS_CALC_MONIT_DATA_MASK_SAMPLES_BEG 32'h0000ffff +`define POS_CALC_MONIT_DATA_MASK_SAMPLES_BEG 'hffff `define POS_CALC_MONIT_DATA_MASK_SAMPLES_END_OFFSET 16 -`define POS_CALC_MONIT_DATA_MASK_SAMPLES_END 32'hffff0000 - +`define POS_CALC_MONIT_DATA_MASK_SAMPLES_END 'hffff0000 +`define ADDR_POS_CALC_OFFSET_X 'h114 +`define ADDR_POS_CALC_OFFSET_Y 'h118 diff --git a/hdl/testbench/orbit_intlk/wave.do b/hdl/testbench/orbit_intlk/wave.do index 2d12a1e0..831ac540 100644 --- a/hdl/testbench/orbit_intlk/wave.do +++ b/hdl/testbench/orbit_intlk/wave.do @@ -45,16 +45,16 @@ add wave -noupdate /wb_orbit_intlk_tb/intlk_trans_bigger_x add wave -noupdate /wb_orbit_intlk_tb/intlk_trans_bigger_y add wave -noupdate /wb_orbit_intlk_tb/intlk_trans_bigger_ltc_x add wave -noupdate /wb_orbit_intlk_tb/intlk_trans_bigger_ltc_y +add wave -noupdate /wb_orbit_intlk_tb/intlk_trans_bigger_any +add wave -noupdate /wb_orbit_intlk_tb/intlk_trans_bigger_ltc add wave -noupdate /wb_orbit_intlk_tb/intlk_trans_bigger -add wave -noupdate /wb_orbit_intlk_tb/intlk_trans_ltc -add wave -noupdate /wb_orbit_intlk_tb/intlk_trans add wave -noupdate /wb_orbit_intlk_tb/intlk_ang_bigger_x add wave -noupdate /wb_orbit_intlk_tb/intlk_ang_bigger_y add wave -noupdate /wb_orbit_intlk_tb/intlk_ang_bigger_ltc_x add wave -noupdate /wb_orbit_intlk_tb/intlk_ang_bigger_ltc_y +add wave -noupdate /wb_orbit_intlk_tb/intlk_ang_bigger_any +add wave -noupdate /wb_orbit_intlk_tb/intlk_ang_bigger_ltc add wave -noupdate /wb_orbit_intlk_tb/intlk_ang_bigger -add wave -noupdate /wb_orbit_intlk_tb/intlk_ang_ltc -add wave -noupdate /wb_orbit_intlk_tb/intlk_ang add wave -noupdate /wb_orbit_intlk_tb/intlk_ltc add wave -noupdate /wb_orbit_intlk_tb/intlk add wave -noupdate /wb_orbit_intlk_tb/test_id @@ -124,16 +124,30 @@ add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_x_o add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_y_o add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_ltc_x_o add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_ltc_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_any_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_ltc_o add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_o -add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_ltc_o -add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_ltc_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_ltc_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_any_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_ltc_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_o add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_x_o add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_y_o add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_ltc_x_o add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_ltc_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_any_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_ltc_o add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_o -add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_ltc_o -add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_ltc_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_ltc_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_any_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_ltc_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_o add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ltc_o add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_o add wave -noupdate /wb_orbit_intlk_tb/DUT/regs_in @@ -149,29 +163,178 @@ add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_en_reg add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_clr_reg add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_max_x_reg add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_max_y_reg +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_min_x_reg +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_min_y_reg add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_en_reg add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_clr_reg add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_max_x_reg add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_max_y_reg +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_min_x_reg +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_min_y_reg add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_x add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_y add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_ltc_x add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_ltc_y +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_any +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger_ltc add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_bigger -add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_ltc -add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_x +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_y +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_ltc_x +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_ltc_y +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_any +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_trans_smaller add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_x add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_y add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_ltc_x add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_ltc_y +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_any +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger_ltc add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_bigger -add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_ltc -add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang -add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_x +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_y +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_ltc_x +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_ltc_y +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_any +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ang_smaller add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk +add wave -noupdate /wb_orbit_intlk_tb/DUT/intlk_ltc add wave -noupdate /wb_orbit_intlk_tb/DUT/c_PERIPH_ADDR_SIZE add wave -noupdate /wb_orbit_intlk_tb/DUT/c_INTLK_LMT_WIDTH -add wave -noupdate -divider orbit_intlk_cdc +add wave -noupdate -divider orbit_intlk +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/g_ADC_WIDTH +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/g_DECIM_WIDTH +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/g_INTLK_LMT_WIDTH +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/ref_rst_n_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/ref_clk_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_en_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_clr_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_min_sum_en_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_min_sum_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_en_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_clr_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_max_x_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_max_y_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_min_x_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_min_y_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_en_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_clr_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_max_x_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_max_y_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_min_x_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_min_y_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/fs_clk_ds_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_ch0_swap_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_ch1_swap_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_ch2_swap_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_ch3_swap_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_tag_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_swap_valid_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_ds_pos_x_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_ds_pos_y_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_ds_pos_q_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_ds_pos_sum_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_ds_pos_valid_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/fs_clk_us_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_ch0_swap_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_ch1_swap_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_ch2_swap_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_ch3_swap_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_tag_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_swap_valid_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_us_pos_x_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_us_pos_y_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_us_pos_q_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_us_pos_sum_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_us_pos_valid_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_bigger_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_bigger_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_bigger_ltc_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_bigger_ltc_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_bigger_any_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_bigger_ltc_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_bigger_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_smaller_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_smaller_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_smaller_ltc_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_smaller_ltc_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_smaller_any_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_smaller_ltc_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_smaller_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_ltc_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_bigger_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_bigger_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_bigger_ltc_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_bigger_ltc_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_bigger_any_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_bigger_ltc_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_bigger_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_smaller_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_smaller_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_smaller_ltc_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_smaller_ltc_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_smaller_any_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_smaller_ltc_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_smaller_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_ltc_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ltc_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_pos_sum_array +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_pos_valid_array +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_bigger_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_bigger +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_smaller_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_smaller +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_bigger_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_bigger +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_smaller_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_smaller +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_all +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_min_sum_n +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_min_sum_valid +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_sum_bigger +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_sum_bigger_valid +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_sum_bigger_reg +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_sum_bigger_or +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_sum_bigger_any +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_sum_bigger_en +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_trans_master_en +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/intlk_ang_master_en +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_ch0_swap +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_ch1_swap +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_ch2_swap +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_ch3_swap +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_tag +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_ds_swap_valid +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_ds_pos_x +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_ds_pos_y +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_ds_pos_q +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_ds_pos_sum +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_ds_pos_valid +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_ch0_swap +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_ch1_swap +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_ch2_swap +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_ch3_swap +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_tag +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/adc_us_swap_valid +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_us_pos_x +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_us_pos_y +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_us_pos_q +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_us_pos_sum +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/decim_us_pos_valid +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/c_ADC_WIDTH +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/c_DECIM_WIDTH +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/c_INTLK_LMT_WIDTH add wave -noupdate -divider intlk_trans add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/g_ADC_WIDTH add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/g_DECIM_WIDTH @@ -182,6 +345,8 @@ add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/ add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_clr_i add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_max_x_i add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_max_y_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_min_x_i +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_min_y_i add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/adc_ds_ch0_swap_i add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/adc_ds_ch1_swap_i add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/adc_ds_ch2_swap_i @@ -208,16 +373,24 @@ add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/ add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_bigger_y_o add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_bigger_ltc_x_o add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_bigger_ltc_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_bigger_any_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_bigger_ltc_o add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_bigger_o -add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_ltc_o -add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_smaller_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_smaller_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_smaller_ltc_x_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_smaller_ltc_y_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_smaller_any_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_smaller_ltc_o +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_smaller_o add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/adc_array add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/adc_tag_array add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/adc_valid_array add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/decim_pos_array add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/decim_pos_valid_array add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_max -add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_max_n +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_max_neg +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/intlk_trans_min add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/adc_valid_and add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/adc_valid add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/decim_pos_valid_and @@ -227,27 +400,40 @@ add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/ add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_sum_valid add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_sum_valid_reg add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_neg add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_valid -add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_n add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_bigger add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_bigger_valid add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_bigger_reg add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_bigger_valid_reg -add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_ltc_all +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_smaller +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_smaller_valid +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_smaller_reg +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_smaller_valid_reg +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_det_bigger_all +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_bigger_ltc_all add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_bigger_or +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_bigger_all +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_bigger_ltc_or +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_bigger_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_bigger_any add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_bigger -add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_all -add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_ltc -add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_any -add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_det_smaller_all +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_smaller_ltc_all +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_smaller_or +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_smaller_all +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_smaller_ltc_or +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_smaller_ltc +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_smaller_any +add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/trans_intlk_smaller add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/c_ADC_WIDTH add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/c_DECIM_WIDTH add wave -noupdate /wb_orbit_intlk_tb/DUT/cmp_orbit_intlk/cmp_orbit_intlk_trans/c_INTLK_LMT_WIDTH add wave -noupdate -divider intlk_ang TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1044545120 fs} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 191 +WaveRestoreCursors {{Cursor 1} {8395000000 fs} 0} {{Cursor 2} {8058029839 fs} 0} +quietly wave cursor active 2 +configure wave -namecolwidth 249 configure wave -valuecolwidth 100 configure wave -justifyvalue left configure wave -signalnamewidth 1 @@ -261,4 +447,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ps update -WaveRestoreZoom {1179077134 fs} {2174785414 fs} +WaveRestoreZoom {7491367289 fs} {8810980669 fs} diff --git a/hdl/testbench/orbit_intlk/wb_orbit_intlk_tb.v b/hdl/testbench/orbit_intlk/wb_orbit_intlk_tb.v index ada9dd8d..7275b3d5 100644 --- a/hdl/testbench/orbit_intlk/wb_orbit_intlk_tb.v +++ b/hdl/testbench/orbit_intlk/wb_orbit_intlk_tb.v @@ -103,16 +103,16 @@ module wb_orbit_intlk_tb; wire intlk_trans_bigger_y; wire intlk_trans_bigger_ltc_x; wire intlk_trans_bigger_ltc_y; + wire intlk_trans_bigger_any; + wire intlk_trans_bigger_ltc; wire intlk_trans_bigger; - wire intlk_trans_ltc; - wire intlk_trans; wire intlk_ang_bigger_x; wire intlk_ang_bigger_y; wire intlk_ang_bigger_ltc_x; wire intlk_ang_bigger_ltc_y; + wire intlk_ang_bigger_any; + wire intlk_ang_bigger_ltc; wire intlk_ang_bigger; - wire intlk_ang_ltc; - wire intlk_ang; wire intlk_ltc; wire intlk; @@ -172,10 +172,10 @@ module wb_orbit_intlk_tb; .intlk_trans_bigger_ltc_x_o (intlk_trans_bigger_ltc_x), .intlk_trans_bigger_ltc_y_o (intlk_trans_bigger_ltc_y), - .intlk_trans_bigger_o (intlk_trans_bigger), + .intlk_trans_bigger_any_o (intlk_trans_bigger_any), - .intlk_trans_ltc_o (intlk_trans_ltc), - .intlk_trans_o (intlk_trans), + .intlk_trans_bigger_ltc_o (intlk_trans_bigger_ltc), + .intlk_trans_bigger_o (intlk_trans_bigger), .intlk_ang_bigger_x_o (intlk_ang_bigger_x), .intlk_ang_bigger_y_o (intlk_ang_bigger_y), @@ -183,10 +183,10 @@ module wb_orbit_intlk_tb; .intlk_ang_bigger_ltc_x_o (intlk_ang_bigger_ltc_x), .intlk_ang_bigger_ltc_y_o (intlk_ang_bigger_ltc_y), - .intlk_ang_bigger_o (intlk_ang_bigger), + .intlk_ang_bigger_any_o (intlk_ang_bigger_any), - .intlk_ang_ltc_o (intlk_ang_ltc), - .intlk_ang_o (intlk_ang), + .intlk_ang_bigger_ltc_o (intlk_ang_bigger_ltc), + .intlk_ang_bigger_o (intlk_ang_bigger), .intlk_ltc_o (intlk_ltc), .intlk_o (intlk) @@ -586,6 +586,116 @@ module wb_orbit_intlk_tb; test_intlk_status ); + //////////////////////// + // TEST #6 + // Negative position + // X/Y within limits. + //////////////////////// + test_id = 6; + test_intlk_en = 1'b1; + + test_intlk_min_sum_en = 1'b1; + test_intlk_min_sum = 'h0_1000; + + test_intlk_trans_en = 1'b1; + + test_intlk_trans_max_x = 'h10_0000; + test_intlk_trans_max_y = 'h10_0000; + + test_intlk_ang_en = 1'b0; + + test_intlk_ang_max_x = 'h1_55CC0; + test_intlk_ang_max_y = 'h1_55CC0; + + test_decim_ds_pos_x = 'h0010_0000; + test_decim_ds_pos_y = 'h0010_0000; + test_decim_ds_pos_q = 'h0; + test_decim_ds_pos_sum = 'h0001_0000; + + test_decim_us_pos_x = 'hFFFF_FF00; + test_decim_us_pos_y = 'hFFFF_FF00; + test_decim_us_pos_q = 'h0; + test_decim_us_pos_sum = 'h0001_0000; + + test_intlk_status = 1'b0; + + wb_intlk_transaction( + test_id, + test_intlk_en, + test_intlk_min_sum_en, + test_intlk_min_sum, + test_intlk_trans_en , + test_intlk_trans_max_x, + test_intlk_trans_max_y, + test_intlk_ang_en , + test_intlk_ang_max_x, + test_intlk_ang_max_y, + test_decim_ds_pos_x, + test_decim_ds_pos_y, + test_decim_ds_pos_q, + test_decim_ds_pos_sum, + test_decim_us_pos_x, + test_decim_us_pos_y, + test_decim_us_pos_q, + test_decim_us_pos_sum, + test_intlk_status + ); + + //////////////////////// + // TEST #7 + // Negative position + // X/Y within limits. + //////////////////////// + test_id = 7; + test_intlk_en = 1'b1; + + test_intlk_min_sum_en = 1'b1; + test_intlk_min_sum = 'h0_1000; + + test_intlk_trans_en = 1'b1; + + test_intlk_trans_max_x = 'h0000_0000; + test_intlk_trans_max_y = 'h0000_0000; + + test_intlk_ang_en = 1'b0; + + test_intlk_ang_max_x = 'h1_55CC0; + test_intlk_ang_max_y = 'h1_55CC0; + + test_decim_ds_pos_x = 'hFFFF_FF00; + test_decim_ds_pos_y = 'hFFFF_FF00; + test_decim_ds_pos_q = 'h0; + test_decim_ds_pos_sum = 'h0001_0000; + + test_decim_us_pos_x = 'hFFFF_FF00; + test_decim_us_pos_y = 'hFFFF_FF00; + test_decim_us_pos_q = 'h0; + test_decim_us_pos_sum = 'h0001_0000; + + test_intlk_status = 1'b0; + + wb_intlk_transaction( + test_id, + test_intlk_en, + test_intlk_min_sum_en, + test_intlk_min_sum, + test_intlk_trans_en , + test_intlk_trans_max_x, + test_intlk_trans_max_y, + test_intlk_ang_en , + test_intlk_ang_max_x, + test_intlk_ang_max_y, + test_decim_ds_pos_x, + test_decim_ds_pos_y, + test_decim_ds_pos_q, + test_decim_ds_pos_sum, + test_decim_us_pos_x, + test_decim_us_pos_y, + test_decim_us_pos_q, + test_decim_us_pos_sum, + test_intlk_status + ); + $display("Simulation Done!"); $display("All Tests Passed!"); $display("---------------------------------------------"); @@ -765,19 +875,19 @@ module wb_orbit_intlk_tb; WB0.read32(`ADDR_ORBIT_INTLK_STS >> `WB_WORD_ACC, wb_reg); @(posedge sys_clk); - if (test_intlk_status == intlk) begin - $display("Interlock module correctly identified a condition: expected %d/ got %d", test_intlk_status, intlk); + if (test_intlk_status == intlk_ltc) begin + $display("Interlock module correctly identified a condition: expected %d/ got %d", test_intlk_status, intlk_ltc); end else begin - $display("Interlock module DID NOT correctly identified a condition: expected %d/ got %d", test_intlk_status, intlk); + $display("Interlock module DID NOT correctly identified a condition: expected %d/ got %d", test_intlk_status, intlk_ltc); err = 1; err_intlk = 1; end - intlk_wb = (wb_reg & `ORBIT_INTLK_STS_INTLK_BIGGER) >> `ORBIT_INTLK_STS_INTLK_BIGGER_OFFSET; + intlk_wb = (wb_reg & `ORBIT_INTLK_STS_INTLK_LTC) >> `ORBIT_INTLK_STS_INTLK_LTC_OFFSET; if (test_intlk_status == intlk_wb) begin $display("Wishbone register correctly identified a condition: expected %d/ got %d", test_intlk_status, intlk_wb); end else begin - $display("Interlock module DID NOT correctly identified a condition: expected %d/ got %d", test_intlk_status, intlk); + $display("Wishbone register DID NOT correctly identified a condition: expected %d/ got %d", test_intlk_status, intlk_wb); err = 1; err_wb = 1; end diff --git a/hdl/testbench/position/Manifest.py b/hdl/testbench/position/Manifest.py index 8a89ecd3..0ab824dc 100644 --- a/hdl/testbench/position/Manifest.py +++ b/hdl/testbench/position/Manifest.py @@ -9,7 +9,22 @@ machine_pkg = "sirius_sr_250M" -modules = {"local" : ["../../", - "../../ip_cores/general-cores/","../../sim/test_pkg/"]} +modules = { + "local" : [ + "../../modules", + "../../ip_cores/general-cores", + "../../ip_cores/dsp-cores", + "../../sim/test_pkg" + ] +} -files = ["position_tb.vhd", "blk_mem_gen_v8_2.vhd"] +files = ["position_tb.vhd"] + +include_dirs = ["../../sim", "../../sim/regs", ".", + "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src", + "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic", + "../../ip_cores/general-cores/modules/wishbone/wb_spi_bidir", + "../../ip_cores/infra-cores/modules/wishbone/wb_ethmac", + "../../ip_cores/general-cores/modules/wishbone/wb_spi"] + +vlog_opt = "+incdir+../../sim/regs +incdir+../../sim +incdir+." diff --git a/hdl/testbench/position/blk_mem_gen_v8_2.vhd b/hdl/testbench/position/blk_mem_gen_v8_2.vhd deleted file mode 100755 index 205eb45a..00000000 --- a/hdl/testbench/position/blk_mem_gen_v8_2.vhd +++ /dev/null @@ -1,281 +0,0 @@ -`protect begin_protected -`protect version = 1 -`protect encrypt_agent = "XILINX" -`protect encrypt_agent_info = "Xilinx Encryption Tool 2014" -`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" -`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) -`protect key_block -VMrHUJ7jR2a4on8XaeYhAjIaz4rRbGfwW8VHamgJPReOlpXR5SnSuFHyXpuBXjJtExIdI4sljp69 -+hXbGMBP6w== - -`protect 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3950ac71 -write 00c0 8b6afea3 -write 00c1 cfb4217e -write 00c2 785178dc -write 00c3 26fd1299 -write 00c4 84aa64d4 -write 00c5 e28d74bf -write 00c6 7d9cc95f -write 00c7 13bae689 -write 00c8 80dc7a03 -write 00c9 f61af860 -write 00ca 7fe77a67 diff --git a/hdl/testbench/position/position_tb.vhd b/hdl/testbench/position/position_tb.vhd index 657b3c3d..621e038e 100644 --- a/hdl/testbench/position/position_tb.vhd +++ b/hdl/testbench/position/position_tb.vhd @@ -29,6 +29,7 @@ use std.textio.all; library work; use work.dsp_cores_pkg.all; +use work.bpm_cores_pkg.all; use work.machine_pkg; entity position_tb is @@ -77,13 +78,13 @@ architecture test of position_tb is constant c_monit2_cic_ratio : positive := machine_pkg.c_pos_calc_monit2_cic_ratio; constant c_ksum : std_logic_vector(23 downto 0) := - std_logic_vector(to_unsigned(1e8, 24)); + std_logic_vector(to_unsigned(1e7, 24)); constant c_kx : std_logic_vector(23 downto 0) := - std_logic_vector(to_unsigned(1e8, 24)); + std_logic_vector(to_unsigned(1e7, 24)); constant c_ky : std_logic_vector(23 downto 0) := - std_logic_vector(to_unsigned(1e8, 24)); + std_logic_vector(to_unsigned(1e7, 24)); signal clock : std_logic := '0'; @@ -155,131 +156,6 @@ architecture test of position_tb is end procedure p_out_file; - - component position_calc is - generic ( - g_input_width : natural; - g_mixed_width : natural; - g_adc_ratio : natural; - g_dds_width : natural; - g_dds_points : natural; - g_sin_file : string; - g_cos_file : string; - g_tbt_cic_delay : natural; - g_tbt_cic_stages : natural; - g_tbt_ratio : natural; - g_tbt_decim_width : natural; - g_fofb_cic_delay : natural; - g_fofb_cic_stages : natural; - g_fofb_ratio : natural; - g_fofb_decim_width : natural; - g_monit1_cic_delay : natural; - g_monit1_cic_stages : natural; - g_monit1_ratio : natural; - g_monit1_cic_ratio : positive; - g_monit2_cic_delay : natural; - g_monit2_cic_stages : natural; - g_monit2_ratio : natural; - g_monit2_cic_ratio : positive; - g_monit_decim_width : natural; - g_tbt_cordic_stages : positive; - g_tbt_cordic_iter_per_clk : positive; - g_tbt_cordic_ratio : positive; - g_fofb_cordic_stages : positive; - g_fofb_cordic_iter_per_clk : positive; - g_fofb_cordic_ratio : positive; - g_k_width : natural; - g_IQ_width : natural); - port ( - adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0); - adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0); - adc_ch2_i : in std_logic_vector(g_input_width-1 downto 0); - adc_ch3_i : in std_logic_vector(g_input_width-1 downto 0); - clk_i : in std_logic; - rst_i : in std_logic; - ksum_i : in std_logic_vector(g_k_width-1 downto 0); - kx_i : in std_logic_vector(g_k_width-1 downto 0); - ky_i : in std_logic_vector(g_k_width-1 downto 0); - mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0); - mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0); - mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0); - mix_ch1_q_o : out std_logic_vector(g_IQ_width-1 downto 0); - mix_ch2_i_o : out std_logic_vector(g_IQ_width-1 downto 0); - mix_ch2_q_o : out std_logic_vector(g_IQ_width-1 downto 0); - mix_ch3_i_o : out std_logic_vector(g_IQ_width-1 downto 0); - mix_ch3_q_o : out std_logic_vector(g_IQ_width-1 downto 0); - mix_valid_o : out std_logic; - mix_ce_o : out std_logic; - tbt_decim_ch0_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_decim_ch0_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_decim_ch1_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_decim_ch1_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_decim_ch2_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_decim_ch2_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_decim_ch3_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_decim_ch3_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_decim_valid_o : out std_logic; - tbt_decim_ce_o : out std_logic; - tbt_amp_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_amp_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_amp_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_amp_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_amp_valid_o : out std_logic; - tbt_amp_ce_o : out std_logic; - tbt_pha_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_pha_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_pha_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_pha_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_pha_valid_o : out std_logic; - tbt_pha_ce_o : out std_logic; - fofb_decim_ch0_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_decim_ch0_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_decim_ch1_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_decim_ch1_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_decim_ch2_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_decim_ch2_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_decim_ch3_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_decim_ch3_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_decim_valid_o : out std_logic; - fofb_decim_ce_o : out std_logic; - fofb_amp_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_amp_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_amp_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_amp_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_amp_valid_o : out std_logic; - fofb_amp_ce_o : out std_logic; - fofb_pha_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_pha_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_pha_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_pha_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_pha_valid_o : out std_logic; - fofb_pha_ce_o : out std_logic; - monit_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0); - monit_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0); - monit_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0); - monit_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0); - monit_amp_valid_o : out std_logic; - monit_amp_ce_o : out std_logic; - tbt_pos_x_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_pos_y_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_pos_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_pos_sum_o : out std_logic_vector(g_tbt_decim_width-1 downto 0); - tbt_pos_valid_o : out std_logic; - tbt_pos_ce_o : out std_logic; - fofb_pos_x_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_pos_y_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_pos_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_pos_sum_o : out std_logic_vector(g_fofb_decim_width-1 downto 0); - fofb_pos_valid_o : out std_logic; - fofb_pos_ce_o : out std_logic; - monit_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0); - monit_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0); - monit_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0); - monit_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0); - monit_pos_valid_o : out std_logic; - monit_pos_ce_o : out std_logic); - end component position_calc; - begin clk_gen : process @@ -348,8 +224,6 @@ begin g_adc_ratio => c_adc_ratio, g_dds_width => c_dds_width, g_dds_points => c_dds_points, - g_sin_file => "../../../dsp-cores/hdl/modules/position_calc/dds_sin.nif", - g_cos_file => "../../../dsp-cores/hdl/modules/position_calc/dds_cos.nif", g_tbt_cic_delay => c_tbt_cic_delay, g_tbt_cic_stages => c_tbt_cic_stages, g_tbt_ratio => c_tbt_ratio, @@ -382,6 +256,8 @@ begin adc_ch1_i => b, adc_ch2_i => c, adc_ch3_i => d, + adc_valid_i => '1', + adc_tag_i => (others => '0'), clk_i => clock, rst_i => reset, @@ -410,6 +286,7 @@ begin tbt_decim_ch3_q_o => open, tbt_decim_valid_o => open, tbt_decim_ce_o => open, + tbt_tag_i => (others => '0'), tbt_amp_ch0_o => a_tbt_out, tbt_amp_ch1_o => b_tbt_out, tbt_amp_ch2_o => c_tbt_out, @@ -446,6 +323,8 @@ begin monit_amp_ch3_o => open, monit_amp_valid_o => open, monit_amp_ce_o => open, + monit_tag_i => (others => '0'), + monit1_tag_i => (others => '0'), tbt_pos_x_o => tbt_pos_x_out, tbt_pos_y_o => tbt_pos_y_out, diff --git a/hdl/testbench/position/sin_lut_sirius_50_191.mif b/hdl/testbench/position/sin_lut_sirius_50_191.mif new file mode 100644 index 00000000..35fd0d44 --- /dev/null +++ b/hdl/testbench/position/sin_lut_sirius_50_191.mif @@ -0,0 +1,191 @@ +1010010101111110 +1010110001101111 +0110011011011110 +0100010001011010 +1000111100000110 +1100110001011011 +0111100010011101 +0010000111001110 +1000001001100011 +1111000011000110 +0111111111011101 +1111110001010001 +1000000010101110 +0001011010000100 +0111101111111110 +1101011100100110 +1000101000001101 +0011101001001100 +0110110101010100 +1011010110001001 +1001110110110000 +0101100100000010 +0101010100100110 +1001101001100111 +1011100111100000 +0110111111111000 +0011010110010000 +1000100000011100 +1101110000101011 +0111110100110001 +0001000101010001 +1000000000111111 +0000000110010100 +0111111110000101 +1110101110010000 +1000001110000001 +0010011011011010 +0111011011000000 +1100011110010110 +1001000110011000 +0100100010111110 +0110001110100110 +1010100010000101 +1010100101001010 +0110010001001110 +0100011111100000 +1001000100010001 +1100100010001000 +0111011100100100 +0010010111011001 +1000001101000011 +1110110010011010 +0111111110011011 +0000000010000111 +1000000001010001 +0001001001011100 +0111110011111000 +1101101100101001 +1000100001111011 +0011011010000100 +0110111101110101 +1011100100000000 +1001101100001011 +0101010111101111 +0101100000111111 +1001110100000100 +1011011001100101 +0110110111011111 +0011100101011100 +1000100110100110 +1101100000100110 +0111110000111111 +0001010101111010 +1000000010010011 +1111110101011110 +0111111111010000 +1110111110111010 +1000001010011000 +0010001011010010 +0111100001000010 +1100101101100101 +1000111110000110 +0100010100111101 +0110011000111100 +1010101110100100 +1010011000111110 +0110000110100011 +0100101101010010 +1001001100111001 +1100010011000101 +0111010110001001 +0010100111011001 +1000010001000110 +1110100001110011 +0111111100110101 +0000010010111100 +1000000000010111 +0000111000101110 +0111110111010000 +1101111100110110 +1000011100001010 +0011001010101110 +0111000101110111 +1011110010001010 +1001100010000011 +0101001011000100 +0101101101000000 +1001111110111101 +1011001011111101 +0110101110100111 +0011110100010111 +1000101101010000 +1101010000101011 +0111101100101011 +0001100110011110 +1000000100001011 +1111100100101001 +0111111111111000 +1111001111101010 +1000000111010010 +0001111011000000 +0111100110100010 +1100111101000011 +1000110110010011 +0100000110101001 +0110100010110111 +1010111011011010 +1010001101001010 +0101111011011100 +0100111010101111 +1001010110000001 +1100000100010010 +0111001111001110 +0010110111001110 +1000010101101100 +1110010001010011 +0111111010101100 +0000100011110001 +1000000000000001 +0000100111111101 +0111111010000100 +1110001101001100 +1000010110111010 +0010111011001001 +0111001101011010 +1100000000100111 +1001011000010111 +0100111110000011 +0101111000100111 +1010001010010001 +1010111110101011 +0110100101010001 +0100000011000010 +1000110100011011 +1101000000111100 +0111100111110101 +0001110110111010 +1000000110100101 +1111010011110110 +0111111111111101 +1111100000011100 +1000000100101110 +0001101010100101 +0111101011100001 +1101001100101110 +1000101111000000 +0011111000000011 +0110101100010100 +1011001000100111 +1010000001110000 +0101101111111100 +0101000111110110 +1001011111100101 +1011110101110000 +0111000111110011 +0011000110110110 +1000011010110011 +1110000000111011 +0111111000000000 +0000110100100011 +1000000000001111 +0000010111001010 +0111111100010110 +1110011101101011 +1000010010001100 +0010101011010111 +0111010100011101 +1100001111010110 +1001001111001000 +0100110000101011 +0110000011110100 diff --git a/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd b/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd index cf0921dc..9da04b5d 100644 --- a/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd +++ b/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd @@ -2858,6 +2858,9 @@ begin -- width of K constants g_k_width => c_pos_calc_k_width, + -- width of offset constants + g_offset_width => c_pos_calc_offset_width, + --width for IQ output g_IQ_width => c_pos_calc_IQ_width, @@ -3083,6 +3086,9 @@ begin -- width of K constants g_k_width => c_pos_calc_k_width, + -- width of offset constants + g_offset_width => c_pos_calc_offset_width, + --width for IQ output g_IQ_width => c_pos_calc_IQ_width,