[arm32] (vec1 & (vec2 ^ vec3)) ^ vec3 should transform into vbit/vbsl/vbif

[Validark]

export fn select(vec1: @Vector(8, u8), vec2: @TypeOf(vec1), vec3: @TypeOf(vec1)) @TypeOf(vec1) {
    return (vec1 & (vec2 ^ vec3)) ^ vec3;
}

export fn select2(vec1: @Vector(8, u8), vec2: @TypeOf(vec1), vec3: @TypeOf(vec1)) @TypeOf(vec1) {
    return (vec1 & vec2) | (~vec1 & vec3);
}

On aarch64, these compile the same:

        bsl     v0.8b, v1.8b, v2.8b
        ret

On arm, we get:
https://zig.godbolt.org/z/haTaP4hnK

select:
        vldr    d16, [sp]
        vmov    d17, r2, r3
        vmov    d18, r0, r1
        veor    d17, d16, d17
        vand    d17, d17, d18
        veor    d16, d17, d16
        vmov    r0, r1, d16
        bx      lr

select2:
        vmov    d18, r0, r1
        vldr    d16, [sp]
        vmov    d17, r2, r3
        vbit    d16, d17, d18
        vmov    r0, r1, d16
        bx      lr

[llvmbot]

@llvm/issue-subscribers-backend-arm

Author: Niles Salter (Validark)

```zig export fn select(vec1: @Vector(8, u8), vec2: @TypeOf(vec1), vec3: @TypeOf(vec1)) @TypeOf(vec1) { return (vec1 & (vec2 ^ vec3)) ^ vec3; }

export fn select2(vec1: @Vector(8, u8), vec2: @TypeOf(vec1), vec3: @TypeOf(vec1)) @TypeOf(vec1) {
return (vec1 & vec2) | (~vec1 & vec3);
}

On aarch64, these compile the same:
```asm
        bsl     v0.8b, v1.8b, v2.8b
        ret

On arm, we get:
https://zig.godbolt.org/z/haTaP4hnK

select:
        vldr    d16, [sp]
        vmov    d17, r2, r3
        vmov    d18, r0, r1
        veor    d17, d16, d17
        vand    d17, d17, d18
        veor    d16, d17, d16
        vmov    r0, r1, d16
        bx      lr

select2:
        vmov    d18, r0, r1
        vldr    d16, [sp]
        vmov    d17, r2, r3
        vbit    d16, d17, d18
        vmov    r0, r1, d16
        bx      lr