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96 changes: 46 additions & 50 deletions include/circt/Dialect/FIRRTL/FIRRTLDeclarations.td
Original file line number Diff line number Diff line change
Expand Up @@ -64,61 +64,57 @@ def InstanceOp : HardwareDeclOp<"instance", [
```
}];

let arguments = (ins FlatSymbolRefAttr:$moduleName, StrAttr:$name, NameKindAttr:$nameKind,
DenseBoolArrayAttr:$portDirections, StrArrayAttr:$portNames,
AnnotationArrayAttr:$annotations,
PortAnnotationsAttr:$portAnnotations,
LayerArrayAttr:$layers,
UnitAttr:$lowerToBind,
OptionalAttr<InnerSymAttr>:$inner_sym);
let arguments = (ins FlatSymbolRefAttr:$moduleName, StrAttr:$name,
NameKindAttr:$nameKind, DenseBoolArrayAttr:$portDirections,
StrArrayAttr:$portNames, AnnotationArrayAttr:$annotations,
PortAnnotationsAttr:$portAnnotations, LayerArrayAttr:$layers,
UnitAttr:$lowerToBind, UnitAttr:$doNotPrint,
OptionalAttr<InnerSymAttr>:$inner_sym);

let results = (outs Variadic<AnyType>:$results);

let hasCustomAssemblyFormat = 1;

let builders = [
OpBuilder<(ins "::mlir::TypeRange":$resultTypes,
"::mlir::StringRef":$moduleName,
"::mlir::StringRef":$name,
"::circt::firrtl::NameKindEnum":$nameKind,
"::mlir::ArrayRef<Direction>":$portDirections,
"::mlir::ArrayRef<Attribute>":$portNames,
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
CArg<"ArrayRef<Attribute>", "{}">:$portAnnotations,
CArg<"::mlir::ArrayRef<Attribute>", "{}">:$layers,
CArg<"bool","false">:$lowerToBind,
CArg<"StringAttr", "StringAttr()">:$innerSym)>,
OpBuilder<(ins "::mlir::TypeRange":$resultTypes,
"::mlir::StringRef":$moduleName,
"::mlir::StringRef":$name,
"::circt::firrtl::NameKindEnum":$nameKind,
"::mlir::ArrayRef<Direction>":$portDirections,
"::mlir::ArrayRef<Attribute>":$portNames,
"ArrayRef<Attribute>":$annotations,
"ArrayRef<Attribute>":$portAnnotations,
"::mlir::ArrayRef<Attribute>":$layers,
"bool":$lowerToBind,
"hw::InnerSymAttr":$innerSym)>,

/// Constructor when you have the target module in hand.
OpBuilder<(ins "FModuleLike":$module,
"mlir::StringRef":$name,
CArg<"NameKindEnum", "NameKindEnum::DroppableName">:$nameKind,
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
CArg<"ArrayRef<Attribute>", "{}">:$portAnnotations,
CArg<"bool","false">:$lowerToBind,
CArg<"hw::InnerSymAttr", "hw::InnerSymAttr()">:$innerSym)>,

/// Constructor when you have a port info list in hand.
OpBuilder<(ins "ArrayRef<PortInfo>":$ports,
"::mlir::StringRef":$moduleName,
"mlir::StringRef":$name,
CArg<"NameKindEnum", "NameKindEnum::DroppableName">:$nameKind,
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
CArg<"ArrayRef<Attribute>", "{}">:$layers,
CArg<"bool","false">:$lowerToBind,
CArg<"hw::InnerSymAttr", "hw::InnerSymAttr()">:$innerSym)>
];
let builders =
[OpBuilder<(ins "::mlir::TypeRange":$resultTypes,
"::mlir::StringRef":$moduleName, "::mlir::StringRef":$name,
"::circt::firrtl::NameKindEnum":$nameKind,
"::mlir::ArrayRef<Direction>":$portDirections,
"::mlir::ArrayRef<Attribute>":$portNames,
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
CArg<"ArrayRef<Attribute>", "{}">:$portAnnotations,
CArg<"::mlir::ArrayRef<Attribute>", "{}">:$layers,
CArg<"bool", "false">:$lowerToBind,
CArg<"bool", "false">:$doNotPrint,
CArg<"StringAttr", "StringAttr()">:$innerSym)>,
OpBuilder<(ins "::mlir::TypeRange":$resultTypes,
"::mlir::StringRef":$moduleName, "::mlir::StringRef":$name,
"::circt::firrtl::NameKindEnum":$nameKind,
"::mlir::ArrayRef<Direction>":$portDirections,
"::mlir::ArrayRef<Attribute>":$portNames,
"ArrayRef<Attribute>":$annotations,
"ArrayRef<Attribute>":$portAnnotations,
"::mlir::ArrayRef<Attribute>":$layers, "bool":$lowerToBind,
"bool":$doNotPrint, "hw::InnerSymAttr":$innerSym)>,

/// Constructor when you have the target module in hand.
OpBuilder<(ins "FModuleLike":$module, "mlir::StringRef":$name,
CArg<"NameKindEnum", "NameKindEnum::DroppableName">:$nameKind,
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
CArg<"ArrayRef<Attribute>", "{}">:$portAnnotations,
CArg<"bool", "false">:$lowerToBind,
CArg<"bool", "false">:$doNotPrint,
CArg<"hw::InnerSymAttr", "hw::InnerSymAttr()">:$innerSym)>,

/// Constructor when you have a port info list in hand.
OpBuilder<(ins "ArrayRef<PortInfo>":$ports,
"::mlir::StringRef":$moduleName, "mlir::StringRef":$name,
CArg<"NameKindEnum", "NameKindEnum::DroppableName">:$nameKind,
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
CArg<"ArrayRef<Attribute>", "{}">:$layers,
CArg<"bool", "false">:$lowerToBind,
CArg<"bool", "false">:$doNotPrint,
CArg<"hw::InnerSymAttr", "hw::InnerSymAttr()">:$innerSym)>];

let extraClassDeclaration = [{
/// Return the port direction for the specified result number.
Expand Down
11 changes: 7 additions & 4 deletions lib/Analysis/FIRRTLInstanceInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -140,10 +140,13 @@ InstanceInfo::InstanceInfo(Operation *op, mlir::AnalysisManager &am) {
attributes.underDut.mergeIn(parentAttrs.underDut);

// Update underLayer.
auto instanceOp = useIt->getInstance();
bool underLayer = (isa<InstanceOp>(instanceOp) &&
cast<InstanceOp>(instanceOp).getLowerToBind()) ||
instanceOp->getParentOfType<LayerBlockOp>();
bool underLayer = false;
if (auto instanceOp = useIt->getInstance<InstanceOp>()) {
if (instanceOp.getLowerToBind() || instanceOp.getDoNotPrint() ||
instanceOp->getParentOfType<LayerBlockOp>())
underLayer = true;
}

if (!isGCCompanion) {
if (underLayer)
attributes.underLayer.mergeIn(true);
Expand Down
11 changes: 5 additions & 6 deletions lib/Conversion/FIRRTLToHW/LowerToHW.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -249,14 +249,13 @@ struct CircuitLoweringState {
// Pre-populate the dutModules member with a list of all modules that are
// determined to be under the DUT.
auto inDUT = [&](igraph::ModuleOpInterface child) {
auto isBind = [](igraph::InstanceRecord *instRec) {
auto inst = instRec->getInstance();
if (auto *finst = dyn_cast<InstanceOp>(&inst))
return finst->getLowerToBind();
auto isPhony = [](igraph::InstanceRecord *instRec) {
if (auto inst = instRec->getInstance<InstanceOp>())
return inst.getLowerToBind() || inst.getDoNotPrint();
return false;
};
if (auto parent = dyn_cast<igraph::ModuleOpInterface>(*dut))
return getInstanceGraph().isAncestor(child, parent, isBind);
return getInstanceGraph().isAncestor(child, parent, isPhony);
return dut == child;
};
circuitOp->walk([&](FModuleLike moduleOp) {
Expand Down Expand Up @@ -3397,7 +3396,7 @@ LogicalResult FIRRTLLowering::visitDecl(InstanceOp oldInstance) {
auto newInstance = builder.create<hw::InstanceOp>(
newModule, oldInstance.getNameAttr(), operands, parameters, innerSym);

if (oldInstance.getLowerToBind())
if (oldInstance.getLowerToBind() || oldInstance.getDoNotPrint())
newInstance.setDoNotPrintAttr(builder.getUnitAttr());

if (newInstance.getInnerSymAttr())
Expand Down
49 changes: 30 additions & 19 deletions lib/Dialect/FIRRTL/FIRRTLOps.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2217,24 +2217,30 @@ LogicalResult LayerOp::verify() {
// InstanceOp
//===----------------------------------------------------------------------===//

void InstanceOp::build(
OpBuilder &builder, OperationState &result, TypeRange resultTypes,
StringRef moduleName, StringRef name, NameKindEnum nameKind,
ArrayRef<Direction> portDirections, ArrayRef<Attribute> portNames,
ArrayRef<Attribute> annotations, ArrayRef<Attribute> portAnnotations,
ArrayRef<Attribute> layers, bool lowerToBind, StringAttr innerSym) {
void InstanceOp::build(OpBuilder &builder, OperationState &result,
TypeRange resultTypes, StringRef moduleName,
StringRef name, NameKindEnum nameKind,
ArrayRef<Direction> portDirections,
ArrayRef<Attribute> portNames,
ArrayRef<Attribute> annotations,
ArrayRef<Attribute> portAnnotations,
ArrayRef<Attribute> layers, bool lowerToBind,
bool doNotPrint, StringAttr innerSym) {
build(builder, result, resultTypes, moduleName, name, nameKind,
portDirections, portNames, annotations, portAnnotations, layers,
lowerToBind,
lowerToBind, doNotPrint,
innerSym ? hw::InnerSymAttr::get(innerSym) : hw::InnerSymAttr());
}

void InstanceOp::build(
OpBuilder &builder, OperationState &result, TypeRange resultTypes,
StringRef moduleName, StringRef name, NameKindEnum nameKind,
ArrayRef<Direction> portDirections, ArrayRef<Attribute> portNames,
ArrayRef<Attribute> annotations, ArrayRef<Attribute> portAnnotations,
ArrayRef<Attribute> layers, bool lowerToBind, hw::InnerSymAttr innerSym) {
void InstanceOp::build(OpBuilder &builder, OperationState &result,
TypeRange resultTypes, StringRef moduleName,
StringRef name, NameKindEnum nameKind,
ArrayRef<Direction> portDirections,
ArrayRef<Attribute> portNames,
ArrayRef<Attribute> annotations,
ArrayRef<Attribute> portAnnotations,
ArrayRef<Attribute> layers, bool lowerToBind,
bool doNotPrint, hw::InnerSymAttr innerSym) {
result.addTypes(resultTypes);
result.getOrAddProperties<Properties>().setModuleName(
SymbolRefAttr::get(builder.getContext(), moduleName));
Expand All @@ -2250,6 +2256,9 @@ void InstanceOp::build(
if (lowerToBind)
result.getOrAddProperties<Properties>().setLowerToBind(
builder.getUnitAttr());
if (doNotPrint)
result.getOrAddProperties<Properties>().setDoNotPrint(
builder.getUnitAttr());
if (innerSym)
result.getOrAddProperties<Properties>().setInnerSym(innerSym);

Expand All @@ -2272,7 +2281,7 @@ void InstanceOp::build(OpBuilder &builder, OperationState &result,
FModuleLike module, StringRef name,
NameKindEnum nameKind, ArrayRef<Attribute> annotations,
ArrayRef<Attribute> portAnnotations, bool lowerToBind,
hw::InnerSymAttr innerSym) {
bool doNotPrint, hw::InnerSymAttr innerSym) {

// Gather the result types.
SmallVector<Type> resultTypes;
Expand All @@ -2298,15 +2307,15 @@ void InstanceOp::build(OpBuilder &builder, OperationState &result,
module.getPortDirectionsAttr(), module.getPortNamesAttr(),
builder.getArrayAttr(annotations), portAnnotationsAttr,
module.getLayersAttr(), lowerToBind ? builder.getUnitAttr() : UnitAttr(),
innerSym);
doNotPrint ? builder.getUnitAttr() : UnitAttr(), innerSym);
}

void InstanceOp::build(OpBuilder &builder, OperationState &odsState,
ArrayRef<PortInfo> ports, StringRef moduleName,
StringRef name, NameKindEnum nameKind,
ArrayRef<Attribute> annotations,
ArrayRef<Attribute> layers, bool lowerToBind,
hw::InnerSymAttr innerSym) {
bool doNotPrint, hw::InnerSymAttr innerSym) {
// Gather the result types.
SmallVector<Type> newResultTypes;
SmallVector<Direction> newPortDirections;
Expand All @@ -2321,7 +2330,7 @@ void InstanceOp::build(OpBuilder &builder, OperationState &odsState,

return build(builder, odsState, newResultTypes, moduleName, name, nameKind,
newPortDirections, newPortNames, annotations, newPortAnnotations,
layers, lowerToBind, innerSym);
layers, lowerToBind, doNotPrint, innerSym);
}

LogicalResult InstanceOp::verify() {
Expand Down Expand Up @@ -2365,7 +2374,8 @@ InstanceOp InstanceOp::erasePorts(OpBuilder &builder,
auto newOp = builder.create<InstanceOp>(
getLoc(), newResultTypes, getModuleName(), getName(), getNameKind(),
newPortDirections, newPortNames, getAnnotations().getValue(),
newPortAnnotations, getLayers(), getLowerToBind(), getInnerSymAttr());
newPortAnnotations, getLayers(), getLowerToBind(), getDoNotPrint(),
getInnerSymAttr());

for (unsigned oldIdx = 0, newIdx = 0, numOldPorts = getNumResults();
oldIdx != numOldPorts; ++oldIdx) {
Expand Down Expand Up @@ -2438,7 +2448,8 @@ InstanceOp::cloneAndInsertPorts(ArrayRef<std::pair<unsigned, PortInfo>> ports) {
return OpBuilder(*this).create<InstanceOp>(
getLoc(), newPortTypes, getModuleName(), getName(), getNameKind(),
newPortDirections, newPortNames, getAnnotations().getValue(),
newPortAnnos, getLayers(), getLowerToBind(), getInnerSymAttr());
newPortAnnos, getLayers(), getLowerToBind(), getDoNotPrint(),
getInnerSymAttr());
}

LogicalResult InstanceOp::verifySymbolUses(SymbolTableCollection &symbolTable) {
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Import/FIRParser.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4132,7 +4132,7 @@ ParseResult FIRStmtParser::parseInstance() {
hw::InnerSymAttr sym = {};
auto result = builder.create<InstanceOp>(
referencedModule, id, NameKindEnum::InterestingName,
annotations.getValue(), portAnnotations, false, sym);
annotations.getValue(), portAnnotations, false, false, sym);

// Since we are implicitly unbundling the instance results, we need to keep
// track of the mapping from bundle fields to results in the unbundledValues
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Transforms/ExtractInstances.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -969,7 +969,7 @@ void ExtractInstancesPass::groupInstances() {
wrapper.getLoc(), wrapper, wrapperName, NameKindEnum::DroppableName,
ArrayRef<Attribute>{},
/*portAnnotations=*/ArrayRef<Attribute>{}, /*lowerToBind=*/false,
hw::InnerSymAttr::get(wrapperInstName));
/*doNotPrint=*/false, hw::InnerSymAttr::get(wrapperInstName));
unsigned portIdx = 0;
for (auto inst : insts)
for (auto result : inst.getResults())
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Transforms/InjectDUTHierarchy.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -177,7 +177,7 @@ void InjectDUTHierarchy::runOnOperation() {
auto wrapperInst =
b.create<InstanceOp>(b.getUnknownLoc(), wrapper, wrapper.getModuleName(),
NameKindEnum::DroppableName, ArrayRef<Attribute>{},
ArrayRef<Attribute>{}, false,
ArrayRef<Attribute>{}, false, false,
hw::InnerSymAttr::get(b.getStringAttr(
dutNS.newName(wrapper.getModuleName()))));
for (const auto &pair : llvm::enumerate(wrapperInst.getResults())) {
Expand Down
1 change: 1 addition & 0 deletions lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -652,6 +652,7 @@ LogicalResult LowerLayersPass::runOnModuleBody(FModuleOp moduleOp,
instanceName, NameKindEnum::DroppableName,
/*annotations=*/ArrayRef<Attribute>{},
/*portAnnotations=*/ArrayRef<Attribute>{}, /*lowerToBind=*/true,
/*doNotPrint=*/false,
/*innerSym=*/
(innerSyms.empty() ? hw::InnerSymAttr{}
: hw::InnerSymAttr::get(builder.getStringAttr(
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Transforms/LowerMemory.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -497,7 +497,7 @@ InstanceOp LowerMemoryPass::emitMemoryInstance(MemOp op, FModuleOp module,
/*annotations=*/ArrayRef<Attribute>(),
/*portAnnotations=*/ArrayRef<Attribute>(),
/*layers=*/ArrayRef<Attribute>(), /*lowerToBind=*/false,
op.getInnerSymAttr());
/*doNotPrint=*/false, op.getInnerSymAttr());

// Update all users of the result of read ports
for (auto [subfield, result] : returnHolder) {
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Transforms/LowerSignatures.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -404,7 +404,7 @@ static void lowerModuleBody(FModuleOp mod,
auto newOp = theBuilder.create<InstanceOp>(
instPorts, inst.getModuleName(), inst.getName(), inst.getNameKind(),
annos.getValue(), inst.getLayers(), inst.getLowerToBind(),
inst.getInnerSymAttr());
inst.getDoNotPrint(), inst.getInnerSymAttr());

auto oldDict = inst->getDiscardableAttrDictionary();
auto newDict = newOp->getDiscardableAttrDictionary();
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1508,7 +1508,7 @@ bool TypeLoweringVisitor::visitDecl(InstanceOp op) {
op.getNameKindAttr(), direction::packAttribute(context, newDirs),
builder->getArrayAttr(newNames), op.getAnnotations(),
builder->getArrayAttr(newPortAnno), op.getLayersAttr(),
op.getLowerToBindAttr(),
op.getLowerToBindAttr(), op.getDoNotPrintAttr(),
sym ? hw::InnerSymAttr::get(sym) : hw::InnerSymAttr());

newInstance->setDiscardableAttrs(op->getDiscardableAttrDictionary());
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Transforms/SpecializeOption.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -85,7 +85,7 @@ struct SpecializeOptionPass
inst.getNameKindAttr(), inst.getPortDirectionsAttr(),
inst.getPortNamesAttr(), inst.getAnnotationsAttr(),
inst.getPortAnnotationsAttr(), builder.getArrayAttr({}),
UnitAttr{}, inst.getInnerSymAttr());
UnitAttr{}, UnitAttr{}, inst.getInnerSymAttr());
inst.replaceAllUsesWith(newInst);
inst.erase();

Expand Down
5 changes: 5 additions & 0 deletions test/Conversion/FIRRTLToHW/lower-to-hw.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -650,6 +650,11 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.connect %qux, %dummy : !firrtl.uint<1>, !firrtl.uint<1>
}

// CHECK-LABEL: hw.module @DoNotPrintTest()
firrtl.module @DoNotPrintTest() {
// CHECK: hw.instance "foo" @foo() -> () {doNotPrint}
firrtl.instance foo {doNotPrint} @foo()
}

// CHECK-LABEL: hw.module private @attributes_preservation
// CHECK-SAME: firrtl.foo = "bar"
Expand Down