Merge branch 'master' of github.com:leros-dev/leros

Author: schoeberl

src/main/scala/leros/DataMem.scala

@@ -4,7 +4,7 @@ import chisel3._
 import leros.util.Assembler
 
 
-class DataMemIO(memAddrWidth: Int) extends Bundle {
+class DataMemIO(val memAddrWidth: Int) extends Bundle {
   val rdAddr = Input(UInt(memAddrWidth.W))
   val rdData = Output(UInt(32.W))
   val wrAddr = Input(UInt(memAddrWidth.W))

src/main/scala/leros/InstrMem.scala

@@ -4,6 +4,10 @@ import chisel3._
 import chisel3.util._
 import leros.util.Assembler
 
+class InstrMemIO(memAddrWidth: Int) extends Bundle {
+  val addr = Input(UInt(memAddrWidth.W))
+  val instr = Output(UInt(16.W))
+}
 
 /**
  * Instruction memory.
@@ -13,10 +17,7 @@ import leros.util.Assembler
  * FIXME: Verilog generation from Chisel results in logic, not in a ROM.
  */
 class InstrMem(memAddrWidth: Int, prog: String) extends Module {
-  val io = IO(new Bundle {
-    val addr = Input(UInt(memAddrWidth.W))
-    val instr = Output(UInt(16.W))
-  })
+  val io = IO(new InstrMemIO(memAddrWidth))
   val code = Assembler.getProgram(prog)
   assert(scala.math.pow(2, memAddrWidth) >= code.length, "Program too large")
   val progMem = VecInit(code.toIndexedSeq.map(_.asUInt(16.W)))

src/main/scala/leros/Leros.scala

@@ -10,12 +10,9 @@ import leros.State._
  *
  * Sequential implementation with two states.
  */
-class Leros(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends Module {
+class Leros(size: Int = 32, memAddrWidth: Int = 8) extends Module {
 
-  val imemIO = IO(new Bundle {
-    val addr = Output(UInt(memAddrWidth.W))
-    val instr = Input(UInt(16.W))
-  })
+  val imemIO = IO(Flipped(new InstrMemIO(memAddrWidth)))
   val dmemIO = IO(Flipped(new DataMemIO(16)))
 
   val alu = Module(new AluAccu(size))
@@ -151,5 +148,5 @@ class Leros(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends Module
 }
 
 object Leros extends App {
-  emitVerilog(new Leros(args(0)), Array("--target-dir", "generated"))
+  emitVerilog(new Leros, Array("--target-dir", "generated"))
 }

src/main/scala/leros/LerosTop.scala

@@ -18,7 +18,7 @@ class LerosTop(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends Modu
     val led = Output(UInt(8.W))
   })
 
-  val leros = Module(new Leros(prog))
+  val leros = Module(new Leros)
   // Fetch from instruction memory with an address register that is reset to 0
   val instrMem = Module(new InstrMem(memAddrWidth, prog))
   // Data memory, including the register memory