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schoeberlschoeberl
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Merge pull request #10 from SyedAnasAlam/master
Writeable instruction memory over uart, missing reset logic
2 parents 4b8c5cd + 21942ac commit 7f57817

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‎src/main/scala/leros/uart/UARTRx.scala

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/*
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* Copyright: 2014-2018, Technical University of Denmark, DTU Compute
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* Author: Martin Schoeberl ([email protected])
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* License: Simplified BSD License
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*
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* A UART is a serial port, also called an RS232 interface.
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*
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*/
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package leros.uart
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import chisel3._
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import chisel3.util._
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class UartIO extends DecoupledIO(UInt(8.W)) {
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}
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/**
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* Receive part of the UART.
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* Use a ready/valid handshaking.
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* The following code is inspired by Tommy's receive code at:
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* https://github.com/tommythorn/yarvi
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*/
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class Rx(frequency: Int, baudRate: Int) extends Module {
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val io = IO(new Bundle {
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val rxd = Input(UInt(1.W))
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val channel = new UartIO()
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})
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val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1).U
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val START_CNT = ((3 * frequency / 2 + baudRate / 2) / baudRate - 1).U
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// Sync in the asynchronous RX data, reset to 1 to not start reading after a reset
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val rxReg = RegNext(RegNext(io.rxd, 1.U), 1.U)
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val shiftReg = RegInit(0.U(8.W))
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val cntReg = RegInit(0.U(20.W))
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val bitsReg = RegInit(0.U(4.W))
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val validReg = RegInit(false.B)
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when(cntReg =/= 0.U) {
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cntReg := cntReg - 1.U
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} .elsewhen(bitsReg =/= 0.U) {
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cntReg := BIT_CNT
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shiftReg := rxReg ## (shiftReg >> 1)
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bitsReg := bitsReg - 1.U
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// the last bit shifted in
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when(bitsReg === 1.U) {
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validReg := true.B
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}
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} .elsewhen(rxReg === 0.U) {
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// wait 1.5 bits after falling edge of start
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cntReg := START_CNT
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bitsReg := 8.U
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}
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when(validReg && io.channel.ready) {
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validReg := false.B
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}
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io.channel.bits := shiftReg
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io.channel.valid := validReg
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}
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//- end
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/**
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* A single byte buffer with a ready/valid interface
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*/
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class Buffer extends Module {
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val io = IO(new Bundle {
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val in = Flipped(new UartIO())
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val out = new UartIO()
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})
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object State extends ChiselEnum {
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val empty, full = Value
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}
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import State._
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val stateReg = RegInit(empty)
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val dataReg = RegInit(0.U(8.W))
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io.in.ready := stateReg === empty
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io.out.valid := stateReg === full
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when(stateReg === empty) {
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when(io.in.valid) {
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dataReg := io.in.bits
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stateReg := full
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}
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} .otherwise { // full
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when(io.out.ready) {
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stateReg := empty
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}
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}
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io.out.bits := dataReg
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}
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/*
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* Buffered uart receiver
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*/
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class UARTRx(frequency: Int, baudRate: Int) extends Module {
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val io = IO(new Bundle {
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val rxd = Input(UInt(1.W))
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val out = new UartIO()
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})
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val rx = Module(new Rx(frequency, baudRate))
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val buf = Module(new Buffer())
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val led = RegInit(0.U(8.W))
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rx.io.rxd := io.rxd
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rx.io.channel <> buf.io.in
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io.out <> buf.io.out
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}

‎src/main/scala/leros/uart/UARTTx.scala

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/*
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* Copyright: 2014-2018, Technical University of Denmark, DTU Compute
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* Author: Martin Schoeberl ([email protected])
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* License: Simplified BSD License
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*
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* A UART is a serial port, also called an RS232 interface.
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*
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*/
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package leros.uart
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import chisel3._
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import chisel3.util._
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import java.nio.file._
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/**
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* Transmit part of the UART.
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* A minimal version without any additional buffering.
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* Use a ready/valid handshaking.
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*/
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class Tx(frequency: Int, baudRate: Int) extends Module {
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val io = IO(new Bundle {
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val txd = Output(UInt(1.W))
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val channel = Flipped(new UartIO())
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})
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val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1).asUInt
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val shiftReg = RegInit(0x7ff.U)
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val cntReg = RegInit(0.U(20.W))
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val bitsReg = RegInit(0.U(4.W))
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io.channel.ready := (cntReg === 0.U) && (bitsReg === 0.U)
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io.txd := shiftReg(0)
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when(cntReg === 0.U) {
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cntReg := BIT_CNT
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when(bitsReg =/= 0.U) {
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val shift = shiftReg >> 1
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shiftReg := 1.U ## shift(9, 0)
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bitsReg := bitsReg - 1.U
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} .otherwise {
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when(io.channel.valid) {
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// two stop bits, data, one start bit
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shiftReg := 3.U ## io.channel.bits ## 0.U
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bitsReg := 11.U
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} .otherwise {
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shiftReg := 0x7ff.U
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}
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}
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} .otherwise {
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cntReg := cntReg - 1.U
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}
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}
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/**
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* A transmitter with a single buffer.
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*/
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class BufferedTx(frequency: Int, baudRate: Int) extends Module {
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val io = IO(new Bundle {
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val txd = Output(UInt(1.W))
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val channel = Flipped(new UartIO())
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})
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val tx = Module(new Tx(frequency, baudRate))
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val buf = Module(new Buffer())
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buf.io.in <> io.channel
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tx.io.channel <> buf.io.out
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io.txd <> tx.io.txd
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}
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/**
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* Send a string.
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*/
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class Sender(frequency: Int, baudRate: Int, msg : String) extends Module {
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val io = IO(new Bundle {
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val txd = Output(UInt(1.W))
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})
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val tx = Module(new BufferedTx(frequency, baudRate))
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io.txd := tx.io.txd
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val text = VecInit(msg.map(_.U))
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val len = msg.length.U
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val cntReg = RegInit(0.U(8.W))
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tx.io.channel.bits := text(cntReg)
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tx.io.channel.valid := cntReg =/= len
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when(tx.io.channel.ready && cntReg =/= len) {
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cntReg := cntReg + 1.U
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}
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}

‎src/main/scala/leros/wrmem/LerosWrMemTest.scala

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package leros.wrmem
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import chisel3._
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import chisel3.util._
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import leros._
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import leros.uart.Sender
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import leros.uart.Sender
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class LerosWrMemTest(clockFreq : Int = 100000000, uartBaudrate : Int = 115200, msg : String) extends Module {
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val io = IO(new Bundle {
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val instr = Output(UInt(16.W))
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})
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val programmer = Module(new Sender(clockFreq, uartBaudrate, msg))
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val wrInstrMem = Module(new WrInstrMemory(8, clockFreq, uartBaudrate))
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val idle :: programming :: readout :: Nil = Enum(3)
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val state = RegInit(idle)
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val pc = RegInit(0.U(8.W))
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wrInstrMem.io.instrAddr := pc
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wrInstrMem.io.uartRX := programmer.io.txd
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switch(state) {
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is(idle) {
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pc := 0.U
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when(wrInstrMem.io.busy) {
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state := programming
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}
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}
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is(programming) {
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when(~wrInstrMem.io.busy) {
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pc := pc + 1.U
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}
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}
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}
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io.instr := wrInstrMem.io.instr
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}

‎src/main/scala/leros/wrmem/ProgFSM.scala

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package leros.wrmem
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import chisel3._
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import chisel3.util._
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class ProgFSM(memAddrWidth : Int) extends Module {
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val io = IO(new Bundle {
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val channel = Flipped(new DecoupledIO(UInt(8.W)))
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val wrAddr = Output(UInt(memAddrWidth.W))
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val wrData = Output(UInt(16.W))
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val wrEna = Output(Bool())
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val busy = Output(Bool())
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})
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val PROGRAMMING_DONE = "h64".U(8.W)
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val idle :: sampleA :: sampleB :: writeMem :: Nil = Enum(4)
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val state = RegInit(idle)
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val wrAddr = RegInit(0.U(memAddrWidth.W))
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val increment = WireDefault(false.B)
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val wrDataA = RegInit(0.U(8.W))
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val wrDataB = RegInit(0.U(8.W))
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io.channel.ready := false.B
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io.wrEna := false.B
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io.busy := false.B
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switch(state) {
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is(idle) {
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io.wrEna := false.B
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io.channel.ready := false.B
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increment := false.B
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io.busy := false.B
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when(io.channel.valid) {
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state := sampleA
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}
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}
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is(sampleA) {
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io.wrEna := false.B
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io.channel.ready := true.B
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increment := false.B
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io.busy := true.B
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wrDataA := io.channel.bits
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when(wrDataA === PROGRAMMING_DONE) {
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state := idle
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}
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. elsewhen(io.channel.valid) {
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state := sampleB
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}
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}
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is(sampleB) {
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io.wrEna := false.B
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io.channel.ready := true.B
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increment := false.B
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io.busy := true.B
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wrDataB := io.channel.bits
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when(wrDataB === PROGRAMMING_DONE) {
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state := idle
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}
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. elsewhen(io.channel.valid) {
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state := writeMem
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}
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}
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is(writeMem) {
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io.wrEna := true.B
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io.channel.ready := false.B
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increment := true.B
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io.busy := true.B
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state := sampleA
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}
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}
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when(increment) {
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wrAddr := wrAddr + 1.U
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}
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// little endian
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io.wrData := wrDataB ## wrDataA
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io.wrAddr := wrAddr
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}

‎src/main/scala/leros/wrmem/WrInstrMem.scala

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package leros.wrmem
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import chisel3._
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import chisel3.util._
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import leros.uart.UARTRx
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import leros.uart.UARTRx
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class WrInstrMemory(memAddrWidth : Int, clockFreq : Int, uartBaudrate : Int) extends Module {
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val io = IO(new Bundle {
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val uartRX = Input(UInt(1.W))
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val instrAddr = Input(UInt(memAddrWidth.W))
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val instr = Output(UInt(16.W))
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val busy = Output(Bool())
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})
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val progFSM = Module(new ProgFSM(memAddrWidth))
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val uartRx = Module(new UARTRx(clockFreq, uartBaudrate))
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val wrAddr = WireDefault(0.U(memAddrWidth.W))
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val wrData = WireDefault(0.U(16.W))
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val wrEna = WireDefault(false.B)
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uartRx.io.out <> progFSM.io.channel
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uartRx.io.rxd := io.uartRX
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wrAddr := progFSM.io.wrAddr
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wrData := progFSM.io.wrData
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wrEna := progFSM.io.wrEna
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val mem = SyncReadMem(scala.math.pow(2, memAddrWidth).toInt, UInt(16.W))
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io.instr := mem.read(io.instrAddr)
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when(wrEna) {
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mem.write(wrAddr , wrData)
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}
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io.busy := progFSM.io.busy
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}

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