[Python][Disasm] Support SLL instructions.

Author: kosarev

tests/testsuite.py

@@ -11,6 +11,7 @@ def __str__(self):
 
     def runTest(self):
         TESTS = (
+            (b'\xcb\x30', 'sll b'),
             (b'\xdd\xe5', 'push ix'),
             (b'\xfd\xe1', 'pop iy'),
             (b'\xed\x50', 'in d, (c)'),

z80/__init__.py

@@ -11,7 +11,8 @@
 from ._error import Error
 from ._instr import (ADD, ADC, AND, CP, OR, SBC, SUB, XOR, BIT, CALL, CCF, CPL,
                      DAA, DEC, DI, DJNZ, EI, EX, EXX, HALT, IM, INC, IN, JP,
-                     JR, LD, LDDR, LDIR, NEG, NOP, RLC, RL, RR, RRC, SLA, SRA,
+                     JR, LD, LDDR, LDIR, NEG, NOP,
+                     RLC, RL, RR, RRC, SLA, SLL, SRA,
                      SRL, OUT, OUTI, POP, PUSH, RES, RET,
                      RLA, RLCA, RLD, RRA, RRCA,
                      RST, SCF, SET, A, AF, AF2, CF, M, NC, NZ, PO, P, Z, DE,

z80/_disasm.py

@@ -15,7 +15,8 @@
 from ._error import Error
 from ._instr import (ADD, ADC, AND, CP, OR, SBC, SUB, XOR, BIT, CALL, CCF, CPL,
                      DAA, DEC, DI, DJNZ, EI, EX, EXX, HALT, IM, INC, IN, JP,
-                     JR, LD, LDDR, LDIR, NEG, NOP, RLC, RL, RR, RRC, SLA, SRA,
+                     JR, LD, LDDR, LDIR, NEG, NOP,
+                     RLC, RL, RR, RRC, SLA, SLL, SRA,
                      SRL, OUT, OUTI, POP, PUSH, RES, RET,
                      RLA, RLCA, RLD, RRA, RRCA,
                      RST, SCF, SET, A, AF, AF2, CF, M, NC, NZ, PO, P, Z, DE,
@@ -168,6 +169,7 @@ class Z80InstrBuilder(object):
         'Orr': RR,
         'Orrc': RRC,
         'Osla': SLA,
+        'Osll': SLL,
         'Osra': SRA,
         'Osrl': SRL,
         'out': OUT,

z80/_instr.py

@@ -404,6 +404,10 @@ class SLA(Instr):
     pass
 
 
+class SLL(Instr):
+    pass
+
+
 class SRA(Instr):
     pass