From e3a5f1ea36668fa6111d0079a37a091539bc0599 Mon Sep 17 00:00:00 2001
From: Asherah Connor <ashe@kivikakk.ee>
Date: Thu, 23 May 2024 22:39:37 +0300
Subject: [PATCH] ChryseTop: clean up.

---
 .../ee/hrzn/chryse/platform/ChryseTop.scala    | 18 +++++++-----------
 .../hrzn/chryse/platform/ice40/ICE40Top.scala  |  6 ++----
 .../scala/ee/hrzn/chryse/tasks/BuildTask.scala |  2 +-
 .../platform/PlatformBoardResourcesSpec.scala  |  4 ++--
 4 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/src/main/scala/ee/hrzn/chryse/platform/ChryseTop.scala b/src/main/scala/ee/hrzn/chryse/platform/ChryseTop.scala
index 17edd5b..36aee88 100644
--- a/src/main/scala/ee/hrzn/chryse/platform/ChryseTop.scala
+++ b/src/main/scala/ee/hrzn/chryse/platform/ChryseTop.scala
@@ -1,23 +1,20 @@
 package ee.hrzn.chryse.platform
 
 import chisel3._
+import chisel3.experimental.noPrefix
 
 import scala.collection.mutable
 
 trait ChryseTop extends RawModule {
-  override def desiredName = "ice40top"
+  override def desiredName = "chrysetop"
 
   case class ConnectedResource(pin: resource.Pin, frequencyHz: Option[Int])
-  case class ConnectionResult(
-      connectedResources: Map[String, ConnectedResource],
-      clockIo: Clock,
-  )
 
   protected def connectResources(
       platform: PlatformBoard[_ <: PlatformBoardResources],
-  ): ConnectionResult = {
-    val connected              = mutable.Map[String, ConnectedResource]()
-    var clockIo: Option[Clock] = None
+      clock: Clock,
+  ): Map[String, ConnectedResource] = {
+    val connected = mutable.Map[String, ConnectedResource]()
 
     for { res <- platform.resources.all } {
       val name = res.name.get
@@ -33,8 +30,7 @@ trait ChryseTop extends RawModule {
             res.pinId.get,
             Some(platform.clockHz),
           )
-          val io = IO(Input(Clock())).suggestName(name)
-          clockIo = Some(io)
+          clock := noPrefix(IO(Input(Clock())).suggestName(name))
 
         case _ =>
           if (platformConnect(name, res)) {
@@ -46,7 +42,7 @@ trait ChryseTop extends RawModule {
       }
     }
 
-    ConnectionResult(connected.to(Map), clockIo.get)
+    connected.to(Map)
   }
 
   protected def platformConnect(
diff --git a/src/main/scala/ee/hrzn/chryse/platform/ice40/ICE40Top.scala b/src/main/scala/ee/hrzn/chryse/platform/ice40/ICE40Top.scala
index 5a8ad88..e089a17 100644
--- a/src/main/scala/ee/hrzn/chryse/platform/ice40/ICE40Top.scala
+++ b/src/main/scala/ee/hrzn/chryse/platform/ice40/ICE40Top.scala
@@ -53,10 +53,8 @@ class ICE40Top[Top <: Module](
 
   // TODO (iCE40): allow clock source override.
 
-  private val ConnectionResult(connectedResources, clockIo) =
-    connectResources(platform)
-
-  clki := clockIo
+  private val connectedResources =
+    connectResources(platform, clki)
 
   override protected def platformConnect(
       name: String,
diff --git a/src/main/scala/ee/hrzn/chryse/tasks/BuildTask.scala b/src/main/scala/ee/hrzn/chryse/tasks/BuildTask.scala
index 40cff46..5d7446f 100644
--- a/src/main/scala/ee/hrzn/chryse/tasks/BuildTask.scala
+++ b/src/main/scala/ee/hrzn/chryse/tasks/BuildTask.scala
@@ -53,7 +53,7 @@ object BuildTask extends BaseTask {
     writePath(
       yosysScriptPath,
       s"""read_verilog -sv $verilogPath
-         |synth_ice40 -top ice40top
+         |synth_ice40 -top chrysetop
          |write_json $jsonPath""".stripMargin,
     )
 
diff --git a/src/test/scala/ee/hrzn/chryse/platform/PlatformBoardResourcesSpec.scala b/src/test/scala/ee/hrzn/chryse/platform/PlatformBoardResourcesSpec.scala
index 439abe1..311f96d 100644
--- a/src/test/scala/ee/hrzn/chryse/platform/PlatformBoardResourcesSpec.scala
+++ b/src/test/scala/ee/hrzn/chryse/platform/PlatformBoardResourcesSpec.scala
@@ -73,7 +73,7 @@ class PlatformBoardResourcesSpec
     (rtl should include).regex(raw"\.view__ubtn_int\s*\(~ubtn\),")
 
     verilog.InterfaceExtractor(rtl) should contain(
-      "ice40top" -> verilog.InterfaceExtractor.Module(
+      "chrysetop" -> verilog.InterfaceExtractor.Module(
         inputs = Seq("clock", "ubtn"),
         outputs = Seq("uart_tx", "ledg"),
       ),
@@ -111,7 +111,7 @@ class PlatformBoardResourcesSpec
     (rtl should include).regex(raw"assign ledr = ~_top_ledr_int;")
 
     verilog.InterfaceExtractor(rtl) should contain(
-      "ice40top" -> verilog.InterfaceExtractor.Module(
+      "chrysetop" -> verilog.InterfaceExtractor.Module(
         inputs = Seq("clock", "ubtn", "uart_rx", "pmod1a2", "pmod1b2"),
         outputs = Seq("uart_tx", "ledr", "pmod1a1", "pmod1b1"),
       ),