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[reggen] Add initial support for version and cip_id hjson fields
This also extends the version number by one digit to conform to a semantic version format. Signed-off-by: Michael Schaffner <[email protected]>
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‎hw/ip/adc_ctrl/data/adc_ctrl.hjson

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@@ -11,11 +11,13 @@
1111
To enable usage while the device is sleeping, it runs on a slow always-on clock.
1212
In addition, it has a low power periodic scan mode for monitoring ADC channels.
1313
'''
14+
// Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool.
15+
cip_id: "1",
1416
design_spec: "../doc",
1517
dv_doc: "../doc/dv",
1618
hw_checklist: "../doc/checklist",
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sw_checklist: "/sw/device/lib/dif/dif_adc_ctrl",
18-
version: "1.0",
20+
version: "1.0.0",
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life_stage: "L1",
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design_stage: "D3",
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verification_stage: "V2S",

‎hw/ip/adc_ctrl/doc/registers.md

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‎hw/ip/aes/data/aes.hjson

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@@ -16,11 +16,13 @@
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[nist-aes]: https://www.nist.gov/publications/advanced-encryption-standard-aes
1818
'''
19+
// Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool.
20+
cip_id: "2",
1921
design_spec: "../doc",
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dv_doc: "../doc/dv",
2123
hw_checklist: "../doc/checklist",
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sw_checklist: "/sw/device/lib/dif/dif_aes",
23-
version: "1.0",
25+
version: "1.0.0",
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life_stage: "L1",
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design_stage: "D2S",
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verification_stage: "V2S",

‎hw/ip/aon_timer/data/aon_timer.hjson

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The wakeup timer has a 12-bit pre-scaler to enable very long timeouts and also generates an interrupt to the core.
1414
The timers run on a ~200 kHz AON clock and have a maximum timeout window of roughly ~6 hours for the watchdog timer and ~1000 days with the use of the pre-scaler for the wakeup timer.
1515
'''
16+
// Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool.
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cip_id: "3",
1618
design_spec: "../doc",
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dv_doc: "../doc/dv",
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hw_checklist: "../doc/checklist",
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sw_checklist: "/sw/device/lib/dif/dif_aon_timer",
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version: "1.0",
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version: "1.0.0",
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life_stage: "L1",
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design_stage: "D3",
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verification_stage: "V2S",

‎hw/ip/aon_timer/doc/registers.md

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@@ -3,112 +3,24 @@
33
<!-- BEGIN CMDGEN util/regtool.py -d ./hw/ip/aon_timer/data/aon_timer.hjson -->
44
## Summary
55

6-
| Name | Offset | Length | Description |
7-
|:--------------------------------------------------------------|:---------|---------:|:---------------------------------------|
8-
| aon_timer.[`CIP_ID`](#cip_id) | 0x0 | 4 | Comportable IP ID. |
9-
| aon_timer.[`REVISION`](#revision) | 0x4 | 4 | Comportable IP semantic version. |
10-
| aon_timer.[`PARAMETER_BLOCK_TYPE`](#parameter_block_type) | 0x8 | 4 | Parameter block type. |
11-
| aon_timer.[`PARAMETER_BLOCK_LENGTH`](#parameter_block_length) | 0xc | 4 | Parameter block length. |
12-
| aon_timer.[`NEXT_PARAMETER_BLOCK`](#next_parameter_block) | 0x10 | 4 | Next parameter block offset. |
13-
| aon_timer.[`ALERT_TEST`](#alert_test) | 0x40 | 4 | Alert Test Register |
14-
| aon_timer.[`WKUP_CTRL`](#wkup_ctrl) | 0x44 | 4 | Wakeup Timer Control register |
15-
| aon_timer.[`WKUP_THOLD`](#wkup_thold) | 0x48 | 4 | Wakeup Timer Threshold Register |
16-
| aon_timer.[`WKUP_COUNT`](#wkup_count) | 0x4c | 4 | Wakeup Timer Count Register |
17-
| aon_timer.[`WDOG_REGWEN`](#wdog_regwen) | 0x50 | 4 | Watchdog Timer Write Enable Register |
18-
| aon_timer.[`WDOG_CTRL`](#wdog_ctrl) | 0x54 | 4 | Watchdog Timer Control register |
19-
| aon_timer.[`WDOG_BARK_THOLD`](#wdog_bark_thold) | 0x58 | 4 | Watchdog Timer Bark Threshold Register |
20-
| aon_timer.[`WDOG_BITE_THOLD`](#wdog_bite_thold) | 0x5c | 4 | Watchdog Timer Bite Threshold Register |
21-
| aon_timer.[`WDOG_COUNT`](#wdog_count) | 0x60 | 4 | Watchdog Timer Count Register |
22-
| aon_timer.[`INTR_STATE`](#intr_state) | 0x64 | 4 | Interrupt State Register |
23-
| aon_timer.[`INTR_TEST`](#intr_test) | 0x68 | 4 | Interrupt Test Register |
24-
| aon_timer.[`WKUP_CAUSE`](#wkup_cause) | 0x6c | 4 | Wakeup request status |
25-
26-
## CIP_ID
27-
Comportable IP ID.
28-
- Offset: `0x0`
29-
- Reset default: `0x3`
30-
- Reset mask: `0xffffffff`
31-
32-
### Fields
33-
34-
```wavejson
35-
{"reg": [{"name": "CIP_ID", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
36-
```
37-
38-
| Bits | Type | Reset | Name | Description |
39-
|:------:|:------:|:-------:|:-------|:--------------------------------------------------|
40-
| 31:0 | ro | 0x3 | CIP_ID | This value is a unique comportable IP identifier. |
41-
42-
## REVISION
43-
Comportable IP semantic version.
44-
- Offset: `0x4`
45-
- Reset default: `0x2000000`
46-
- Reset mask: `0xffffffff`
47-
48-
### Fields
49-
50-
```wavejson
51-
{"reg": [{"name": "RESERVED", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "SUBMINOR", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "MINOR", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "MAJOR", "bits": 8, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
52-
```
53-
54-
| Bits | Type | Reset | Name | Description |
55-
|:------:|:------:|:-------:|:---------|:---------------------------------|
56-
| 31:24 | ro | 0x2 | MAJOR | Major version number. |
57-
| 23:16 | ro | 0x0 | MINOR | Minor version number. |
58-
| 15:8 | ro | 0x0 | SUBMINOR | Subminor (patch) version number. |
59-
| 7:0 | ro | 0x0 | RESERVED | Reserved version number. |
60-
61-
## PARAMETER_BLOCK_TYPE
62-
Parameter block type.
63-
- Offset: `0x8`
64-
- Reset default: `0x0`
65-
- Reset mask: `0xffffffff`
66-
67-
### Fields
68-
69-
```wavejson
70-
{"reg": [{"name": "BLOCK_TYPE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
71-
```
72-
73-
| Bits | Type | Reset | Name | Description |
74-
|:------:|:------:|:-------:|:-----------|:----------------------|
75-
| 31:0 | ro | 0x0 | BLOCK_TYPE | Parameter block type. |
76-
77-
## PARAMETER_BLOCK_LENGTH
78-
Parameter block length.
79-
- Offset: `0xc`
80-
- Reset default: `0xc`
81-
- Reset mask: `0xffffffff`
82-
83-
### Fields
84-
85-
```wavejson
86-
{"reg": [{"name": "BLOCK_LENGTH", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
87-
```
88-
89-
| Bits | Type | Reset | Name | Description |
90-
|:------:|:------:|:-------:|:-------------|:---------------------------------|
91-
| 31:0 | ro | 0xc | BLOCK_LENGTH | Parameter block length in bytes. |
92-
93-
## NEXT_PARAMETER_BLOCK
94-
Next parameter block offset.
95-
- Offset: `0x10`
96-
- Reset default: `0x0`
97-
- Reset mask: `0xffffffff`
98-
99-
### Fields
100-
101-
```wavejson
102-
{"reg": [{"name": "BLOCK_OFFSET", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
103-
```
104-
105-
| Bits | Type | Reset | Name | Description |
106-
|:------:|:------:|:-------:|:-------------|:----------------------------------------------------------------------------------------|
107-
| 31:0 | ro | 0x0 | BLOCK_OFFSET | This offset value is zero if there is no other parameter block. |
6+
| Name | Offset | Length | Description |
7+
|:------------------------------------------------|:---------|---------:|:---------------------------------------|
8+
| aon_timer.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register |
9+
| aon_timer.[`WKUP_CTRL`](#wkup_ctrl) | 0x4 | 4 | Wakeup Timer Control register |
10+
| aon_timer.[`WKUP_THOLD`](#wkup_thold) | 0x8 | 4 | Wakeup Timer Threshold Register |
11+
| aon_timer.[`WKUP_COUNT`](#wkup_count) | 0xc | 4 | Wakeup Timer Count Register |
12+
| aon_timer.[`WDOG_REGWEN`](#wdog_regwen) | 0x10 | 4 | Watchdog Timer Write Enable Register |
13+
| aon_timer.[`WDOG_CTRL`](#wdog_ctrl) | 0x14 | 4 | Watchdog Timer Control register |
14+
| aon_timer.[`WDOG_BARK_THOLD`](#wdog_bark_thold) | 0x18 | 4 | Watchdog Timer Bark Threshold Register |
15+
| aon_timer.[`WDOG_BITE_THOLD`](#wdog_bite_thold) | 0x1c | 4 | Watchdog Timer Bite Threshold Register |
16+
| aon_timer.[`WDOG_COUNT`](#wdog_count) | 0x20 | 4 | Watchdog Timer Count Register |
17+
| aon_timer.[`INTR_STATE`](#intr_state) | 0x24 | 4 | Interrupt State Register |
18+
| aon_timer.[`INTR_TEST`](#intr_test) | 0x28 | 4 | Interrupt Test Register |
19+
| aon_timer.[`WKUP_CAUSE`](#wkup_cause) | 0x2c | 4 | Wakeup request status |
10820

10921
## ALERT_TEST
11022
Alert Test Register
111-
- Offset: `0x40`
23+
- Offset: `0x0`
11224
- Reset default: `0x0`
11325
- Reset mask: `0x1`
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@@ -125,7 +37,7 @@ Alert Test Register
12537

12638
## WKUP_CTRL
12739
Wakeup Timer Control register
128-
- Offset: `0x44`
40+
- Offset: `0x4`
12941
- Reset default: `0x0`
13042
- Reset mask: `0x1fff`
13143

@@ -143,7 +55,7 @@ Wakeup Timer Control register
14355

14456
## WKUP_THOLD
14557
Wakeup Timer Threshold Register
146-
- Offset: `0x48`
58+
- Offset: `0x8`
14759
- Reset default: `0x0`
14860
- Reset mask: `0xffffffff`
14961

@@ -159,7 +71,7 @@ Wakeup Timer Threshold Register
15971

16072
## WKUP_COUNT
16173
Wakeup Timer Count Register
162-
- Offset: `0x4c`
74+
- Offset: `0xc`
16375
- Reset default: `0x0`
16476
- Reset mask: `0xffffffff`
16577

@@ -175,7 +87,7 @@ Wakeup Timer Count Register
17587

17688
## WDOG_REGWEN
17789
Watchdog Timer Write Enable Register
178-
- Offset: `0x50`
90+
- Offset: `0x10`
17991
- Reset default: `0x1`
18092
- Reset mask: `0x1`
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@@ -192,7 +104,7 @@ Watchdog Timer Write Enable Register
192104

193105
## WDOG_CTRL
194106
Watchdog Timer Control register
195-
- Offset: `0x54`
107+
- Offset: `0x14`
196108
- Reset default: `0x0`
197109
- Reset mask: `0x3`
198110
- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
@@ -211,7 +123,7 @@ Watchdog Timer Control register
211123

212124
## WDOG_BARK_THOLD
213125
Watchdog Timer Bark Threshold Register
214-
- Offset: `0x58`
126+
- Offset: `0x18`
215127
- Reset default: `0x0`
216128
- Reset mask: `0xffffffff`
217129
- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
@@ -228,7 +140,7 @@ Watchdog Timer Bark Threshold Register
228140

229141
## WDOG_BITE_THOLD
230142
Watchdog Timer Bite Threshold Register
231-
- Offset: `0x5c`
143+
- Offset: `0x1c`
232144
- Reset default: `0x0`
233145
- Reset mask: `0xffffffff`
234146
- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
@@ -245,7 +157,7 @@ Watchdog Timer Bite Threshold Register
245157

246158
## WDOG_COUNT
247159
Watchdog Timer Count Register
248-
- Offset: `0x60`
160+
- Offset: `0x20`
249161
- Reset default: `0x0`
250162
- Reset mask: `0xffffffff`
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@@ -261,7 +173,7 @@ Watchdog Timer Count Register
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262174
## INTR_STATE
263175
Interrupt State Register
264-
- Offset: `0x64`
176+
- Offset: `0x24`
265177
- Reset default: `0x0`
266178
- Reset mask: `0x3`
267179

@@ -279,7 +191,7 @@ Interrupt State Register
279191

280192
## INTR_TEST
281193
Interrupt Test Register
282-
- Offset: `0x68`
194+
- Offset: `0x28`
283195
- Reset default: `0x0`
284196
- Reset mask: `0x3`
285197

@@ -297,7 +209,7 @@ Interrupt Test Register
297209

298210
## WKUP_CAUSE
299211
Wakeup request status
300-
- Offset: `0x6c`
212+
- Offset: `0x2c`
301213
- Reset default: `0x0`
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- Reset mask: `0x1`
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‎hw/ip/clkmgr/data/clkmgr.hjson

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For example, the idle status of relevant hardware blocks is tracked and clock gating requests from software are ignored as long as these blocks are active.
2020
Further security features include switchable clock jitter, continuous monitoring of clock frequencies, and various countermeasures to deter fault injection (FI) attacks.
2121
'''
22+
// Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool.
23+
cip_id: "4",
2224
design_spec: "../doc",
2325
dv_doc: "../doc/dv",
2426
hw_checklist: "../doc/checklist",
2527
sw_checklist: "/sw/device/lib/dif/dif_clkmgr",
2628
revisions: [
2729
{
28-
version: "1.0",
30+
version: "1.0.0",
2931
life_stage: "L1",
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design_stage: "D1",
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verification_stage: "V1",

‎hw/ip/clkmgr/data/clkmgr.hjson.tpl

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For example, the idle status of relevant hardware blocks is tracked and clock gating requests from software are ignored as long as these blocks are active.
1616
Further security features include switchable clock jitter, continuous monitoring of clock frequencies, and various countermeasures to deter fault injection (FI) attacks.
1717
'''
18+
// Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool.
19+
cip_id: "4",
1820
design_spec: "../doc",
1921
dv_doc: "../doc/dv",
2022
hw_checklist: "../doc/checklist",
2123
sw_checklist: "/sw/device/lib/dif/dif_clkmgr",
2224
revisions: [
2325
{
24-
version: "1.0",
26+
version: "1.0.0",
2527
life_stage: "L1",
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design_stage: "D2S",
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verification_stage: "V2S",

‎hw/ip/csrng/data/csrng.hjson

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[nist-sp-800-90a]: https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-90Ar1.pdf
1515
[nist-sp-800-90c]: https://csrc.nist.gov/CSRC/media/Publications/sp/800-90c/draft/documents/sp800_90c_second_draft.pdf
1616
'''
17+
// Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool.
18+
cip_id: "5",
1719
design_spec: "../doc",
1820
dv_doc: "../doc/dv",
1921
hw_checklist: "../doc/checklist",
2022
sw_checklist: "/sw/device/lib/dif/dif_csrng",
21-
version: "1.0",
23+
version: "1.0.0",
2224
life_stage: "L1",
2325
design_stage: "D2S",
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verification_stage: "V2S",

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