More exit cleanup.

Hex routing avoids board edges.
Preflight checks 0.4mm GTL/GBL to edge

Author: jamesbowman

hexboard.py

@@ -120,10 +120,42 @@ def hex_setup(self):
             shapely.points(coordinates), self.route_radius, quad_segs=16)
         self.route_tree = STRtree(route_disks)
         self.route_point_tree = STRtree(shapely.points(coordinates))
+        self.route_outline = (
+            self.outline_polygon if self.outline_polygon is not None
+            else sg.box(0, 0, *self.size))
+        outlines = self.layers['GML'].lines
+        if outlines:
+            self.route_outline = max(
+                (sg.Polygon(line) for line in outlines), key=lambda p: p.area)
+        self.edge_block_cache = {}
         self.blocked = {layer: self.layer_blocks(layer) for layer in ('GTL', 'GBL')}
         self.routes = []
         self.route_widths = []
 
+    def edge_blocks(self, width):
+        """Reserve trace radius and edge clearance against the perimeter.
+
+        Convex insets contain the segments between allowed centers. Concave
+        outlines need an extra half-step margin to protect those segments.
+        """
+        clearance = float(getattr(self, "hex_edge_clearance", 0))
+        assert math.isfinite(clearance) and clearance >= 0
+        key = (width, clearance)
+        if key not in self.edge_block_cache:
+            segment_margin = (
+                0 if self.route_outline.equals(self.route_outline.convex_hull)
+                else self.hr)
+            interior = self.route_outline.buffer(
+                -(clearance + width / 2 + segment_margin))
+            blocked = self.gr.zeros(np.uint8) | (self.gr.valid == 0)
+            points = shapely.points([h.to_plane() for h in self.route_hexes])
+            inside = shapely.covers(interior, points)
+            for h, allowed in zip(self.route_hexes, inside):
+                if not allowed:
+                    blocked[h.q, h.r] = 1
+            self.edge_block_cache[key] = blocked
+        return self.edge_block_cache[key].copy()
+
     def layer_blocks(
             self, nm, width=None, exempt_points=(),
             exempt_geometries=()):
@@ -155,7 +187,7 @@ def layer_blocks(
             layer_poly = so.unary_union(
                 copper + drill_keepouts + self.keepouts +
                 self.route_keepouts[nm]).buffer(0)
-            blocked = self.gr.zeros(np.uint8) | (self.gr.valid == 0)
+            blocked = self.edge_blocks(width)
             for i in self.route_tree.query(
                     layer_poly, predicate="intersects"):
                 h = self.route_hexes[i]
@@ -169,7 +201,7 @@ def layer_blocks(
             fixed_geometry = fixed_geometry.buffer(geometry_expansion)
         layer_poly = so.unary_union(
             [fixed_geometry] + drill_keepouts).buffer(0)
-        blocked = self.gr.zeros(np.uint8) | (self.gr.valid == 0)
+        blocked = self.edge_blocks(width)
         for i in self.route_tree.query(layer_poly, predicate="intersects"):
             h = self.route_hexes[i]
             blocked[h.q, h.r] = 1
@@ -247,6 +279,11 @@ def _hex_route_pad_endpoints(self, a, b):
             self.pad_hex_cells(b)
             if isinstance(b, PadEndpoint)
             else frozenset((tuple(Hex.from_xy(*target.xy)),)))
+        edge_blocked = self.edge_blocks(self.trace)
+        for endpoint, cells in ((a, source_cells), (b, target_cells)):
+            if not isinstance(endpoint, PadEndpoint):
+                assert all(not edge_blocked[q, r] for q, r in cells), (
+                    "Route endpoint violates board-edge clearance")
         exempt_geometries = tuple(
             endpoint.draw.boundary
             for endpoint in (a, b)
@@ -313,6 +350,9 @@ def hex_route(self, a, b):
         target = b
         a = Hex.from_xy(*source.xy)
         b = Hex.from_xy(*target.xy)
+        edge_blocked = self.edge_blocks(self.trace)
+        assert not edge_blocked[a.q, a.r] and not edge_blocked[b.q, b.r], (
+            "Route endpoint violates board-edge clearance")
 
         wavefront = set([tuple(a)])
         dirs = [Hex(dq,dr) for (dq, dr) in axial_direction_vectors]
@@ -381,6 +421,11 @@ def hex_route_net(self, terminals, width=None):
              else frozenset((tuple(Hex.from_xy(*draw.xy)),)))
             for terminal, draw in zip(terminals, draws)
         ]
+        edge_blocked = self.edge_blocks(route_width)
+        for terminal, cells in zip(terminals, endpoint_cells):
+            if not isinstance(terminal, PadEndpoint):
+                assert all(not edge_blocked[q, r] for q, r in cells), (
+                    "Route endpoint violates board-edge clearance")
         exempt_geometries = tuple(
             terminal.draw.boundary
             for terminal in terminals

preflight/spiq_a.json

@@ -30,6 +30,7 @@
   "excluded_designators": ["J4", "U3"],
   "expected_gml_contours": 5,
   "expected_gml_contours_reason": "one rounded board perimeter plus J1's four plated USB-C mounting slots",
+  "copper_edge_clearance_mm": {"GTL": 0.4, "GBL": 0.4},
   "topology": {
     "copper_layers": ["GTL", "G2L", "G3L", "GBL"],
     "net_clearance_mm": 0.1,

spiq_a.py

@@ -416,6 +416,7 @@ def spiq_a():
         via_space = cu.mil(5),
         silk = cu.mil(5))
     brd.hex_clearance = 0.100
+    brd.hex_edge_clearance = 0.400
 
     def spiq_logo():
         x0, y0 = (0.9, 0.9)
@@ -798,13 +799,13 @@ def ldo_cap(
         brd.hex_route(u1.s("QSPI_SCLK"), brd.pad_endpoint(u2.s("CLK")))
         brd.hex_route(u1.s("QSPI_SD3"), brd.pad_endpoint(u2.s("IO3")))
 
-        brd.hex_route(u1.s("USB_DM"), brd.pad_endpoint(r7.pads[1]))
         brd.hex_route(u1.s("USB_DP"), brd.pad_endpoint(r8.pads[1]))
+        brd.hex_route(u1.s("USB_DM"), brd.pad_endpoint(r7.pads[1]))
         brd.hex_route(u1.s("XIN"), brd.pad_endpoint(y1.s("CLK")))
 
         brd.hex_route(u1.s("SWCLK"), brd.pad_endpoint(j4.s("SWCLK")))
-        brd.hex_route(u1.s("GPIO0"), brd.pad_endpoint(j4.s("TX")))
         brd.hex_route(u1.s("GPIO1"), brd.pad_endpoint(j4.s("RX")))
+        brd.hex_route(u1.s("GPIO0"), brd.pad_endpoint(j4.s("TX")))
         brd.hex_route(u1.s("SWDIO"), brd.pad_endpoint(j4.s("SWDIO")))
 
         for (a, b) in zip(bus, j3.pads):

tests/test_hexboard.py

@@ -30,6 +30,39 @@ def terminals(self, board):
             result.append(terminal)
         return tuple(result)
 
+    def test_edge_blocks_follow_outline_on_both_layers(self):
+        board = self.board()
+        board.outline_polygon = sg.Polygon([
+            (0, 3), (3, 0), (12, 0), (12, 12), (0, 12)])
+        board.hex_edge_clearance = 0.4
+        board.hex_setup()
+        corner = Hex.from_xy_fine(1, 1)
+        inside = Hex.from_xy_fine(6, 6)
+        for layer in ("GTL", "GBL"):
+            self.assertTrue(board.blocked[layer][corner.q, corner.r])
+            self.assertFalse(board.blocked[layer][inside.q, inside.r])
+
+    def test_wide_routes_reserve_more_edge_space(self):
+        board = self.board()
+        board.hex_edge_clearance = 0.4
+        narrow = board.edge_blocks(0.1)
+        wide = board.edge_blocks(0.8)
+        self.assertTrue(any(
+            wide[h.q, h.r] and not narrow[h.q, h.r]
+            for h in board.route_hexes))
+
+    def test_point_and_net_endpoints_cannot_override_edge_blocks(self):
+        board = self.board()
+        board.hex_edge_clearance = 0.4
+        board.hex_setup()
+        a, b, c = self.terminals(board)
+        a.xy = Hex.from_xy_fine(0.1, 6).to_plane()
+        for source, target in ((a, b), (b, a)):
+            with self.assertRaisesRegex(AssertionError, "board-edge"):
+                board.hex_route(source, target)
+        with self.assertRaisesRegex(AssertionError, "board-edge"):
+            board.hex_route_net((a, b, c))
+
     def test_default_width_preserves_single_cell_occupancy(self):
         board = self.board()
         before = board.blocked["GTL"].copy()

tests/test_pcb_preflight_edges.py

@@ -0,0 +1,72 @@
+import tempfile
+import unittest
+from pathlib import Path
+from unittest.mock import patch
+
+import shapely.geometry as sg
+
+from tools import pcb_preflight
+
+
+def gerber(*polygons):
+    lines = ["%MOMM*%", "%FSLAX34Y34*%", "%LPD*%"]
+    for polygon in polygons:
+        lines.append("G36*")
+        for i, (x, y) in enumerate(polygon.exterior.coords):
+            lines.append(
+                f"X{round(x * 10000):07d}Y{round(y * 10000):07d}"
+                f"D{2 if i == 0 else 1:02d}*")
+        lines.append("G37*")
+    return "\n".join(lines) + "\nM02*\n"
+
+
+class CopperEdgeTests(unittest.TestCase):
+    def check_copper(self, copper, outline=None, slots=()):
+        if outline is None:
+            outline = sg.box(0, 0, 10, 10)
+        with tempfile.TemporaryDirectory() as directory:
+            root = Path(directory)
+            (root / "board.GML").write_text(gerber(outline, *slots))
+            (root / "board.GTL").write_text(gerber(*copper))
+            audit = pcb_preflight.Audit()
+            with patch.object(pcb_preflight, "ROOT", root):
+                pcb_preflight.audit_copper_edges(audit, {
+                    "board": "board",
+                    "copper_edge_clearance_mm": {"GTL": 0.4},
+                })
+            return audit
+
+    def test_exact_clearance_passes(self):
+        self.assertTrue(self.check_copper([sg.box(.4, .4, 9.6, 9.6)]).passed)
+
+    def test_isolated_artwork_too_close_fails(self):
+        audit = self.check_copper([
+            sg.box(2, 2, 8, 8), sg.box(.3, 4, .35, 4.1)])
+        self.assertFalse(audit.passed)
+        self.assertIn("0.3000 mm", audit.checks[0].detail)
+
+    def test_entirely_external_copper_fails(self):
+        audit = self.check_copper([sg.box(11, 4, 12, 5)])
+        self.assertFalse(audit.passed)
+        self.assertIn("outside board", audit.checks[0].detail)
+
+    def test_actual_perimeter_not_bounding_box(self):
+        # A chamfered corner cuts through this otherwise safely inset pad.
+        outline = sg.Polygon([(0, 2), (2, 0), (10, 0), (10, 10), (0, 10)])
+        self.assertFalse(self.check_copper(
+            [sg.box(.5, .5, 1, 1)], outline).passed)
+
+    def test_internal_plated_slot_not_treated_as_outer_edge(self):
+        self.assertTrue(self.check_copper(
+            [sg.box(3.9, 3.9, 6.1, 6.1)],
+            slots=[sg.box(4, 4, 6, 6)]).passed)
+
+    def test_missing_outline_fails_closed(self):
+        with tempfile.TemporaryDirectory() as directory:
+            audit = pcb_preflight.Audit()
+            with patch.object(pcb_preflight, "ROOT", Path(directory)):
+                pcb_preflight.audit_copper_edges(audit, {
+                    "board": "missing",
+                    "copper_edge_clearance_mm": {"GBL": 0.4},
+                })
+            self.assertFalse(audit.passed)

tools/pcb_preflight.py

@@ -442,6 +442,63 @@ def audit_manufacturing_files(
             )
 
 
+def audit_copper_edges(audit: Audit, profile: dict[str, Any]) -> None:
+    """Check all copper, including artwork, against the outer GML perimeter."""
+    limits = profile.get("copper_edge_clearance_mm")
+    if not limits:
+        return
+    import shapely.geometry as sg
+    from shapely.ops import nearest_points
+    if __package__:
+        from .pcb_topology import (
+            TopologyFormatError, parse_cuflow_gerber, parse_cuflow_paths_text)
+    else:
+        from pcb_topology import (
+            TopologyFormatError, parse_cuflow_gerber, parse_cuflow_paths_text)
+
+    board = profile["board"]
+    try:
+        paths = parse_cuflow_paths_text(
+            (ROOT / f"{board}.GML").read_text(encoding="ascii"))
+        if not paths or any(not path.is_ring for path in paths):
+            raise ValueError("GML must contain closed, simple contours")
+        # Internal slots have separate rules, particularly plated slots.
+        perimeter = max((sg.Polygon(path) for path in paths),
+                        key=lambda polygon: polygon.area)
+        if not perimeter.is_valid or perimeter.area <= 0:
+            raise ValueError("invalid outer GML perimeter")
+    except (OSError, ValueError, TopologyFormatError) as error:
+        audit.add("Copper-to-board-edge clearance", False,
+                  f"cannot read perimeter: {error}")
+        return
+
+    for layer, limit in limits.items():
+        name = f"{layer} copper-to-board-edge clearance"
+        try:
+            clearance = float(limit)
+            if not math.isfinite(clearance) or clearance < 0:
+                raise ValueError("clearance must be finite and nonnegative")
+            copper = parse_cuflow_gerber(ROOT / f"{board}.{layer}")
+            if copper.is_empty:
+                audit.add(name, True, "no copper on layer")
+                continue
+            outside = copper.difference(perimeter)
+            if not outside.is_empty:
+                point = outside.representative_point()
+                audit.add(name, False,
+                          f"copper outside board at ({point.x:.3f}, "
+                          f"{point.y:.3f}) mm; needs {clearance:.3f} mm inset")
+                continue
+            distance = copper.distance(perimeter.boundary)
+            point, _ = nearest_points(copper, perimeter.boundary)
+            audit.add(name, distance + 1e-9 >= clearance,
+                      f"minimum {distance:.4f} mm; needs {clearance:.3f} mm; "
+                      f"nearest copper at ({point.x:.3f}, {point.y:.3f}) mm "
+                      "(includes unconnected artwork)")
+        except (OSError, ValueError, TopologyFormatError) as error:
+            audit.add(name, False, f"cannot check copper: {error}")
+
+
 def audit_copper_topology(
         audit: Audit, profile: dict[str, Any]) -> None:
     config = profile.get("topology")
@@ -1794,6 +1851,7 @@ def main() -> int:
     catalog = load_catalog(audit, relative_path(profile["part_catalog"]))
     audit_bom_and_pnp(audit, profile, catalog)
     audit_manufacturing_files(audit, profile)
+    audit_copper_edges(audit, profile)
     audit_copper_topology(audit, profile)
 
     report_path = args.report or ROOT / f"{args.board}-preflight.html"