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jaqchenwkz
jaqchen
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wkz
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arch: Add support for mips architecture
There exists mainly two variants of ABIs in the linux kernel for MIPS architecture, o32 and n32/n64. Configure option `CFLAGS=-DUSE_MIPS_N32 can be specified to enable n32/n64 kernel ABI. Note that only support for 32-bit MIPS architecture is added.
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‎configure.ac

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@@ -39,6 +39,7 @@ AC_SUBST(arch)
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AS_CASE($host_cpu,
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arm*, arch=arm,
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mips*, arch=mips,
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arch=$host_cpu)
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AC_OUTPUT

‎src/libply/arch/mips.c

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/*
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* Copyright Tobias Waldekranz <[email protected]>
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* Copyright Ye Jiaqiang <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <assert.h>
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#include <ply/internal.h>
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#define arch_typedef(_a, _t) { \
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.ttype = T_TYPEDEF, \
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.tdef = { .name = #_a, .type = _t }, \
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}
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struct type t_s8 = arch_typedef(s8, &t_schar);
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struct type t_u8 = arch_typedef(u8, &t_uchar);
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struct type t_s16 = arch_typedef(s16, &t_sshort);
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struct type t_u16 = arch_typedef(u16, &t_ushort);
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struct type t_s32 = arch_typedef(s32, &t_sint);
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struct type t_u32 = arch_typedef(u32, &t_uint);
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struct type t_s64 = arch_typedef(s64, &t_sllong);
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struct type t_u64 = arch_typedef(u64, &t_ullong);
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static int reg_fprint(struct type *t, FILE *fp, const void *data)
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{
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return fprintf(fp, "%#lx", *((unsigned long *)data));
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}
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struct type t_reg_t = {
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.ttype = T_TYPEDEF,
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.tdef = {
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.name = "reg_t",
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.type = &t_ulong,
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},
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.fprint = reg_fprint,
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};
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struct tfield f_pt_regs_fields[] = {
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/*
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* Only 32-bit MIPS architecture is supported.
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* 8 userspace registers padding, which is mandatory for MIPS32.
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* Refer to linux/arch/mips/include/asm/ptrace.h
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*/
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{ .name = "uarg0", .type = &t_reg_t },
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{ .name = "uarg1", .type = &t_reg_t },
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{ .name = "uarg2", .type = &t_reg_t },
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{ .name = "uarg3", .type = &t_reg_t },
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{ .name = "uarg4", .type = &t_reg_t },
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{ .name = "uarg5", .type = &t_reg_t },
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{ .name = "uarg6", .type = &t_reg_t },
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{ .name = "uarg7", .type = &t_reg_t },
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{ .name = "zero", .type = &t_reg_t }, /* $0 */
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{ .name = "at", .type = &t_reg_t }, /* $1 */
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{ .name = "v0", .type = &t_reg_t }, /* $2 */
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{ .name = "v1", .type = &t_reg_t }, /* $3 */
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{ .name = "a0", .type = &t_reg_t }, /* $4 */
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{ .name = "a1", .type = &t_reg_t }, /* $5 */
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{ .name = "a2", .type = &t_reg_t }, /* $6 */
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{ .name = "a3", .type = &t_reg_t }, /* $7 */
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#ifndef USE_MIPS_N32 /* o32 ABI */
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{ .name = "t0", .type = &t_reg_t }, /* $8 */
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{ .name = "t1", .type = &t_reg_t }, /* $9 */
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{ .name = "t2", .type = &t_reg_t }, /* $10 */
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{ .name = "t3", .type = &t_reg_t }, /* $11 */
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#else /* n32 or native 64-bit ABI */
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{ .name = "a4", .type = &t_reg_t }, /* $8 */
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{ .name = "a5", .type = &t_reg_t }, /* $9 */
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{ .name = "a6", .type = &t_reg_t }, /* $10 */
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{ .name = "a7", .type = &t_reg_t }, /* $11 */
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#endif
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{ .name = "t4", .type = &t_reg_t }, /* $12 */
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{ .name = "t5", .type = &t_reg_t }, /* $13 */
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{ .name = "t6", .type = &t_reg_t }, /* $14 */
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{ .name = "t7", .type = &t_reg_t }, /* $15 */
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{ .name = "s0", .type = &t_reg_t }, /* $16 */
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{ .name = "s1", .type = &t_reg_t }, /* $17 */
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{ .name = "s2", .type = &t_reg_t }, /* $18 */
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{ .name = "s3", .type = &t_reg_t }, /* $19 */
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{ .name = "s4", .type = &t_reg_t }, /* $20 */
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{ .name = "s5", .type = &t_reg_t }, /* $21 */
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{ .name = "s6", .type = &t_reg_t }, /* $22 */
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{ .name = "s7", .type = &t_reg_t }, /* $23 */
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{ .name = "t8", .type = &t_reg_t }, /* $24 */
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{ .name = "t9", .type = &t_reg_t }, /* $25 */
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{ .name = "k0", .type = &t_reg_t }, /* $26 */
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{ .name = "k1", .type = &t_reg_t }, /* $27 */
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{ .name = "gp", .type = &t_reg_t }, /* $28 */
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{ .name = "sp", .type = &t_reg_t }, /* $29 */
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{ .name = "fp", .type = &t_reg_t }, /* $30, or s8 */
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{ .name = "ra", .type = &t_reg_t }, /* $31 */
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{ .name = "cp0_status", .type = &t_reg_t },
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{ .name = "hi", .type = &t_reg_t },
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{ .name = "lo", .type = &t_reg_t },
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/*
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* Uncomment next line for register `acx, which is rarely
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* enabled via CONFIG_CPU_HAS_SMARTMIPS kernel option:
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*/
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/* { .name = "acx", .type = &t_reg_t }, */
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{ .name = "cp0_badvaddr", .type = &t_reg_t },
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{ .name = "cp0_cause", .type = &t_reg_t },
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{ .name = "cp0_epc", .type = &t_reg_t },
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{ .name = NULL, .type = NULL }
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};
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struct type t_pt_regs = {
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.ttype = T_STRUCT,
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.sou = {
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.name = "pt_regs",
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.fields = f_pt_regs_fields,
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},
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};
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struct type *arch_types[] = {
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&t_s8, &t_u8,
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&t_s16, &t_u16,
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&t_s32, &t_u32,
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&t_s64, &t_u64,
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&t_reg_t, &t_pt_regs,
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NULL
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};
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const char *arch_register_argument(int num)
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{
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switch (num) {
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case 0: return "a0";
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case 1: return "a1";
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case 2: return "a2";
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case 3: return "a3";
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#ifdef USE_MIPS_N32
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case 4: return "a4";
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case 5: return "a5";
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case 6: return "a6";
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case 7: return "a7";
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#endif
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default:
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break;
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}
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return NULL;
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}
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const char *arch_register_pc(void)
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{
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return "cp0_epc";
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}
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const char *arch_register_return(void)
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{
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return "v0";
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}
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__attribute__((constructor))
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static void arch_init(void)
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{
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type_struct_layout(&t_pt_regs);
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type_add_list(arch_types);
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}

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