Preparing to release v0.6.3 (#563)

Author: mkorbel1

CHANGELOG.md

@@ -1,3 +1,8 @@
+## 0.6.3
+
+- Fixed a bug where `withSet` on `LogicStructure`s could sometimes attempt to access the wrong range, causing unexpected exceptions (<https://github.com/intel/rohd/pull/561>).
+- Fixed a bug where `flop` and `FlipFlop` would generate SystemVerilog with an asynchronous reset even if `asyncReset` was set to `false` (<https://github.com/intel/rohd/pull/564>).
+
 ## 0.6.2
 
 - Changed addition syntax for generated SystemVerilog to be prettier, while remaining lint-clean (<https://github.com/intel/rohd/issues/444>).

lib/src/utilities/config.dart

@@ -10,5 +10,5 @@
 /// A utility for ROHD configuration file.
 class Config {
   /// The version of the ROHD framework.
-  static const String version = '0.6.2';
+  static const String version = '0.6.3';
 }

pubspec.yaml

@@ -1,5 +1,5 @@
 name: rohd
-version: 0.6.2
+version: 0.6.3
 description: The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware.
 homepage: https://intel.github.io/rohd-website
 repository: https://github.com/intel/rohd