Preparing to release v0.5.2

Author: mkorbel1

CHANGELOG.md

@@ -1,3 +1,19 @@
+## 0.5.2
+
+- Added APIs for accessing indices of a `List<Logic>` using another `Logic`: `Logic.selectFrom` and `List<Logic>.selectIndex`.
+- Added/fixed support for compiling ROHD to JavaScript via bug fixes, compile-time arithmetic precision consideration, and testing (<https://github.com/intel/rohd/pull/445>).
+- Added `isZero` to `LogicValue`.
+- Improved `Pipeline` abstraction via bug fixes, better error checking, improved documentation, and new APIs (<https://github.com/intel/rohd/pull/447>).
+- Improved performance of construction of `Combinational.ssa` (<https://github.com/intel/rohd/pull/443>).
+- Updated `Simulator.endSimulation` API to return a `Future` which completes once the simulation has ended (<https://github.com/intel/rohd/pull/455>).
+- Fixed bugs where certain non-synthesizable function calls on `LogicStructure`s (e.g. for verification) could add additional hardware (which did not affect functionality) and also cause unexpected behavior on `previousValue` (<https://github.com/intel/rohd/issues/457>).
+- Fixed bugs where certain APIs on `Logic` (e.g. `changed`, `previousValue`) could have incorrect behavior after a `Simulator.reset` (<https://github.com/intel/rohd/pull/458>).
+- Fixed a bug where `LogicValue.clog2` was inaccurate in rare scenarios.
+- Fixed a bug that caused a crash when comparing certain `LogicValue`s.
+- Fixed a bug where conversions between `BigInt`s and `LogicValue`s could result in incorrect arithmetic operations.
+- Fixed a bug where `FiniteStateMachine`-generated mermaid diagrams were missing "default next state" cases (<https://github.com/intel/rohd/pull/454>).
+- Allowed generated SystemVerilog to contain assignments to `z` (floating) if explicitly connected to a constant `z` (<https://github.com/intel/rohd/pull/441>).
+
 ## 0.5.1
 
 - Fixed bugs and improved controllability around naming of internal signals and collapsing of inlineable functionality, leading to significantly more readable generated SystemVerilog (<https://github.com/intel/rohd/pull/439>).

lib/src/utilities/config.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2022-2023 Intel Corporation
+// Copyright (C) 2022-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // config.dart
@@ -10,5 +10,5 @@
 /// A utility for ROHD configuration file.
 class Config {
   /// The version of the ROHD framework.
-  static const String version = '0.5.1';
+  static const String version = '0.5.2';
 }

pubspec.yaml

@@ -1,6 +1,6 @@
 name: rohd
-version: 0.5.1
-description: The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware
+version: 0.5.2
+description: The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware.
 homepage: https://intel.github.io/rohd-website
 repository: https://github.com/intel/rohd
 issue_tracker: https://github.com/intel/rohd/issues