This commit fixes a bug to run consecutive experiments, and closes issue #3

Author: Mario Ruiz

README.md

@@ -45,11 +45,13 @@ If you use the TCP/IP stack or the checksum computation in your project please c
 @INPROCEEDINGS{ruiz2019tcp, 
     title={{Limago: an FPGA-based Open-source 100~GbE TCP/IP Stack}}, 
     author={Ruiz, Mario and Sidler, David and Sutter, Gustavo and Alonso, Gustavo and L{\'o}pez-Buedo, Sergio},
-    booktitle={Field Programmable Logic and Applications (FPL), 2019 29th International Conference on},
+    booktitle={{2019 29th International Conference on Field Programmable Logic and Applications (FPL)}}, 
     year={2019},
     month={Sep},
+    pages={286-292}, 
     organization={IEEE},
-    doi={},
+    doi={10.1109/FPL.2019.00053},
+    ISSN={1946-147X}, 
 }
 ```
 

RTL/cycle_limiter.v

@@ -86,7 +86,7 @@ module cycle_limiter (
 );
 
 
-    reg  [  4:  0]              cycle_counter = 16'h0;
+    reg  [  11:  0]              cycle_counter = 16'h0;
     reg                         internal_ready=  1'b1;
 
 
@@ -97,7 +97,7 @@ module cycle_limiter (
     assign M_AXIS_TVALID    = S_AXIS_TVALID & /* 1'b1  */internal_ready;   // Assert output valid depending on internal ready
     assign S_AXIS_TREADY    = M_AXIS_TREADY & /* 1'b1  */internal_ready;   // Assert output ready depending on internal ready
 
-    localparam integer        MAX_CYCLE_COUNT = 17;
+    localparam integer        MAX_CYCLE_COUNT = 18;
 
     localparam       INITIAL_STATE   = 0,
                      WAITING_PACKET  = 1,