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Commit 1e27e93

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author
Mario Ruiz
committed
Add target for VirtexUltrascale+ HBM
1 parent c0cdb71 commit 1e27e93

12 files changed

+53
-25
lines changed

‎.gitignore

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,4 +6,4 @@ synlog.tcl
66
*prj/
77
*.dir/
88
*.pb
9-
synthesis_results/
9+
synthesis_results_*HMB/

‎Makefile

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,23 @@
11

22

33
.PHONY:all
4-
all: create_folder
5-
make -C synthesis_results
4+
all: create_folder_noHBM
5+
make -C synthesis_results_noHMB
66

7-
create_folder:
8-
mkdir -p synthesis_results
9-
cp Makefile.synthesis synthesis_results/Makefile
7+
create_folder_noHBM:
8+
mkdir -p synthesis_results_noHMB
9+
cp Makefile.synthesis synthesis_results_noHMB/Makefile
10+
11+
.PHONY:hbm
12+
hbm: create_folder_HBM
13+
make -C synthesis_results_HMB FPGAPART=xcu280-fsvh2892-2L-e
14+
15+
create_folder_HBM:
16+
mkdir -p synthesis_results_HMB
17+
cp Makefile.synthesis synthesis_results_HMB/Makefile
1018

1119
clean:
1220
rm -rf *.log *.jou
1321

1422
distclean:
15-
rm -rf synthesis_results
23+
rm -rf synthesis_results_noHMB synthesis_results_HMB

‎Makefile.synthesis

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@ PORTSRC=$(TOPDIR)/hls/port_handler
1111
TCLDIR=$(TOPDIR)/scripts
1212

1313

14+
FPGAPART ?= xcvu9p-flga2104-2l-e
15+
1416
project = TOE_hls_prj IPERF2_TCP_hls_prj ECHOSERVER_hls_prj ARP_hls_prj \
1517
ETH_inserter_hls_prj ICMP_hls_prj PKT_HANDLER_prj userAbstraction_prj \
1618
portHandler_prj
@@ -31,40 +33,40 @@ distclean: clean
3133
TOE_hls_prj: $(shell find $(TOESCR) -type f) \
3234
$(TCLDIR)/toe_script.tcl
3335
rm -rf $@
34-
vivado_hls -f $(TCLDIR)/toe_script.tcl -tclargs $(TOPDIR) $@
36+
vivado_hls -f $(TCLDIR)/toe_script.tcl -tclargs $(TOPDIR) $@ FPGAPART
3537

3638
IPERF2_TCP_hls_prj: $(shell find $(IPERFSRC) -type f) \
3739
$(TCLDIR)/iperf2_tcp_script.tcl
3840
rm -rf $@
39-
vivado_hls -f $(TCLDIR)/iperf2_tcp_script.tcl -tclargs $(TOPDIR) $@
41+
vivado_hls -f $(TCLDIR)/iperf2_tcp_script.tcl -tclargs $(TOPDIR) $@ FPGAPART
4042

4143
ECHOSERVER_hls_prj: $(shell find $(ECHOSRC) -type f) $(TCLDIR)/echo_server_script.tcl
4244
rm -rf $@
43-
vivado_hls -f $(TCLDIR)/echo_server_script.tcl -tclargs $(TOPDIR) $@
45+
vivado_hls -f $(TCLDIR)/echo_server_script.tcl -tclargs $(TOPDIR) $@ FPGAPART
4446

4547
ARP_hls_prj: $(shell find $(ARPSRC) -type f) $(TCLDIR)/arp_script.tcl
4648
rm -rf $@
47-
vivado_hls -f $(TCLDIR)/arp_script.tcl -tclargs $(TOPDIR) $@
49+
vivado_hls -f $(TCLDIR)/arp_script.tcl -tclargs $(TOPDIR) $@ FPGAPART
4850

4951
ETH_inserter_hls_prj: $(shell find $(ETHSRC) -type f) $(TCLDIR)/ethernet_inserter_script.tcl
5052
rm -rf $@
51-
vivado_hls -f $(TCLDIR)/ethernet_inserter_script.tcl -tclargs $(TOPDIR) $@
53+
vivado_hls -f $(TCLDIR)/ethernet_inserter_script.tcl -tclargs $(TOPDIR) $@ FPGAPART
5254

5355
ICMP_hls_prj: $(shell find $(ICMPSRC) -type f) $(TCLDIR)/icmp_script.tcl
5456
rm -rf $@
55-
vivado_hls -f $(TCLDIR)/icmp_script.tcl -tclargs $(TOPDIR) $@
57+
vivado_hls -f $(TCLDIR)/icmp_script.tcl -tclargs $(TOPDIR) $@ FPGAPART
5658

5759
PKT_HANDLER_prj: $(shell find $(PKTSRC) -type f) $(TCLDIR)/packet_handler_script.tcl
5860
rm -rf $@
59-
vivado_hls -f $(TCLDIR)/packet_handler_script.tcl -tclargs $(TOPDIR) $@
61+
vivado_hls -f $(TCLDIR)/packet_handler_script.tcl -tclargs $(TOPDIR) $@ FPGAPART
6062

6163
userAbstraction_prj: $(shell find $(USRSRC) -type f) $(TCLDIR)/userAbstraction.tcl
6264
rm -rf $@
63-
vivado_hls -f $(TCLDIR)/userAbstraction.tcl -tclargs $(TOPDIR) $@
65+
vivado_hls -f $(TCLDIR)/userAbstraction.tcl -tclargs $(TOPDIR) $@ FPGAPART
6466

6567
portHandler_prj: $(shell find $(PORTSRC) -type f) $(TCLDIR)/portHandler.tcl
6668
rm -rf $@
67-
vivado_hls -f $(TCLDIR)/portHandler.tcl -tclargs $(TOPDIR) $@
69+
vivado_hls -f $(TCLDIR)/portHandler.tcl -tclargs $(TOPDIR) $@ FPGAPART
6870

6971
.PHONY: list help
7072
list:

‎scripts/arp_script.tcl

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,14 +2,16 @@
22
set root_folder [lindex $argv 2]
33
# Get project name from the arguments
44
set proj_name [lindex $argv 3]
5+
# Get FPGA part
6+
set fpga_part [lindex $argv 4]
57
# Create project
68
open_project ${proj_name}
79

810
set_top arp_server
911
add_files ${root_folder}/hls/arp_server/arp_server.cpp
1012

1113
open_solution "ultrascale_plus"
12-
set_part {xcvu9p-flga2104-2l-e} -tool vivado
14+
set_part ${fpga_part} -tool vivado
1315
create_clock -period 3.1 -name default
1416
set_clock_uncertainty 0.2
1517

‎scripts/echo_server_script.tcl

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
set root_folder [lindex $argv 2]
33
# Get project name from the arguments
44
set proj_name [lindex $argv 3]
5+
# Get FPGA part
6+
set fpga_part [lindex $argv 4]
57
# Create project
68
open_project ${proj_name}
79

@@ -11,7 +13,7 @@ add_files ${root_folder}/hls/echo_replay/echo_server_application.cpp
1113
add_files -tb ${root_folder}/hls/echo_replay/test_echo_server_application.cpp
1214

1315
open_solution "ultrascale_plus"
14-
set_part {xcvu9p-flga2104-2l-e} -tool vivado
16+
set_part ${fpga_part} -tool vivado
1517
create_clock -period 3.1 -name default
1618
set_clock_uncertainty 0.2
1719

‎scripts/ethernet_inserter_script.tcl

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
set root_folder [lindex $argv 2]
33
# Get project name from the arguments
44
set proj_name [lindex $argv 3]
5+
# Get FPGA part
6+
set fpga_part [lindex $argv 4]
57
# Create project
68
open_project ${proj_name}
79

@@ -11,7 +13,7 @@ add_files ${root_folder}/hls/ethernet_inserter/ethernet_header_inserter.cpp
1113
add_files -tb ${root_folder}/hls/ethernet_inserter/ethernet_header_inserter_test.cpp
1214

1315
open_solution "ultrascale_plus"
14-
set_part {xcvu9p-flga2104-2l-e} -tool vivado
16+
set_part ${fpga_part} -tool vivado
1517
create_clock -period 3.1 -name default
1618
set_clock_uncertainty 0.2
1719

‎scripts/icmp_script.tcl

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
set root_folder [lindex $argv 2]
33
# Get project name from the arguments
44
set proj_name [lindex $argv 3]
5+
# Get FPGA part
6+
set fpga_part [lindex $argv 4]
57
# Create project
68
open_project ${proj_name}
79

@@ -14,7 +16,7 @@ add_files -tb ${root_folder}/hls/TOE/testbench/pcap2stream.cpp -cflags "-Ihls/TO
1416
add_files -tb ${root_folder}/hls/TOE/testbench/pcap.cpp -cflags "-Ihls/TOE/testbench/."
1517

1618
open_solution "ultrascale_plus"
17-
set_part {xcvu9p-flga2104-2l-e} -tool vivado
19+
set_part ${fpga_part} -tool vivado
1820
create_clock -period 3.1 -name default
1921
set_clock_uncertainty 0.2
2022
#csim_design -argv "${root_folder}/hls/icmp_server/icmp.pcap ${root_dir}/hls/icmp_server/icmp_golden.pcap"

‎scripts/iperf2_tcp_script.tcl

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
set root_folder [lindex $argv 2]
33
# Get project name from the arguments
44
set proj_name [lindex $argv 3]
5+
# Get FPGA part
6+
set fpga_part [lindex $argv 4]
57
# Create project
68
open_project ${proj_name}
79

@@ -14,7 +16,7 @@ add_files ${root_folder}/hls/TOE/common_utilities/common_utilities.cpp
1416
add_files -tb ${root_folder}/hls/iperf2_tcp/test_iperf_client.cpp
1517

1618
open_solution "ultrascale_plus"
17-
set_part {xcvu9p-flga2104-2l-e} -tool vivado
19+
set_part ${fpga_part} -tool vivado
1820
create_clock -period 3.1 -name default
1921
set_clock_uncertainty 0.2
2022

‎scripts/packet_handler_script.tcl

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
set root_folder [lindex $argv 2]
33
# Get project name from the arguments
44
set proj_name [lindex $argv 3]
5+
# Get FPGA part
6+
set fpga_part [lindex $argv 4]
57
# Create project
68
open_project ${proj_name}
79

@@ -11,7 +13,7 @@ add_files ${root_folder}/hls/packet_handler/packet_handler.cpp
1113
add_files -tb ${root_folder}/hls/packet_handler/test_packet_hanlder.cpp
1214

1315
open_solution "ultrascale_plus"
14-
set_part {xcvu9p-flga2104-2l-e} -tool vivado
16+
set_part ${fpga_part} -tool vivado
1517
create_clock -period 3.1 -name default
1618
set_clock_uncertainty 0.2
1719

‎scripts/portHandler.tcl

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
set root_folder [lindex $argv 2]
33
# Get project name from the arguments
44
set proj_name [lindex $argv 3]
5+
# Get FPGA part
6+
set fpga_part [lindex $argv 4]
57
# Create project
68
open_project ${proj_name}
79

@@ -15,7 +17,7 @@ add_files -tb ${root_folder}/hls/TOE/testbench/pcap.cpp -cflags ""
1517
add_files -tb ${root_folder}/hls/TOE/testbench/pcap2stream.cpp -cflags ""
1618

1719
open_solution "ultrascale_plus"
18-
set_part {xcvu9p-flga2104-2l-e} -tool vivado
20+
set_part ${fpga_part} -tool vivado
1921
create_clock -period 3.1 -name default
2022
set_clock_uncertainty 0.2
2123

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