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adding statistic metrics gathering functions for upstream SST inclusion
1 parent ca55839 commit 96947d7

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7 files changed

+153
-6
lines changed

7 files changed

+153
-6
lines changed

DRAMSim.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -37,16 +37,16 @@
3737

3838
using std::string;
3939

40-
namespace DRAMSim
40+
namespace DRAMSim
4141
{
42-
class MultiChannelMemorySystem
42+
class MultiChannelMemorySystem
4343
{
44-
public:
44+
public:
4545
bool addTransaction(bool isWrite, uint64_t addr);
4646
void update();
4747
void printStats(bool finalStats);
48-
bool willAcceptTransaction();
49-
bool willAcceptTransaction(uint64_t addr);
48+
bool willAcceptTransaction();
49+
bool willAcceptTransaction(uint64_t addr);
5050

5151
void RegisterCallbacks(TransactionCompleteCB *readDone, TransactionCompleteCB *writeDone);
5252
};

MemoryController.cpp

Lines changed: 90 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -647,6 +647,96 @@ void MemoryController::resetStats()
647647
}
648648
}
649649

650+
//retrieves the target 'metric' stat and returns the value as a double in *stat
651+
bool MemoryController::getStats( double *stat, DSIM_STAT metric ){
652+
double totalBandwidth=0.0;
653+
uint64_t cyclesElapsed =
654+
(currentClockCycle % EPOCH_LENGTH == 0) ? EPOCH_LENGTH : currentClockCycle % EPOCH_LENGTH;
655+
unsigned bytesPerTransaction = JEDEC_DATA_BUS_BITS*BL/8;
656+
double secondsThisEpoch = (double)cyclesElapsed * tCK * 1E-9;
657+
vector<double> bandwidth = vector<double>(NUM_RANKS*NUM_BANKS,0.0);
658+
659+
switch( metric ){
660+
case TOTAL_BANDWIDTH:
661+
for (unsigned i = 0; i < NUM_RANKS; ++i) {
662+
for (unsigned j = 0; j < NUM_BANKS; ++j) {
663+
bandwidth[SEQUENTIAL(i,j)] =
664+
(((double)(totalReadsPerBank[SEQUENTIAL(i,j)] +
665+
totalWritesPerBank[SEQUENTIAL(i,j)]) *
666+
(double)bytesPerTransaction)/(1024.0*1024.0*1024.0)) /
667+
secondsThisEpoch;
668+
totalBandwidth += bandwidth[SEQUENTIAL(i,j)];
669+
}
670+
}
671+
*stat = totalBandwidth;
672+
return true;
673+
break;
674+
case TOTAL_TRANSACTIONS:
675+
case TOTAL_BYTES_TRANSFERRED:
676+
case TOTAL_READS:
677+
case TOTAL_WRITES:
678+
case PENDING_READ_TRANSACTIONS:
679+
case PENDING_RTN_TRANSACTIONS:
680+
default:
681+
// none of these are double values
682+
return false;
683+
break;
684+
}
685+
}
686+
687+
//retrieves the target 'metric' stat and returns the value as a uint64_t in *stat
688+
bool MemoryController::getStats( uint64_t *stat, DSIM_STAT metric ){
689+
unsigned bytesPerTransaction = JEDEC_DATA_BUS_BITS*BL/8;
690+
uint64_t totalReads = 0x00ull;
691+
uint64_t totalWrites = 0x00ull;
692+
693+
switch( metric ){
694+
case TOTAL_BYTES_TRANSFERRED:
695+
if (operationMode == PseudoChannelMode)
696+
bytesPerTransaction /= 2;
697+
698+
*stat = (uint64_t)(totalTransactions * bytesPerTransaction);
699+
return true;
700+
break;
701+
case TOTAL_READS:
702+
for (unsigned i = 0; i < NUM_RANKS; ++i) {
703+
for (unsigned j = 0; j < NUM_BANKS; ++j) {
704+
totalReads += totalReadsPerBank[SEQUENTIAL(i,j)];
705+
totalWritesPerRank[i] += totalWritesPerBank[SEQUENTIAL(i,j)];
706+
}
707+
}
708+
*stat = totalReads;
709+
return true;
710+
break;
711+
case TOTAL_WRITES:
712+
for (unsigned i = 0; i < NUM_RANKS; ++i) {
713+
for (unsigned j = 0; j < NUM_BANKS; ++j) {
714+
totalWrites += totalWritesPerBank[SEQUENTIAL(i,j)];
715+
}
716+
}
717+
*stat = totalWrites;
718+
return true;
719+
break;
720+
case TOTAL_TRANSACTIONS:
721+
*stat = (uint64_t)(transactionQueue.size());
722+
return true;
723+
break;
724+
case PENDING_READ_TRANSACTIONS:
725+
*stat = (uint64_t)(pendingReadTransactions.size());
726+
return true;
727+
break;
728+
case PENDING_RTN_TRANSACTIONS:
729+
*stat = (uint64_t)(returnTransaction.size());
730+
return true;
731+
break;
732+
case TOTAL_BANDWIDTH:
733+
default:
734+
// none of these are double values
735+
return false;
736+
break;
737+
}
738+
}
739+
650740
//prints statistics at the end of an epoch or simulation
651741
void MemoryController::printStats(bool finalStats)
652742
{

MemoryController.h

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,17 @@
4545

4646
using namespace std;
4747

48+
// stats enumerated types
49+
typedef enum{
50+
TOTAL_TRANSACTIONS,
51+
TOTAL_BYTES_TRANSFERRED,
52+
TOTAL_BANDWIDTH,
53+
TOTAL_READS,
54+
TOTAL_WRITES,
55+
PENDING_READ_TRANSACTIONS,
56+
PENDING_RTN_TRANSACTIONS
57+
}DSIM_STAT;
58+
4859
namespace DRAMSim
4960
{
5061
#ifdef DEBUG_LATENCY
@@ -92,7 +103,11 @@ class MemoryController : public SimulatorObject
92103
void updateBankStates();
93104
void update();
94105
void printStats(bool finalStats = false);
95-
void resetStats();
106+
void resetStats();
107+
108+
// retrieve the target stats entry 'metric' in 'stat'
109+
bool getStats( double *stat, DSIM_STAT metric );
110+
bool getStats( uint64_t *stat, DSIM_STAT metric );
96111

97112
public:
98113
vector<Transaction*> transactionQueue;

MemorySystem.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,14 @@ bool MemorySystem::addTransaction(bool isWrite, uint64_t addr)
117117
}
118118
}
119119

120+
bool MemorySystem::getStats( double *stat, DSIM_STAT metric ){
121+
return memoryController->getStats(stat, metric);
122+
}
123+
124+
bool MemorySystem::getStats( uint64_t *stat, DSIM_STAT metric ){
125+
return memoryController->getStats(stat, metric);
126+
}
127+
120128
void MemorySystem::printStats(bool finalStats)
121129
{
122130
memoryController->printStats(finalStats);

MemorySystem.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,9 @@ class MemorySystem : public SimulatorObject
5353
bool WillAcceptTransaction();
5454
void RegisterCallbacks(Callback_t *readDone, Callback_t *writeDone);
5555

56+
bool getStats( double *stat, DSIM_STAT metric );
57+
bool getStats( uint64_t *stat, DSIM_STAT metric );
58+
5659
public:
5760
Callback_t* ReturnReadData;
5861
Callback_t* WriteDataDone;

MultiChannelMemorySystem.cpp

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -122,6 +122,34 @@ bool MultiChannelMemorySystem::willAcceptTransaction(uint64_t addr)
122122
return channels[chan]->WillAcceptTransaction();
123123
}
124124

125+
bool MultiChannelMemorySystem::getStats( double *stat, DSIM_STAT metric ){
126+
double value = 0.;
127+
double total = 0.;
128+
for (unsigned i = 0; i < NUM_CHANS; ++i){
129+
if( channels[i]->getStats( &value, metric ) ){
130+
total += value;
131+
value = 0.;
132+
}else{
133+
return false;
134+
}
135+
}
136+
return true;
137+
}
138+
139+
bool MultiChannelMemorySystem::getStats( uint64_t *stat, DSIM_STAT metric ){
140+
uint64_t value = 0.;
141+
uint64_t total = 0.;
142+
for (unsigned i = 0; i < NUM_CHANS; ++i){
143+
if( channels[i]->getStats( &value, metric ) ){
144+
total += value;
145+
value = 0.;
146+
}else{
147+
return false;
148+
}
149+
}
150+
return true;
151+
}
152+
125153
void MultiChannelMemorySystem::printStats(bool finalStats)
126154
{
127155
for (unsigned i = 0; i < NUM_CHANS; ++i) {

MultiChannelMemorySystem.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,9 @@ class MultiChannelMemorySystem : public SimulatorObject
4747
void printStats(bool finalStats=false);
4848
void RegisterCallbacks(TransactionCompleteCB *readDone, TransactionCompleteCB *writeDone);
4949

50+
bool getStats( double *stat, DSIM_STAT metric );
51+
bool getStats( uint64_t *stat, DSIM_STAT metric );
52+
5053
private:
5154
unsigned findChannelNumber(uint64_t addr);
5255

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