Nextpnr-xilinx issues: ERROR: Unable to place cell 'inverter1', no BELs remaining to implement cell type '$_NOT_'

[Arthuuuuroo]

Hello,

I'm facing the same issue as #86, but no answers have been posted.

When launching PnR, with this command : ./nextpnr-xilinx -l nextpnr.log --xdc ring_oscillator.xdc --chipdb xilinx/xc7s50csga324-1.bin --json ring_oscillator.json --write ring_oscillator_routed.json --fasm ring_oscillator.fasm --router router1 --freq 12

I got this error:

ERROR: Unable to place cell 'inverter1', no BELs remaining to implement cell type '$NOT'

#LOG

Info: Packing constants..
Info: Inserting IO buffers..
Info: Constraining 'RO_OUT' to site 'IOB_X0Y0'
Info: Tile 'LIOB33_SING_X0Y0'
Info: Constraining 'Enable' to site 'IOB_X0Y1'
Info: Tile 'LIOB33_X0Y1'
Info: Generating output buffer for 'RO_OUT$obuf$'
Info: Generating input buffer for 'Enable$ibuf$'
Info: Created 2 PAD cells from:
Info: 2x PAD
Info: Preparing clocking...
Info: Packing constants..
Info: Packing PLLs...
Info: Packing global buffers...
Info: Packing MUX[789]s..
Info: Packing carries..
Info: Grouped 0 MUXCYs and 0 XORCYs into 0 chains.
Info: Blasted 0 non-chain MUXCYs and 0 non-chain XORCYs to soft logic
Info: Packing LUTs..
Info: Packing DRAM..
Info: Transformed 0 tied-low DRAM address inputs to be tied-high
Info: Packing BRAM..
Info: Packing DSPs..
Info: Packing flipflops..
Info: Constrained 0 LUTFF pairs.

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0xe2dbd45a

Info: Device utilisation:
Info: SLICE_LUTX: 0/65200 0%
Info: SLICE_FFX: 0/65200 0%
Info: CARRY4: 0/ 8150 0%
Info: PSEUDO_GND: 1/18055 0%
Info: PSEUDO_VCC: 1/18055 0%
Info: HARD0: 0/ 1980 0%
Info: RAMB18E1_RAMB18E1: 0/ 150 0%
Info: FIFO18E1_FIFO18E1: 0/ 75 0%
Info: RAMBFIFO36E1_RAMBFIFO36E1: 0/ 75 0%
Info: RAMB36E1_RAMB36E1: 0/ 75 0%
Info: DSP48E1_DSP48E1: 0/ 120 0%
Info: PAD: 2/ 730 0%
Info: IOB33M_OUTBUF: 0/ 120 0%
Info: IOB33S_OUTBUF: 0/ 120 0%
Info: IOB33_OUTBUF: 1/ 250 0%
Info: IOB33M_INBUF_EN: 0/ 120 0%
Info: IOB33S_INBUF_EN: 0/ 120 0%
Info: IOB33_INBUF_EN: 1/ 250 0%
Info: IOB33M_TERM_OVERRIDE: 0/ 120 0%
Info: IOB33S_TERM_OVERRIDE: 0/ 120 0%
Info: IOB33_TERM_OVERRIDE: 0/ 250 0%
Info: PULL_OR_KEEP1: 0/ 490 0%
Info: IDELAYE2_IDELAYE2: 0/ 250 0%
Info: OLOGICE3_TFF: 0/ 250 0%
Info: OLOGICE3_OUTFF: 0/ 250 0%
Info: OLOGICE3_MISR: 0/ 250 0%
Info: OSERDESE2_OSERDESE2: 0/ 250 0%
Info: ILOGICE3_IFF: 0/ 250 0%
Info: ILOGICE3_ZHOLD_DELAY: 0/ 250 0%
Info: ISERDESE2_ISERDESE2: 0/ 250 0%
Info: BUFIO_BUFIO: 0/ 20 0%
Info: IDELAYCTRL_IDELAYCTRL: 0/ 5 0%
Info: BUFGCTRL: 0/ 32 0%
Info: BUFG_BUFG: 0/ 32 0%
Info: INVERTER: 0/ 120 0%
Info: OLOGICE2_TFF: 0/ 250 0%
Info: OLOGICE2_OUTFF: 0/ 250 0%
Info: PLLE2_ADV_PLLE2_ADV: 0/ 5 0%
Info: SELMUX2_1: 0/25450 0%
Info: BSCAN: 0/ 4 0%
Info: DCIRESET_DCIRESET: 0/ 1 0%
Info: FRAME_ECC_FRAME_ECC: 0/ 1 0%
Info: ICAP_ICAP: 0/ 2 0%
Info: STARTUP_STARTUP: 0/ 1 0%
Info: USR_ACCESS_USR_ACCESS: 0/ 1 0%
Info: DNA_PORT_DNA_PORT: 0/ 1 0%
Info: EFUSE_USR_EFUSE_USR: 0/ 1 0%
Info: BUFHCE_BUFHCE: 0/ 72 0%
Info: BUFFER: 0/ 240 0%
Info: ILOGICE2_IFF: 0/ 250 0%
Info: OLOGICE2_MISR: 0/ 250 0%

Info: Placed 4 cells based on constraints.

Did you find a solution about this?

Thanks,