CH3_REGS and CHANNEL3 errors (schematic side)

[jbshelton]

The first "error" is more a confusing way of marking things- the 'D7' input to GAVU in the NR30 section of CH3_REGS is what I assume to be bit 7 of FF1E (NR34) due to the FF1E input to EPYX, but isn't marked clearly. I think renaming it to "FF1E_D7" or something similar would help.
The second error: but the "length timer" section of CHANNEL3 has no outputs, suggesting that channel 3's length counter has no effect. I'm sure this is just an error from automatic schematic generation or something.

[msinger]

I already found the solution to your second error. Please see #42. Also important to fix the length counter is #40.

I disagree with the first "error" though. It actually is confusing, but the D7 input of GAVU is labeled correctly. It is bit 7 of the common data bus, through which the CPU can set bit 7 of register FF1E. The Q output of GAVU could be labeled as FF1E_D7, because that is what bit 7 of that register holds. The confusing thing is that the caption of this block says "FF1A NR30", even though the block describes bit 7 of FF1A and bit 7 of FF1E. So in my opinion, either the caption should be changed to include FF1E, or the bottom part of this block should be moved to the right side of this page, under the caption "FF1E NR34". But I'm not sure where to make the cut.