Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

Author: dsengupta0628

test/regression_vars.tcl

@@ -166,6 +166,7 @@ record_public_tests {
   verilog_attribute
   verilog_specify
   verilog_write_escape
+  verilog_unconnected_dbterm
 }
 
 define_test_group fast [group_tests all]

test/verilog_unconnected_dbterm.ok

@@ -0,0 +1,4 @@
+Find b1/out2: b1/out2
+Find b2/out2: b2/out2
+Net connected to b2/u3/Z: b2/out2
+Find internal net connected to b2/out2: b2/out2

test/verilog_unconnected_dbterm.tcl

@@ -0,0 +1,14 @@
+read_liberty ../examples/nangate45_typ.lib.gz
+read_verilog verilog_unconnected_dbterm.v
+link_design top 
+puts "Find b1/out2: [get_property [get_pins b1/out2] full_name]"
+puts "Find b2/out2: [get_property [get_pins b2/out2] full_name]"
+# Check if net is connected to "b2/u3/Z" that was the b2/out2 in parent block
+set iterm [sta::find_pin "b2/u3/Z"]
+set net [get_net -of_object [get_pin $iterm]]
+if { $net != "NULL" } {
+  puts "Net connected to b2/u3/Z: [get_full_name $net]"
+} else {
+  puts "b2/u3/Z is not connected to any net."
+}
+puts "Find internal net connected to b2/out2: [get_property [get_net b2/out2] full_name]"

test/verilog_unconnected_dbterm.v

@@ -0,0 +1,27 @@
+module top (in, clk1, clk2, out, out2);
+   input in, clk1, clk2;
+   output out, out2;
+   block1 b1 (.in(in), .clk(clk1), .out(b1out), .out2(out2));
+   block2 b2 (.in(b1out), .clk(clk2), .out(out));
+endmodule // top
+
+module block1 (in, clk, out, out2);
+   input in, clk;
+   output out, out2;
+   BUF_X1 u1 (.A(in), .Z(u1out));
+   DFF_X1 r1 (.D(u1out), .CK(clk), .Q(r1q));
+   BUF_X1 u2 (.A(r1q), .Z(out));
+   BUF_X1 u3 (.A(out), .Z(out2));
+endmodule // block1
+
+module block2 (in, clk, out, out2);
+   input in, clk;
+   output out, out2;
+   BUF_X1 u1 (.A(in), .Z(u1out));
+   DFF_X1 r1 (.D(u1out), .CK(clk), .Q(r1q));
+   BUF_X1 u2 (.A(r1q), .Z(out));
+   BUF_X1 u3 (.A(out), .Z(out2));
+endmodule // block2
+
+
+

verilog/VerilogReader.cc

@@ -1824,13 +1824,11 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst,
       }
     }
 
-    if (lib_cell) {
-      // Make all pins so timing arcs are built.
-      LibertyCellPortBitIterator port_iter(lib_cell);
-      while (port_iter.hasNext()) {
-        LibertyPort *port = port_iter.next();
-        network_->makePin(inst, reinterpret_cast<Port*>(port), nullptr);
-      }
+    // Make all pins so timing arcs are built and get_pins finds them.
+    ConcreteCellPortBitIterator port_iter(reinterpret_cast<const ConcreteCell*>(cell));
+    while (port_iter.hasNext()) {
+      Port *port = reinterpret_cast<Port*>(port_iter.next());
+      network_->makePin(inst, port, nullptr);
     }
     bool is_leaf = network_->isLeaf(cell);
     VerilogBindingTbl bindings(zero_net_name_, one_net_name_);
@@ -1983,12 +1981,16 @@ VerilogReader::makeInstPin(Instance *inst,
       network_->connect(inst, port, net);
   }
   else {
-    Pin *pin = network_->makePin(inst, port, net);
-    if (!is_leaf && net) {
-      const char *port_name = network_->name(port);
-      Net *child_net = bindings->ensureNetBinding(port_name, inst, network_);
-      network_->makeTerm(pin, child_net);
-    }
+    // Ensure pin exists (may have been pre-created), then connect to parent
+    // net if present. Always create a term for the child-side net.
+    Pin *pin = network_->findPin(inst, port);
+    if (pin == nullptr)
+      pin = network_->makePin(inst, port, net);
+    else if (net)
+      pin = network_->connect(inst, port, net);
+    const char *port_name = network_->name(port);
+    Net *child_net = bindings->ensureNetBinding(port_name, inst, network_);
+    network_->makeTerm(pin, child_net);
   }
 }