Appreciate such example.

[briansune]

I had tested with 16 bit 2+8 setting of 2 stage CIC and 8 oversample under 6.25M.
Any detail formula of the RC selection and the low and high side offset?
From my setting I had investigate over Altera and Xilinx FPGA LVDS 2.5 standard and look like using CIC and reduce the low side offset to 1xxx over 16 bit resolution and high side to 64xxx range.
While I also found that from paper :
https://devzone.missinglinkelectronics.com/index.php/source-menu-ioconnect-adc
I would like to ask any detail DC response curves?
It looks like rail reach is far idle but paper do show a good 16 bit linearity.

[davemuscle]

Hey,
I definitely had to fiddle with the RC network a bit to get a good looking response. I think in the end I went with an empirical choice, but section 5.1 from this Lattice document has some good notes and even an alternate way at setting it up:

https://www.latticesemi.com/-/media/LatticeSemi/Documents/ReferenceDesigns/SZ/FPGA-RD-02047-1-6-Simple-Sigma-Delta-ADC.ashx?document_id=35762

If you can't access that this is the parent page:
https://www.latticesemi.com/products/designsoftwareandip/intellectualproperty/referencedesigns/referencedesign03/simplesigmadeltaadc

Could you clarify on the low/high side offsets? For my FPGA board, a 2.5 LVDS pair was able to digitize between ~0 to ~3.3V. It was able to handle that since the bank voltage for those pins on my FPGA board is set to 3.3V, regardless of the 2.5V IO standard. It would probably be a good idea to restrain that a bit and have some analog conditioning force the input to be within 1.5V +- 1V maybe.

I did not record any DC response curves but I do recall the digital resolution would be what you expect for an unsigned ADC.

[briansune]

Able to digitize between ~0 to ~3.3V is a tricky description. Which what I experience is a digitized offset range from 1xxx to 64xxx.
Of cause meaning 0 to 3.3V.
The background hardware setup is a 10k-1nF LPF from 1 pin to LVDS negative input. while LVDS positive is 10k series.
Code is cloned from your repository with pll modification to Xilinx accordingly.
Clock frequency is kept at 6.25Mhz.
Test condition is pure DC from "SPD1000X Programmable Linear DC Power Supply"
Return result is monitored via ILA or sig tap.

[davemuscle]

Just so we're on the same page, this is what you should expect for DC if you have a 3.3V bank and 16-bit ADC (max = 65536)

• 0V -> adc_output = 0
• 1.0V -> adc_output = 1 * max / 3.3 = 19859
• 1,67V -> adc_output = 32768
• 2.0V -> adc_output = 2 * max /3.3 = 39718
• 3.3V -> adc_output = max

I just updated the simulation under tb/adc/, pull it and modify the Makefile under that folder to match your test setup. For your case set OUTPUT_DIGITAL=1 and USE_DC=1 then run 'make clean sim plot'.

In my quick testing now I've determined when you change the OVERSAMPLE_RATE and CIC_STAGES you should accordingly change the ADC_BITLEN parameter to match. The output is always going to be proportional to 2**(CIC_STAGES*$clog2(OVERSAMPLE_RATE). So for your next testing, set ADC_BITLEN=6

[briansune]

In my quick testing now I've determined when you change the OVERSAMPLE_RATE and CIC_STAGES you should accordingly change the ADC_BITLEN parameter to match. The output is always going to be proportional to 2**(CIC_STAGES*$clog2(OVERSAMPLE_RATE). So for your next testing, set ADC_BITLEN=6

Of cause when 16 bit resolution the bit width of the BITLEN is set to 16.
There are no FIR filter is used just a CIC.
It is puzzle that 0V and 3.3V can achieve 0 and max without offset on your real hardware setup.
Please correct me if anything I am misunderstood.

[briansune]

So from simulation it shows a sine wave with offset range.
However, idle in simulation is not the case.
What I am really can't figure out is that can you achieve 0V - 0 value and 3V3 - max of resolution in bit-width?

No matter I use through-hole components nor smd to reduce parasitic it is still similar result with noisy modulated result + offset.
Of cause it is responding to the 0V to 3V3 with 16bit 1xxx to 64xxx accordingly.
But these all result is still far beyond the paper claims.

[davemuscle]

Can you try using OVERSAMPLE_RATIO=256 in your next build and compare the result? Also could try making the capacitor large and see if there is an improvement.

[briansune]

Dave, my default setup is using oversample = 256 otherwise 2 stage CIC cannot form a 16bit resolution as your code clearly suggested.

So Dave, are you really achieving 14bit good ADC from 0V to 3V3 without losing or offset?

[davemuscle]

Gotcha, thought you were using OVERSAMPLE_RATIO=8. What do you mean 'without losing or offset'?

You can see here that that 1.0V amplitude is attenuated slightly:
https://github.com/davemuscle/sigma_delta_converters#adc-standard-measurement

[briansune]

Gotcha, thought you were using OVERSAMPLE_RATIO=8.

I am test such soft ADC only via a linear DC supply so from 0V It should return 0# but not really
It is offset to range 2xxx and 3V3 is offset to 64xxx rather than 65535.

This is what the issue here.

[davemuscle]

I see now. Will have to setup my station at some point and try it.

For now I'd recommend testing different RC networks and seeing if there is an improvment

[briansune]

according to Lattice manual, it is mention that time constant * freq >= 500 is good.
So the default setup is a 10k + 1nF = 62.5 is not enough.
I pushed to clock to 62.5Mhz and the offset effect is still exist.
Not sure you can repeat such?

[davemuscle]

Set the hardware back up and performed some DC measurements:

• Voltage = 0 Digital = 779 Expected = 0.0
• Voltage = 0.025 Digital = 802 Expected = 124.12
• Voltage = 0.1 Digital = 1223 Expected = 496.48
• Voltage = 1.0 Digital = 5525 Expected = 4964.84
• Voltage = 2.0 Digital = 10352 Expected = 9929.69
• Voltage = 3.0 Digital = 15261 Expected = 14894.54
• Voltage = 3.3 Digital = 16383 Expected = 16384.0

Since the 'offset' fixes itself as the voltage increases, I want to attribute this to ground noise. I've seen a really bad ground loop on my instrumentation device in the past, plus it's powered from a USB hub.

[briansune]

Dave, now you are repeating what I am experiencing.
low side is highly offset to a point that is not explain why and paper I attached show completely discrepancy.
So with your 14 bit setup It looks like high side is even too good compare to my result.

My setup would require even high than the IO back supply voltage to reach max value.
Meantime, I need to know more about the DC you measuring is stable or moving epically ?

[davemuscle]

It moves around, there will always be variance on the lower bits. I would say it isn't "epically" though. This is for 1V DC:

At this point it may be a good idea to instantiate the XADC core and compare the result.

[briansune]

First really appreciate all the discussion here.
Did you utilize the filter as well? It looks like too stable and jumping is still low considered.
But now I am really confused by the paper and the claim of soft ADC performance.

I am very sure soft DAC is wonderful yet I haven't tried yours as I create mine as well before.
But soft ADC is very questionable.
So I will consider if LVDS really good for good ADC resolution, however external comparator is good way to investigate if you ask me.

[davemuscle]

I used the hardware setup as-is from here (no filter):
https://github.com/davemuscle/sigma_delta_converters/blob/master/rtl/hw_test/top.sv

It may also be a good idea to scope your ground pin, if possible. Depending on your hardware setup, making the circuit smaller + using shorter wires to the FPGA could help

[briansune]

Dave would it possible to recapture the 0V noise and value from your 14bit?
3V3 and 0V would be nice to monitor as this case as low and high limit is what such soft ADC is constrained I guess.
I am also going to share out a result on my board here as cross referencing.

[davemuscle]

I'd have to set back up the hardware -- I'm using this FPGA board for a few different things. What good would recapturing be without changes? Here are my recorded results:

Instrumentation device on and outputting 0V:

Forgot to add this before, but this is an interesting point:
Instrumentation device completely off but with wires still connected (floating):

[briansune]

Dave thank you:

Hardware Setup:

Here is my plot via Python and 16bit soft ADC:
When Power Supply is set to 0V/0.01A

When Power Supply is set to 3V3/0.01A

For my case if PSU is off:

[briansune]

What good would recapturing be without changes?
Because previous test it is missing a lot of the soft ADC dynamic result so for 0V and 3V3 it is really necessary to capture the result to share out and see what really happening.

It is shown that if ILA is used and not sure if it is the sample point of ILA is not enough nor the logic usage do affect the soft ADC performance as well.
As we all know individual soft ADC LE usage is very low and placement can be far away form IO buffer and switch power rail could be coupled during huge transection of logic. AKA noise

I will try to preform automated power supply and point plot capture as we can see how this actually perform

[davemuscle]

A few questions about the hardware setup picture, assuming you don't have a breadboard offscreen:

1. Is the resistor leg twisted around the male jumper pin? If that moves around at all you'll get noisy results, it might need to be soldered or plugged into a breadboard at least.
2. Have you measured how clean the output supply is? Might need some bypass capacitors near the output if it's having to travel far.
3. Where is the capacitor of the integrator circuit?

Regarding the plots,

1. It looks like there is some systemic issue every 2000 (2048?) samples, could this be an issue with your sampling / uploader circuit?

[briansune]

A few questions about the hardware setup picture, assuming you don't have a breadboard offscreen:

Is the resistor leg twisted around the male jumper pin? If that moves around at all you'll get noisy results, it might need to be soldered or plugged into a breadboard at least.
->It is double twisted from front and end.

->Dave bread board is a highly capacitive test gear I will never suggest using bread board when you have a solder and all PCB test board you can work with (No offense but bread board is really a gear only for very harsh circuit build).

Have you measured how clean the output supply is?
Might need some bypass capacitors near the output if it's having to travel far.
->Well It could be a nice suggestion but I don' think it will do much with the average offset.

Where is the capacitor of the integrator circuit?
->Can you see there is a very small 0603 R-C is solder at the connector.

It looks like there is some systemic issue every 2000 (2048?) samples, could this be an issue with your sampling / uploader circuit?
-> I dont think this is really the case. if it is repetitive it should be very periodically I think this is really noise from environment but I can investigate a bit.

[briansune]

Dave just little update on my script and the result.
So after adding capacitor and without the result really make not much different.
The spike of the reading may be caused by surrounding as I move away other electronic gear.
New reading are as follow:
Good thing is that the reading look it is usable but may still need more modification to reduce the noise as well.
I am considering the FPGA IO bank supply must isolated from other interface.
And looks like 3.3V cannot reach max value unless it is +0.1V VCCIO.

It is true that there are some noise are injected to the ADC, and the response time of the ADC is inverse log behavior as RC proposed.

0V PSU on:

3V3 PSU:

0V PSU off:

[briansune]

Including two additional 0V - 3V3 , 3V3 - 0V:

[davemuscle]

Nice, it looks a bit better now. There still appears to be ~40 mV of noise riding your 0V PSU on signal, though. Could you eliminate the PSU from the mix and attempt to sample a digital LVCMOS pin at 0 and 3.3V? Maybe even put a voltage divider in the mix to sample at 1.67V so you can measure away from the either rail.

[briansune]

But Dave, you can see no matter how good the test equipment it gets it is still considered as offset 200 - 400 decimal at low side aka 200 / 65536 * 3.3. It is still far usable compared to general 16 bit ADC.
Of cause what do you expect if it can be measure Analog when it is just less than 0.1 cent cost.

[briansune]

Hey Dave,
I have a bit idea not sure you agree.
What if FPGA 1 soft ADC is used to measure the noise of the system.
Aka it is short 10k input to ground.
While other ADC channels are subtracted with this noise spectrum and result in a limiter to restrict the subtracted measurements to 16 bit range?

Would you think this is a even better way to control?
Of cause such idea can also be extend to shorting 1 soft ADC to VIO and hence we got a 0 and VIO range to pass to a DSP to scale the range of the soft ADC back to 16 bit.

[davemuscle]

Hey,
I think that would be an interesting idea to try. That's a pretty well tested differential signaling concept for noise reduction, so you'll probably get a better result. Maybe include an extra guard bit or two so you don't underflow at the 0V rail.

Other comment, have you ever measured the output of your PSU with an oscope?

[briansune]

It is interesting that my PSU noise is not really changed under ON/OFF
But a offset on DC rail

OFF

ON