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Update code for Amaranth RFCs 37 and 38.
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11 files changed

+174
-232
lines changed

11 files changed

+174
-232
lines changed

‎examples/attosoc.py

Lines changed: 44 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -27,29 +27,28 @@
2727

2828

2929
class WBMemory(Component):
30-
@property
31-
def signature(self):
32-
return self._signature
33-
3430
def __init__(self, *, sim=False, num_bytes=0x400):
3531
bus_signature = wishbone.Signature(addr_width=23, data_width=32,
3632
granularity=8)
37-
bus_signature.memory_map = MemoryMap(addr_width=25, data_width=8)
38-
self._signature = Signature({
33+
sig = {
3934
"bus": In(bus_signature)
40-
})
35+
}
4136

4237
if sim:
43-
self._signature.members["ctrl"] = Out(Signature({
38+
sig["ctrl"] = Out(Signature({
4439
"force_ws": Out(1) # noqa: F821
4540
}))
4641

4742
self.sim = sim
4843
self.num_bytes = num_bytes
4944

50-
super().__init__()
51-
bus_signature.memory_map.add_resource(self.bus, name="ram",
52-
size=num_bytes)
45+
super().__init__(sig)
46+
47+
# Allocate a bunch of address space for RAM
48+
self.bus.memory_map = MemoryMap(addr_width=25, data_width=8)
49+
# But only actually _use_ a small chunk of it.
50+
self.bus.memory_map.add_resource(self.bus, name="ram",
51+
size=num_bytes)
5352

5453
@property
5554
def init_mem(self):
@@ -92,16 +91,11 @@ def elaborate(self, plat):
9291

9392

9493
class WBLeds(Component):
95-
@property
96-
def signature(self):
97-
return self._signature
98-
9994
def __init__(self):
10095
bus_signature = wishbone.Signature(addr_width=25, data_width=8,
10196
granularity=8)
102-
bus_signature.memory_map = MemoryMap(addr_width=25, data_width=8,
103-
name="leds")
104-
self._signature = Signature({
97+
98+
super().__init__({
10599
"bus": In(bus_signature),
106100
"leds": Out(8),
107101
"gpio": In(Signature({
@@ -111,14 +105,14 @@ def __init__(self):
111105
})).array(8)
112106
})
113107

114-
super().__init__()
115-
bus_signature.memory_map.add_resource(self.leds,
116-
name="leds", size=1)
117-
bus_signature.memory_map.add_resource(((g.o for g in self.gpio),
118-
(g.i for g in self.gpio)),
119-
name="inout", size=1)
120-
bus_signature.memory_map.add_resource((g.oe for g in self.gpio),
121-
name="oe", size=1)
108+
self.bus.memory_map = MemoryMap(addr_width=25, data_width=8,
109+
name="leds")
110+
self.bus.memory_map.add_resource(self.leds, name="leds", size=1)
111+
self.bus.memory_map.add_resource(((g.o for g in self.gpio),
112+
(g.i for g in self.gpio)),
113+
name="inout", size=1)
114+
self.bus.memory_map.add_resource((g.oe for g in self.gpio),
115+
name="oe", size=1)
122116

123117
def elaborate(self, plat):
124118
m = Module()
@@ -150,14 +144,10 @@ def elaborate(self, plat):
150144

151145

152146
class CSRLeds(Component):
153-
@property
154-
def signature(self):
155-
return self._signature
156-
157147
def __init__(self):
158148
self.mux = csr.bus.Multiplexer(addr_width=4, data_width=8, name="gpio")
159-
self._signature = self.mux.signature
160-
self._signature.members += {
149+
sig = {
150+
"bus": Out(self.mux.signature.members["bus"].signature),
161151
"leds": Out(8),
162152
"gpio": In(Signature({
163153
"i": In(1),
@@ -173,7 +163,8 @@ def __init__(self):
173163
self.mux.add(self.inout_reg, name="inout", addr=4)
174164
self.mux.add(self.oe_reg, name="oe", addr=8)
175165

176-
super().__init__()
166+
super().__init__(sig)
167+
self.bus.memory_map = self.mux.bus.memory_map
177168

178169
def elaborate(self, plat):
179170
m = Module()
@@ -199,22 +190,18 @@ def elaborate(self, plat):
199190

200191

201192
class WBTimer(Component):
202-
@property
203-
def signature(self):
204-
return self._signature
205-
206193
def __init__(self):
207194
bus_signature = wishbone.Signature(addr_width=30, data_width=8,
208195
granularity=8)
209-
bus_signature.memory_map = MemoryMap(addr_width=30, data_width=8,
210-
name="timer")
211-
self._signature = Signature({
196+
197+
super().__init__({
212198
"bus": In(bus_signature),
213199
"irq": Out(1),
214200
})
215201

216-
super().__init__()
217-
bus_signature.memory_map.add_resource(self.irq, name="irq", size=1)
202+
self.bus.memory_map = MemoryMap(addr_width=30, data_width=8,
203+
name="timer")
204+
self.bus.memory_map.add_resource(self.irq, name="irq", size=1)
218205

219206
def elaborate(self, plat):
220207
m = Module()
@@ -247,15 +234,16 @@ def signature(self):
247234
def __init__(self):
248235
self.mux = csr.bus.Multiplexer(addr_width=3, data_width=8,
249236
name="timer")
250-
self._signature = self.mux.signature
251-
self._signature.members += {
237+
sig = {
238+
"bus": Out(self.mux.signature.members["bus"].signature),
252239
"irq": Out(1)
253240
}
254241

255242
self.irq_reg = csr.Element(8, "r", path=("irq",))
256243
self.mux.add(self.irq_reg, name="irq")
257244

258-
super().__init__()
245+
super().__init__(sig)
246+
self.bus.memory_map = self.mux.bus.memory_map
259247

260248
def elaborate(self, plat):
261249
m = Module()
@@ -367,26 +355,21 @@ def elaborate(self, platform):
367355

368356

369357
class WBSerial(Component):
370-
@property
371-
def signature(self):
372-
return self._signature
373-
374358
def __init__(self):
375359
bus_signature = wishbone.Signature(addr_width=30, data_width=8,
376360
granularity=8)
377-
bus_signature.memory_map = MemoryMap(addr_width=30, data_width=8,
378-
name="serial")
379-
self._signature = Signature({
361+
362+
super().__init__({
380363
"bus": In(bus_signature),
381364
"rx": In(1),
382365
"tx": Out(1),
383366
"irq": Out(1),
384367
})
385-
386-
super().__init__()
387-
bus_signature.memory_map.add_resource((self.tx, self.rx), name="rxtx",
388-
size=1)
389-
bus_signature.memory_map.add_resource(self.irq, name="irq", size=1)
368+
self.bus.memory_map = MemoryMap(addr_width=30, data_width=8,
369+
name="serial")
370+
self.bus.memory_map.add_resource((self.tx, self.rx), name="rxtx",
371+
size=1)
372+
self.bus.memory_map.add_resource(self.irq, name="irq", size=1)
390373
self.serial = UART(divisor=12000000 // 9600)
391374

392375
def elaborate(self, plat):
@@ -446,15 +429,11 @@ def elaborate(self, plat):
446429

447430

448431
class CSRSerial(Component):
449-
@property
450-
def signature(self):
451-
return self._signature
452-
453432
def __init__(self):
454433
self.mux = csr.bus.Multiplexer(addr_width=3, data_width=8, alignment=0,
455434
name="serial")
456-
self._signature = self.mux.signature
457-
self._signature.members += {
435+
sig = {
436+
"bus": Out(self.mux.signature.members["bus"].signature),
458437
"rx": In(1),
459438
"tx": Out(1),
460439
"irq": Out(1)
@@ -465,8 +444,9 @@ def __init__(self):
465444
self.irq_reg = csr.Element(8, "r", path=("irq",))
466445
self.mux.add(self.irq_reg, name="irq", addr=4)
467446

468-
super().__init__()
447+
super().__init__(sig)
469448
self.serial = UART(divisor=12000000 // 9600)
449+
self.bus.memory_map = self.mux.bus.memory_map
470450

471451
def elaborate(self, plat):
472452
m = Module()

‎pdm.lock

Lines changed: 10 additions & 11 deletions
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‎pyproject.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ authors = [
88
dependencies = [
99
"m5meta>=1.0.4",
1010
"m5pre>=1.0.3",
11-
"amaranth @ git+https://github.com/amaranth-lang/amaranth@ef5cfa7",
11+
"amaranth @ git+https://github.com/amaranth-lang/amaranth",
1212
]
1313
requires-python = ">=3.11"
1414
readme = "README.md"

‎src/sentinel/alu.py

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -66,19 +66,15 @@ def __init__(self, width):
6666

6767

6868
class ALU(Component):
69-
@property
70-
def signature(self):
71-
return Signature({
69+
# Assumes: op is held steady for duration of op.
70+
def __init__(self, width: int):
71+
self.width = width
72+
super().__init__(Signature({
7273
"a": Out(self.width),
7374
"b": Out(self.width),
7475
"o": In(self.width),
7576
"ctrl": Out(AluCtrlSignature),
76-
}).flip()
77-
78-
# Assumes: op is held steady for duration of op.
79-
def __init__(self, width: int):
80-
self.width = width
81-
super().__init__()
77+
}).flip())
8278

8379
###
8480

‎src/sentinel/control.py

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,8 +22,6 @@
2222

2323

2424
class Control(Component):
25-
signature = ControlSignature
26-
2725
def __init__(self, ucode: Optional[TextIO] = None):
2826
self.ucoderom = UCodeROM(main_file=ucode)
2927
# Enums from microcode ROM.
@@ -73,7 +71,13 @@ def __init__(self, ucode: Optional[TextIO] = None):
7371
self.mem_extend = Signal.like(self.ucoderom.fields.mem_extend)
7472
self.except_ctl = Signal.like(self.ucoderom.fields.except_ctl)
7573

76-
super().__init__()
74+
super().__init__({
75+
"alu": Out(AluCtrlSignature),
76+
"decode": In(1),
77+
"gp": Out(GPControlSignature),
78+
"pc": Out(PCControlSignature),
79+
"csr": Out(CSRControlSignature)
80+
})
7781

7882
def elaborate(self, platform):
7983
m = Module()

‎src/sentinel/datapath.py

Lines changed: 7 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -66,15 +66,9 @@
6666
})
6767

6868

69-
DataPathSignature = Signature({
70-
"gp": Out(GPSignature),
71-
"csr": Out(CSRSignature),
72-
"pc": Out(PcSignature),
73-
})
74-
75-
7669
class ProgramCounter(Component):
77-
signature = PcSignature.flip()
70+
def __init__(self):
71+
super().__init__(PcSignature.flip())
7872

7973
def elaborate(self, platform):
8074
m = Module()
@@ -89,10 +83,8 @@ def elaborate(self, platform):
8983

9084

9185
class RegFile(Component):
92-
signature = Signature({
93-
"pub": In(GPSignature),
94-
"priv": In(PrivateCSRGPSignature)
95-
})
86+
pub: In(GPSignature)
87+
priv: In(PrivateCSRGPSignature)
9688

9789
def __init__(self, *, formal):
9890
self.formal = formal
@@ -152,6 +144,9 @@ def elaborate(self, platform):
152144

153145

154146
class CSRFile(Component):
147+
pub: In(CSRSignature)
148+
priv: Out(PrivateCSRGPSignature)
149+
155150
MSTATUS = 0
156151
MIE = 0x4
157152
MTVEC = 0x5
@@ -160,11 +155,6 @@ class CSRFile(Component):
160155
MCAUSE = 0xA
161156
MIP = 0xC
162157

163-
signature = Signature({
164-
"pub": In(CSRSignature),
165-
"priv": Out(PrivateCSRGPSignature)
166-
})
167-
168158
def elaborate(self, platform):
169159
m = Module()
170160

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