Share JAL and JALR microcode.

Author: cr1901

src/sentinel/microcode.asm

@@ -404,6 +404,7 @@ bgeu: a_src => imm, b_src => pc, latch_a => 1, latch_b => 1, CMP_GEU, \
 
 origin 0x98;
 jalr: b_src => imm, latch_b => 1;
+jalr_shared:
       // Bring in PC and prepare to construct PC + 4. Calculate jmp target.
       latch_a => 1, latch_b => 1, a_src => four, b_src => pc, alu_op => add, \
         alu_o_mod => clear_lsb_o;
@@ -442,18 +443,8 @@ sw_wait:  mem_req => 1, invert_test => 1, cond_test => mem_valid, \
           STOP_MEMREQ_THEN_JUMP_TO_ZERO;
 
 origin 0xB0;
-jal: a_src => imm, b_src => pc, latch_a => 1, latch_b => 1;
-     // Prepare to construct PC + 4. Calculate jmp target.
-     latch_a => 1, a_src => four, alu_op => add, alu_o_mod => clear_lsb_o;
-     // PC + 4 available on next cycle, just in time to be stored in RD.
-     // Preemptively load target PC. If there's an exception, make sure the old
-     // PC is still available on ALU output so we can reload.
-     a_src => zero, latch_a => 1, pc_action => load_alu_o, alu_op => add, \
-        except_ctl => latch_jal, jmp_type => direct, cond_test => exception, \
-        invert_test => 1, target => fast_epilog;
-     // Exception detected. Pass the old PC through, and then reload.
-     alu_op => add, jmp_type => direct, cond_test => true, \
-         target => branch_exception_detected;
+jal: a_src => imm, b_src => pc, latch_a => 1, latch_b => 1, \
+        jmp_type => direct, target => jalr_shared;
 
 fast_epilog: INSN_FETCH_EAGER_READ_RS1, WRITE_RD, SKIP_WAIT_IF_ACK;
 fast_epilog_csr: INSN_FETCH_EAGER_READ_RS1, WRITE_RD_CSR, SKIP_WAIT_IF_ACK;