[BUG] Array interface of load -> compute -> store in systolic tile

[kaizizzzzzz]

Describe the bug
In our hls code of packed_systolic, the interface tile of load->compute and compute->load is using array, which will cause incorrect result when testing on board. Csim is correct because the cpu simulator can't actually perform "dataflow".

To Reproduce
Provide test cases to reproduce the error.
Any case using "packed_systolic" in "/playground/int8_gemm.py" will have this bug.

Buggy output
Provide the output of the buggy program.
unexpected output value.

Expected behavior
A clear and concise description of what you expected to happen.
change the array interface described above to stream interface.

Additional context
Add any other context about the problem here.