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Describe the bug
Valid syntax rejected. Verible-verilog-syntax does not seem to support a dimensioned parameter in a list of parameter assignments.
Version
% verible-verilog-syntax --version v0.0-3471-g9cb45092 Commit 2023-12-23 Built 2023-12-23T08:07:18Z
To Reproduce
Given testme.sv as follows:
testme.sv
module testme (sig1, sig2); parameter integer PRAM1 = 0, PRAM_ARY [3:0] = '{default:8}; input sig1; output logic sig2; assign sig2 = (PRAM_ARY[1]>4)? sig1 : '0; endmodule
Run
verible-verilog-syntax testme.sv
Actual behavior:
Code rejected
testme.sv:6:14: syntax error at token "["
Expected behavior
Accepts syntax
SV-2017 spec section 6.20.1 Parameter declaration syntax
parameter_declaration ::= parameter data_type_or_implicit list_of_param_assignments | parameter type list_of_type_assignments list_of_param_assignments ::= param_assignment { , param_assignment } param_assignment ::= parameter_identifier { unpacked_dimension } [ = constant_param_expression ]
parameter_declaration ::= parameter data_type_or_implicit list_of_param_assignments | parameter type list_of_type_assignments
list_of_param_assignments ::= param_assignment { , param_assignment }
param_assignment ::= parameter_identifier { unpacked_dimension } [ = constant_param_expression ]
The text was updated successfully, but these errors were encountered:
No branches or pull requests
Describe the bug
Valid syntax rejected. Verible-verilog-syntax does not seem to support a dimensioned parameter in a list of parameter assignments.
Version
To Reproduce
Given
testme.sv
as follows:Run
verible-verilog-syntax testme.sv
Actual behavior:
Code rejected
testme.sv:6:14: syntax error at token "["
Expected behavior
Accepts syntax
SV-2017 spec section 6.20.1 Parameter declaration syntax
The text was updated successfully, but these errors were encountered: