diff --git a/interp/src/flatten/flat_ir/base.rs b/interp/src/flatten/flat_ir/base.rs
index ab3d52cb0..e92d08fc4 100644
--- a/interp/src/flatten/flat_ir/base.rs
+++ b/interp/src/flatten/flat_ir/base.rs
@@ -538,11 +538,15 @@ impl AssignedValue {
         self
     }
 
-    pub fn set_propagate_clocks(mut self) -> Self {
+    pub fn with_propagate_clocks(mut self) -> Self {
         self.propagate_clocks = true;
         self
     }
 
+    pub fn set_propagate_clocks(&mut self, propagate_clocks: bool) {
+        self.propagate_clocks = propagate_clocks;
+    }
+
     /// Returns true if the two AssignedValues do not have the same winner
     pub fn has_conflict_with(&self, other: &Self) -> bool {
         self.winner != other.winner
diff --git a/interp/src/flatten/structures/environment/env.rs b/interp/src/flatten/structures/environment/env.rs
index 0896a4c52..a80e0e083 100644
--- a/interp/src/flatten/structures/environment/env.rs
+++ b/interp/src/flatten/structures/environment/env.rs
@@ -2437,7 +2437,7 @@ impl<C: AsRef<Context> + Clone> Simulator<C> {
                                         .with_transitive_clocks_opt(
                                             val.transitive_clocks().cloned(),
                                         )
-                                        .set_propagate_clocks();
+                                        .with_propagate_clocks();
                                     // direct clock becomes a transitive clock
                                     // on assignment
                                     if let Some(c) = val.clocks() {
@@ -2707,6 +2707,14 @@ impl<C: AsRef<Context> + Clone> Simulator<C> {
                                 .as_option_mut()
                                 .unwrap()
                                 .add_transitive_clocks(set_extension);
+
+                            // this is necessary for ports which were implicitly
+                            // assigned zero and is redundant for other ports
+                            // which will already have propagate_clocks set
+                            self.env.ports[dest]
+                                .as_option_mut()
+                                .unwrap()
+                                .set_propagate_clocks(true);
                         }
                     }
                 }