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bunniebunnie
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update bio tests for clkmode option
1 parent 7ce1986 commit dff5bc7

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3 files changed

+202
-13
lines changed

3 files changed

+202
-13
lines changed

‎libs/xous-bio-bdma/src/bio_tests/dma.rs‎

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
use core::mem::size_of;
22

33
use utra::bio_bdma::SFR_CFGINFO;
4+
use utralib::utra::bio_bdma::SFR_CONFIG_CLOCKING_MODE;
45

56
use crate::*;
67

@@ -84,7 +85,7 @@ pub fn filter_test() -> usize {
8485
bio_ss.bio.wo(utra::bio_bdma::SFR_FILTER_BOUNDS_2, (0x6000_0000 - HW_IOX_BASE as u32) >> 12);
8586

8687
// with the filters so set, test some transactions that "should" pass
87-
if dma_basic(false) != 4 {
88+
if dma_basic(false, 0) != 4 {
8889
passing = false;
8990
print!("DMA Filter: allowed transactions are incorrectly blocked");
9091
};
@@ -195,7 +196,7 @@ pub fn filter_test() -> usize {
195196
///
196197
/// The `concurrent` flag causes the CPU to do concurrent traffic during the test to
197198
/// exercise contention on AXI bus.
198-
pub fn dma_basic(concurrent: bool) -> usize {
199+
pub fn dma_basic(concurrent: bool, clkmode: u8) -> usize {
199200
const TEST_LEN: usize = 64;
200201
let mut passing = 0;
201202
if !concurrent {
@@ -212,6 +213,9 @@ pub fn dma_basic(concurrent: bool) -> usize {
212213
bio_ss.bio.wo(utra::bio_bdma::SFR_CTRL, 0x0);
213214
bio_ss.load_code(dma_basic_code(), 0, BioCore::Core0);
214215

216+
// setup clocking mode option
217+
bio_ss.bio.rmwf(SFR_CONFIG_CLOCKING_MODE, clkmode as u32);
218+
215219
// These actually "don't matter" because there are no synchronization instructions in the code
216220
// Everything runs at "full tilt"
217221
bio_ss.bio.wo(utra::bio_bdma::SFR_QDIV0, 0x1_0000);
@@ -640,7 +644,7 @@ bio_code!(dma_mc_dst_addr_code, DMA_MC_DST_ADDR_START, DMA_MC_DST_ADDR_END,
640644
);
641645

642646
/// Attempt to fire off all four engines at once, simultaneously, for maximum bus contention
643-
pub fn dma_coincident() -> usize {
647+
pub fn dma_coincident(clkmode: u8) -> usize {
644648
let mut passing = 0;
645649
print!("DMA coincident\r");
646650
// clear prior test config state
@@ -651,6 +655,9 @@ pub fn dma_coincident() -> usize {
651655
// reset all the fifos
652656
bio_ss.bio.wo(utra::bio_bdma::SFR_FIFO_CLR, 0xF);
653657

658+
// setup clocking mode option
659+
bio_ss.bio.rmwf(SFR_CONFIG_CLOCKING_MODE, clkmode as u32);
660+
654661
// stop all the machines, so that code can be loaded
655662
bio_ss.bio.wo(utra::bio_bdma::SFR_CTRL, 0x0);
656663
bio_ss.load_code(dma_coincident_code(), 0, BioCore::Core0);

‎utralib/cramium/core.svd‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
44
<vendor>litex</vendor>
55
<name>SOC</name>
6-
<description><![CDATA[Litex SoC 2025-01-11 17:47:31]]></description>
6+
<description><![CDATA[Litex SoC 2025-02-08 04:21:32]]></description>
77

88
<addressUnitBits>8</addressUnitBits>
99
<width>32</width>

‎utralib/cramium/daric.svd‎

Lines changed: 191 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -552,6 +552,14 @@ bit position to clear the flag]]></description>
552552
<description><![CDATA[qs0err flag register. `1` means event happened, write back `1` in respective bit
553553
position to clear the flag]]></description>
554554
</field>
555+
<field>
556+
<name>aluinvld</name>
557+
<msb>5</msb>
558+
<bitRange>[5:5]</bitRange>
559+
<lsb>5</lsb>
560+
<description><![CDATA[aluinvld flag register. `1` means event happened, write back `1` in respective
561+
bit position to clear the flag]]></description>
562+
</field>
555563
</fields>
556564
</register>
557565
<register>
@@ -1124,6 +1132,13 @@ bit position to clear the flag]]></description>
11241132
<lsb>4</lsb>
11251133
<description><![CDATA[tsmode read/write control register]]></description>
11261134
</field>
1135+
<field>
1136+
<name>cr_opt_ifskey</name>
1137+
<msb>5</msb>
1138+
<bitRange>[5:5]</bitRange>
1139+
<lsb>5</lsb>
1140+
<description><![CDATA[cr_opt.ifskey read/write control register]]></description>
1141+
</field>
11271142
</fields>
11281143
</register>
11291144
<register>
@@ -1569,10 +1584,74 @@ bit position to clear the flag]]></description>
15691584
</field>
15701585
</fields>
15711586
</register>
1587+
<register>
1588+
<name>SFR_TICKCYC</name>
1589+
<description><![CDATA[See file:///F:/code/cram-nto/modules/crypto_top/rtl/pke.sv]]></description>
1590+
<addressOffset>0x0050</addressOffset>
1591+
<resetValue>0x00</resetValue>
1592+
<size>32</size>
1593+
<fields>
1594+
<field>
1595+
<name>sfr_tickcyc</name>
1596+
<msb>7</msb>
1597+
<bitRange>[7:0]</bitRange>
1598+
<lsb>0</lsb>
1599+
<description><![CDATA[sfr_tickcyc read/write control register]]></description>
1600+
</field>
1601+
</fields>
1602+
</register>
1603+
<register>
1604+
<name>SFR_TICKCNT</name>
1605+
<description><![CDATA[See file:///F:/code/cram-nto/modules/crypto_top/rtl/pke.sv]]></description>
1606+
<addressOffset>0x0054</addressOffset>
1607+
<resetValue>0x00</resetValue>
1608+
<size>32</size>
1609+
<fields>
1610+
<field>
1611+
<name>sfr_tickcnt</name>
1612+
<msb>31</msb>
1613+
<bitRange>[31:0]</bitRange>
1614+
<lsb>0</lsb>
1615+
<description><![CDATA[sfr_tickcnt read only status register]]></description>
1616+
</field>
1617+
</fields>
1618+
</register>
1619+
<register>
1620+
<name>SFR_MASKSEED</name>
1621+
<description><![CDATA[See file:///F:/code/cram-nto/modules/crypto_top/rtl/pke.sv]]></description>
1622+
<addressOffset>0x0060</addressOffset>
1623+
<resetValue>0x00</resetValue>
1624+
<size>32</size>
1625+
<fields>
1626+
<field>
1627+
<name>sfr_maskseed</name>
1628+
<msb>31</msb>
1629+
<bitRange>[31:0]</bitRange>
1630+
<lsb>0</lsb>
1631+
<description><![CDATA[sfr_maskseed read/write control register]]></description>
1632+
</field>
1633+
</fields>
1634+
</register>
1635+
<register>
1636+
<name>SFR_MASKSEEDAR</name>
1637+
<description><![CDATA[See file:///F:/code/cram-nto/modules/crypto_top/rtl/pke.sv]]></description>
1638+
<addressOffset>0x0064</addressOffset>
1639+
<resetValue>0x00</resetValue>
1640+
<size>32</size>
1641+
<fields>
1642+
<field>
1643+
<name>sfr_maskseedar</name>
1644+
<msb>31</msb>
1645+
<bitRange>[31:0]</bitRange>
1646+
<lsb>0</lsb>
1647+
<description><![CDATA[sfr_maskseedar performs action on write of value: 0x5a]]></description>
1648+
</field>
1649+
</fields>
1650+
</register>
15721651
</registers>
15731652
<addressBlock>
15741653
<offset>0</offset>
1575-
<size>0x44</size>
1654+
<size>0x68</size>
15761655
<usage>registers</usage>
15771656
</addressBlock>
15781657
</peripheral>
@@ -2090,10 +2169,42 @@ position to clear the flag]]></description>
20902169
</field>
20912170
</fields>
20922171
</register>
2172+
<register>
2173+
<name>SFR_WDATABYPASS_MODE</name>
2174+
<description><![CDATA[See file:///F:/code/cram-nto/modules/crypto_top/rtl/scedma.sv]]></description>
2175+
<addressOffset>0x0070</addressOffset>
2176+
<resetValue>0x00</resetValue>
2177+
<size>32</size>
2178+
<fields>
2179+
<field>
2180+
<name>sfr_wdatabypass_mode</name>
2181+
<msb>1</msb>
2182+
<bitRange>[1:0]</bitRange>
2183+
<lsb>0</lsb>
2184+
<description><![CDATA[sfr_wdatabypass_mode read/write control register]]></description>
2185+
</field>
2186+
</fields>
2187+
</register>
2188+
<register>
2189+
<name>SFR_WDATABYPASS_DATA</name>
2190+
<description><![CDATA[See file:///F:/code/cram-nto/modules/crypto_top/rtl/scedma.sv]]></description>
2191+
<addressOffset>0x0074</addressOffset>
2192+
<resetValue>0x00</resetValue>
2193+
<size>32</size>
2194+
<fields>
2195+
<field>
2196+
<name>sfr_wdatabypass_data</name>
2197+
<msb>31</msb>
2198+
<bitRange>[31:0]</bitRange>
2199+
<lsb>0</lsb>
2200+
<description><![CDATA[sfr_wdatabypass_data read/write control register]]></description>
2201+
</field>
2202+
</fields>
2203+
</register>
20932204
</registers>
20942205
<addressBlock>
20952206
<offset>0</offset>
2096-
<size>0x64</size>
2207+
<size>0x78</size>
20972208
<usage>registers</usage>
20982209
</addressBlock>
20992210
</peripheral>
@@ -2393,10 +2504,74 @@ bit position to clear the flag]]></description>
23932504
</field>
23942505
</fields>
23952506
</register>
2507+
<register>
2508+
<name>SFR_TS_SR_TS0</name>
2509+
<description><![CDATA[See file:///F:/code/cram-nto/modules/crypto_top/rtl/sce_glbsfra.sv]]></description>
2510+
<addressOffset>0x00e0</addressOffset>
2511+
<resetValue>0x00</resetValue>
2512+
<size>32</size>
2513+
<fields>
2514+
<field>
2515+
<name>sr_ts0</name>
2516+
<msb>31</msb>
2517+
<bitRange>[31:0]</bitRange>
2518+
<lsb>0</lsb>
2519+
<description><![CDATA[sr_ts read only status register]]></description>
2520+
</field>
2521+
</fields>
2522+
</register>
2523+
<register>
2524+
<name>SFR_TS_SR_TS1</name>
2525+
<description><![CDATA[See file:///F:/code/cram-nto/modules/crypto_top/rtl/sce_glbsfra.sv]]></description>
2526+
<addressOffset>0x00e4</addressOffset>
2527+
<resetValue>0x00</resetValue>
2528+
<size>32</size>
2529+
<fields>
2530+
<field>
2531+
<name>sr_ts1</name>
2532+
<msb>31</msb>
2533+
<bitRange>[31:0]</bitRange>
2534+
<lsb>0</lsb>
2535+
<description><![CDATA[sr_ts read only status register]]></description>
2536+
</field>
2537+
</fields>
2538+
</register>
2539+
<register>
2540+
<name>SFR_TS_SR_TS2</name>
2541+
<description><![CDATA[See file:///F:/code/cram-nto/modules/crypto_top/rtl/sce_glbsfra.sv]]></description>
2542+
<addressOffset>0x00e8</addressOffset>
2543+
<resetValue>0x00</resetValue>
2544+
<size>32</size>
2545+
<fields>
2546+
<field>
2547+
<name>sr_ts2</name>
2548+
<msb>31</msb>
2549+
<bitRange>[31:0]</bitRange>
2550+
<lsb>0</lsb>
2551+
<description><![CDATA[sr_ts read only status register]]></description>
2552+
</field>
2553+
</fields>
2554+
</register>
2555+
<register>
2556+
<name>SFR_TS_SR_TS3</name>
2557+
<description><![CDATA[See file:///F:/code/cram-nto/modules/crypto_top/rtl/sce_glbsfra.sv]]></description>
2558+
<addressOffset>0x00ec</addressOffset>
2559+
<resetValue>0x00</resetValue>
2560+
<size>32</size>
2561+
<fields>
2562+
<field>
2563+
<name>sr_ts3</name>
2564+
<msb>31</msb>
2565+
<bitRange>[31:0]</bitRange>
2566+
<lsb>0</lsb>
2567+
<description><![CDATA[sr_ts read only status register]]></description>
2568+
</field>
2569+
</fields>
2570+
</register>
23962571
</registers>
23972572
<addressBlock>
23982573
<offset>0</offset>
2399-
<size>0x64</size>
2574+
<size>0xf0</size>
24002575
<usage>registers</usage>
24012576
</addressBlock>
24022577
</peripheral>
@@ -3376,7 +3551,7 @@ position to clear the flag]]></description>
33763551
<msb>7</msb>
33773552
<bitRange>[7:0]</bitRange>
33783553
<lsb>0</lsb>
3379-
<description><![CDATA[sfr_aclkgr read/write control register]]></description>
3554+
<description><![CDATA[sfr_aclkgr read only status register]]></description>
33803555
</field>
33813556
</fields>
33823557
</register>
@@ -3392,7 +3567,7 @@ position to clear the flag]]></description>
33923567
<msb>7</msb>
33933568
<bitRange>[7:0]</bitRange>
33943569
<lsb>0</lsb>
3395-
<description><![CDATA[sfr_hclkgr read/write control register]]></description>
3570+
<description><![CDATA[sfr_hclkgr read only status register]]></description>
33963571
</field>
33973572
</fields>
33983573
</register>
@@ -3408,7 +3583,7 @@ position to clear the flag]]></description>
34083583
<msb>7</msb>
34093584
<bitRange>[7:0]</bitRange>
34103585
<lsb>0</lsb>
3411-
<description><![CDATA[sfr_iclkgr read/write control register]]></description>
3586+
<description><![CDATA[sfr_iclkgr read only status register]]></description>
34123587
</field>
34133588
</fields>
34143589
</register>
@@ -3424,7 +3599,7 @@ position to clear the flag]]></description>
34243599
<msb>7</msb>
34253600
<bitRange>[7:0]</bitRange>
34263601
<lsb>0</lsb>
3427-
<description><![CDATA[sfr_pclkgr read/write control register]]></description>
3602+
<description><![CDATA[sfr_pclkgr read only status register]]></description>
34283603
</field>
34293604
</fields>
34303605
</register>
@@ -3738,6 +3913,13 @@ respective bit position to clear the flag]]></description>
37383913
<lsb>7</lsb>
37393914
<description><![CDATA[disable_filter_mem read/write control register]]></description>
37403915
</field>
3916+
<field>
3917+
<name>clocking_mode</name>
3918+
<msb>9</msb>
3919+
<bitRange>[9:8]</bitRange>
3920+
<lsb>8</lsb>
3921+
<description><![CDATA[clocking_mode read/write control register]]></description>
3922+
</field>
37413923
</fields>
37423924
</register>
37433925
<register>
@@ -10517,8 +10699,8 @@ position to clear the flag]]></description>
1051710699
<fields>
1051810700
<field>
1051910701
<name>vdena</name>
10520-
<msb>3</msb>
10521-
<bitRange>[3:0]</bitRange>
10702+
<msb>5</msb>
10703+
<bitRange>[5:0]</bitRange>
1052210704
<lsb>0</lsb>
1052310705
<description><![CDATA[vdena read/write control register]]></description>
1052410706
</field>

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