diff --git a/RELEASE-v0.9.md b/RELEASE-v0.9.md index ed328f8c0..833037231 100644 --- a/RELEASE-v0.9.md +++ b/RELEASE-v0.9.md @@ -484,7 +484,14 @@ perform the Xous firmware upgrade. This requires running manual update commands, - Mailbox protocol to other devices has been tested, working. - TRNG has been tuned, partially validated. - BIO-BDMA test cases added -- Various fixes to track changes in Rust 1.80 + - Full USB mass storage stack added in loader mode + - Interactive USB updates via loader mode + - Camera driver with live preview + - QR code decoding (up to version 8) +- mini-gfx: + - New graphics crate for small screen targets that does not require windows or borders. Drops the GAM, condenses APIs together for smaller memory footprint devices. + - Very much a WIP +- Various fixes to track changes in Rust 1.80/1.81/1.82/1.83 - Add documentation to the `modals` library (thanks @rowr111) - Due to a breaking change in Renode, this release is only compatible with Renode equal to or later than 1.15.2.7965（e6e79aad-202408180425) (see issue #570 / PR #572) - Migrate to `rkyv` v0.8+. diff --git a/libs/cramium-hal/Cargo.toml b/libs/cramium-hal/Cargo.toml index 37ec79007..0fe0fb902 100644 --- a/libs/cramium-hal/Cargo.toml +++ b/libs/cramium-hal/Cargo.toml @@ -39,6 +39,8 @@ board-baosec = [ board-baosor = ["camera-ov2640", "axp2101"] # Precursor form factor board-dabao = [] # Dev board form factor verilator-only = [] +mpw = [] +hdl-test = [] udma-stress-test = [ ] # For RTL simulation testing - aggravates a key corner case @@ -47,4 +49,4 @@ compress-entropy = [] magic-manual = [] std = ["log", "xous-api-names", "usb-device", "xous-api-ticktimer"] derive-rkyv = ["rkyv"] -default = [] +default = ["hdl-test"] diff --git a/libs/cramium-hal/src/ov2640/ov2640.rs b/libs/cramium-hal/src/ov2640/ov2640.rs index bda70b80d..5bf82ddc1 100644 --- a/libs/cramium-hal/src/ov2640/ov2640.rs +++ b/libs/cramium-hal/src/ov2640/ov2640.rs @@ -215,6 +215,8 @@ impl Ov2640 { /// TODO: figure out how to length-bound this to...the frame slice size? line size? idk... pub unsafe fn rx_buf_phys(&self) -> &[T] { &self.ifram.as_ref().unwrap().as_phys_slice() } + /// TODO: Rework this to use the frame sync + automatic re-initiation on capture_await() for frames + /// TODO: Also make an interrupt driven version of this. pub fn capture_async(&mut self) { // we want the sliced resolution so resolve resolution through the method call wrapper let (cols, rows) = self.resolution(); diff --git a/libs/cramium-hal/src/udma/i2c.rs b/libs/cramium-hal/src/udma/i2c.rs index 607ac0553..9e32570d0 100644 --- a/libs/cramium-hal/src/udma/i2c.rs +++ b/libs/cramium-hal/src/udma/i2c.rs @@ -4,7 +4,19 @@ use crate::ifram::IframRange; use crate::udma::*; use crate::udma::{Bank, Udma}; +#[cfg(not(feature = "hdl-test"))] const TIMEOUT_ITERS: usize = 1_000_000; +#[cfg(feature = "hdl-test")] +const TIMEOUT_ITERS: usize = 5000; + +// MPW had this register: +// pub const REG_SETUP: crate::Register = crate::Register::new(13, 0x1); +// pub const REG_SETUP_R_DO_RST: crate::Field = crate::Field::new(1, 0, REG_SETUP); +// It is gone in NTO and we use the UDMA system reset instead +#[cfg(feature = "mpw")] +const SETUP_OFFSET: usize = 13; +#[cfg(feature = "mpw")] +const DO_RST_MASK: usize = 1; #[derive(Copy, Clone)] #[repr(u8)] @@ -75,9 +87,12 @@ const MAX_I2C_TXLEN: usize = 512; const MAX_I2C_RXLEN: usize = 512; const MAX_I2C_CMDLEN: usize = 512; -pub struct I2c { +pub struct I2c<'a> { csr: CSR, - _channel: I2cChannel, + #[allow(dead_code)] // used in NTO + udma_global: &'a dyn UdmaGlobalConfig, + #[allow(dead_code)] // used in NTO + channel: I2cChannel, divider: u16, perclk_freq: u32, pub ifram: IframRange, @@ -91,20 +106,25 @@ pub struct I2c { pending: I2cPending, } -impl Udma for I2c { +impl Udma for I2c<'_> { fn csr_mut(&mut self) -> &mut CSR { &mut self.csr } fn csr(&self) -> &CSR { &self.csr } } -impl I2c { +impl<'a> I2c<'a> { /// Safety: called only after global clock for I2C channel is enabled. /// It is also unsafe to `Drop` because you have to cleanup the clock manually. #[cfg(feature = "std")] - pub unsafe fn new(channel: I2cChannel, i2c_freq: u32, perclk_freq: u32) -> Option { + pub unsafe fn new( + channel: I2cChannel, + i2c_freq: u32, + perclk_freq: u32, + udma_global: &'a dyn UdmaGlobalConfig, + ) -> Option { // one page is the minimum size we can request if let Some(ifram) = IframRange::request(4096, None) { - Some(I2c::new_with_ifram(channel, i2c_freq, perclk_freq, ifram)) + Some(I2c::new_with_ifram(channel, i2c_freq, perclk_freq, ifram, udma_global)) } else { None } @@ -115,6 +135,7 @@ impl I2c { i2c_freq: u32, perclk_freq: u32, ifram: IframRange, + udma_global: &'a dyn UdmaGlobalConfig, ) -> Self { // divide-by-4 is an empirical observation let divider: u16 = ((((perclk_freq / 2) / i2c_freq) / 4).min(u16::MAX as u32)) as u16; @@ -134,18 +155,33 @@ impl I2c { ) .expect("couldn't map i2c port"); #[cfg(target_os = "xous")] + #[allow(unused_mut)] // because it is used when `mpw` feature is selected let mut csr = CSR::new(csr_range.as_mut_ptr() as *mut u32); #[cfg(not(target_os = "xous"))] + #[allow(unused_mut)] // because it is used when `mpw` feature is selected let mut csr = CSR::new(base_addr as *mut u32); - // reset the block - csr.wfo(utra::udma_i2c_0::REG_SETUP_R_DO_RST, 1); - csr.wo(utra::udma_i2c_0::REG_SETUP, 0); + // reset the block, if MPW. If NTO, this is handled by udma global + #[cfg(feature = "mpw")] + unsafe { + csr.base().add(SETUP_OFFSET).write_volatile(DO_RST_MASK as u32); + csr.base().add(SETUP_OFFSET).write_volatile(0); + } + #[cfg(not(feature = "mpw"))] + { + udma_global.reset(match channel { + I2cChannel::Channel0 => PeriphId::I2c0, + I2cChannel::Channel1 => PeriphId::I2c1, + I2cChannel::Channel2 => PeriphId::I2c2, + I2cChannel::Channel3 => PeriphId::I2c3, + }); + } // one page is the minimum size we can request let ifram_base = ifram.virt_range.as_ptr() as usize; let ifram_base_phys = ifram.phys_range.as_ptr() as usize; let mut i2c = I2c { csr, - _channel: channel, + udma_global, + channel, ifram, divider, cmd_buf: unsafe { core::slice::from_raw_parts_mut(ifram_base as *mut u32, MAX_I2C_CMDLEN) }, @@ -221,8 +257,22 @@ impl I2c { self.udma_reset(Bank::Custom); self.udma_reset(Bank::Tx); self.udma_reset(Bank::Rx); - self.csr.wfo(utra::udma_i2c_0::REG_SETUP_R_DO_RST, 1); - self.csr.wo(utra::udma_i2c_0::REG_SETUP, 0); + // reset the block, if MPW. If NTO, this needs to be handled by the upper level code with a + // reset to udma_global + #[cfg(feature = "mpw")] + unsafe { + self.csr.base().add(SETUP_OFFSET).write_volatile(DO_RST_MASK as u32); + self.csr.base().add(SETUP_OFFSET).write_volatile(0); + } + #[cfg(not(feature = "mpw"))] + { + self.udma_global.reset(match self.channel { + I2cChannel::Channel0 => PeriphId::I2c0, + I2cChannel::Channel1 => PeriphId::I2c1, + I2cChannel::Channel2 => PeriphId::I2c2, + I2cChannel::Channel3 => PeriphId::I2c3, + }); + } self.send_cmd_list(&[I2cCmd::Config(self.divider)]); self.pending.take(); @@ -236,7 +286,10 @@ impl I2c { let ret = match self.pending.take() { I2cPending::Read(len) => { if let Some(buf) = rx_buf { + #[cfg(feature = "mpw")] buf[..len].copy_from_slice(&self.rx_buf[3..3 + len]); + #[cfg(not(feature = "mpw"))] + buf[..len].copy_from_slice(&self.rx_buf[..len]); Ok(len) } else { // the pending transaction was a read, but the user did not call us @@ -250,14 +303,66 @@ impl I2c { ret } + pub fn reset(&mut self) { + // reset the block + self.udma_reset(Bank::Custom); + self.udma_reset(Bank::Tx); + self.udma_reset(Bank::Rx); + // reset the block, if MPW. If NTO, this needs to be handled by the upper level code with a + // reset to udma_global + #[cfg(feature = "mpw")] + unsafe { + self.csr.base().add(SETUP_OFFSET).write_volatile(DO_RST_MASK as u32); + self.csr.base().add(SETUP_OFFSET).write_volatile(0); + } + #[cfg(not(feature = "mpw"))] + { + self.udma_global.reset(match self.channel { + I2cChannel::Channel0 => PeriphId::I2c0, + I2cChannel::Channel1 => PeriphId::I2c1, + I2cChannel::Channel2 => PeriphId::I2c2, + I2cChannel::Channel3 => PeriphId::I2c3, + }); + } + + self.send_cmd_list(&[I2cCmd::Config(self.divider)]); + self.pending.take(); + } + fn busy(&self) -> bool { self.csr.rf(utra::udma_i2c_0::REG_STATUS_R_BUSY) != 0 - || self.csr.rf(utra::udma_i2c_0::REG_STATUS_R_BUSY) != 0 || self.udma_busy(Bank::Custom) || self.udma_busy(Bank::Tx) || self.udma_busy(Bank::Rx) } + /// Basically, does a read from an I2C address without specifying a register. The protocol + /// would not make sense for any real-world application, but it is an MVP than exercises + /// both a write (to specify the device address) and a read (the response data) form of + /// the I2C PHY protocol. + #[cfg(feature = "hdl-test")] + #[allow(dead_code)] + pub fn i2c_hdl_test(&mut self, byte: u8) -> Result { + self.new_tranaction(); + self.push_cmd(I2cCmd::Config(self.divider)); + self.push_cmd(I2cCmd::Start); + self.push_cmd(I2cCmd::WriteByte(byte << 1 | 0x1)); // issue a read + self.push_cmd(I2cCmd::RdNack); + self.push_cmd(I2cCmd::Stop); + + // safety: this is safe because the cmd_buf_phys() slice is passed to a function that only + // uses it as a base/bounds reference and it will not actually access the data. + unsafe { + self.udma_enqueue(Bank::Rx, &self.rx_buf_phys[..1], CFG_EN); + self.udma_enqueue(Bank::Custom, &self.cmd_buf_phys[..self.seq_len], CFG_EN); + } + self.pending = I2cPending::Read(1); + + let mut rx = [0u8]; + self.i2c_await(Some(&mut rx), false)?; + Ok(rx[0]) + } + pub fn i2c_write_async(&mut self, dev: u8, adr: u8, data: &[u8]) -> Result { // The implementation of this is gross because we have to stuff the command list assert!(data.len() < 256); // is is a conservative bound, the limit is due to the cmd buf length limit @@ -280,6 +385,13 @@ impl I2c { self.udma_enqueue(Bank::Tx, &self.tx_buf_phys[..data.len()], CFG_EN); self.udma_enqueue(Bank::Custom, &self.cmd_buf_phys[..self.seq_len], CFG_EN); } + // wait for the commands to propagate before returning + #[cfg(not(feature = "mpw"))] + while self.csr.rf(utra::udma_i2c_0::REG_STATUS_R_BUSY) == 0 + || self.csr.rf(utra::udma_i2c_0::REG_CMD_SIZE_R_CMD_SIZE) != 0 + {} + #[cfg(feature = "mpw")] + while self.csr.rf(utra::udma_i2c_0::REG_STATUS_R_BUSY) == 0 {} self.pending = I2cPending::Write(data.len()); Ok(data.len()) } @@ -297,8 +409,20 @@ impl I2c { // block has to be reset on every start transaction due to a... bug? programming error? // where the Rx length is mismatched from the actual length of Rx data expected because // it seems the Rx buffer pointer increments even during Tx events. - self.csr.wfo(utra::udma_i2c_0::REG_SETUP_R_DO_RST, 1); - self.csr.wo(utra::udma_i2c_0::REG_SETUP, 0); + #[cfg(feature = "mpw")] + unsafe { + self.csr.base().add(SETUP_OFFSET).write_volatile(DO_RST_MASK as u32); + self.csr.base().add(SETUP_OFFSET).write_volatile(0); + } + #[cfg(not(feature = "mpw"))] + { + self.udma_global.reset(match self.channel { + I2cChannel::Channel0 => PeriphId::I2c0, + I2cChannel::Channel1 => PeriphId::I2c1, + I2cChannel::Channel2 => PeriphId::I2c2, + I2cChannel::Channel3 => PeriphId::I2c3, + }); + } // into the pre-allocated Tx buf self.new_tranaction(); @@ -319,16 +443,26 @@ impl I2c { // safety: this is safe because the cmd_buf_phys() slice is passed to a function that only // uses it as a base/bounds reference and it will not actually access the data. unsafe { - // the extra 3 are dummy bytes that were received while the address was being set up + // the extra 3 are dummy bytes that were received while the address was being set up - MPW bug + #[cfg(feature = "mpw")] self.udma_enqueue(Bank::Rx, &self.rx_buf_phys[..len + 3], CFG_EN); + #[cfg(not(feature = "mpw"))] + self.udma_enqueue(Bank::Rx, &self.rx_buf_phys[..len], CFG_EN); self.udma_enqueue(Bank::Custom, &self.cmd_buf_phys[..self.seq_len], CFG_EN); } + // wait for the commands to propagate before returning + #[cfg(not(feature = "mpw"))] + while self.csr.rf(utra::udma_i2c_0::REG_STATUS_R_BUSY) == 0 + || self.csr.rf(utra::udma_i2c_0::REG_CMD_SIZE_R_CMD_SIZE) != 0 + {} + #[cfg(feature = "mpw")] + while self.csr.rf(utra::udma_i2c_0::REG_STATUS_R_BUSY) == 0 {} self.pending = I2cPending::Read(len); Ok(len) } } -impl I2cApi for I2c { +impl I2cApi for I2c<'_> { fn i2c_read( &mut self, dev: u8, diff --git a/libs/cramium-hal/src/udma/mod.rs b/libs/cramium-hal/src/udma/mod.rs index 19da2b93b..4f1d0fe30 100644 --- a/libs/cramium-hal/src/udma/mod.rs +++ b/libs/cramium-hal/src/udma/mod.rs @@ -28,6 +28,7 @@ use crate::SharedCsr; enum GlobalReg { ClockGate = 0, EventIn = 1, + Reset = 2, } impl Into for GlobalReg { fn into(self) -> usize { self as usize } @@ -241,6 +242,7 @@ pub trait UdmaGlobalConfig { event_type: PeriphEventType, to_channel: EventChannel, ); + fn reset(&self, peripheral: PeriphId); } #[repr(u32)] @@ -319,6 +321,20 @@ impl GlobalConfig { // Safety: only safe when used in the context of UDMA registers. unsafe { self.csr.base().add(GlobalReg::EventIn.into()).read_volatile() } } + + pub fn reset(&self, peripheral: PeriphId) { + unsafe { + // assert reset + self.csr.base().add(GlobalReg::Reset.into()).write_volatile(peripheral.into()); + // a few nops for the reset to propagate + core::arch::asm!( + "nop", "nop", "nop", "nop", "nop", "nop", "nop", "nop", "nop", "nop", "nop", "nop", "nop", + "nop", "nop", "nop", + ); + // de-assert reset + self.csr.base().add(GlobalReg::Reset.into()).write_volatile(0); + } + } } impl UdmaGlobalConfig for GlobalConfig { @@ -338,6 +354,8 @@ impl UdmaGlobalConfig for GlobalConfig { ) { self.map_event(peripheral, event_type, to_channel); } + + fn reset(&self, peripheral: PeriphId) { self.reset(peripheral); } } // --------------------------------- DMA channel ------------------------------------ pub(crate) const CFG_EN: u32 = 0b01_0000; // start a transfer diff --git a/loader/Cargo.toml b/loader/Cargo.toml index 841a421d4..a419d1fa3 100644 --- a/loader/Cargo.toml +++ b/loader/Cargo.toml @@ -127,6 +127,7 @@ reset-debug = [] usb = [] qr = ["nalgebra"] updates = [] +cramium-mpw = ["cramium-hal/mpw"] # general flags debug-print = [] diff --git a/loader/src/platform/cramium/cramium.rs b/loader/src/platform/cramium/cramium.rs index 843a9cb2e..b58f9bc0e 100644 --- a/loader/src/platform/cramium/cramium.rs +++ b/loader/src/platform/cramium/cramium.rs @@ -300,7 +300,9 @@ pub fn early_init() -> u32 { }; #[cfg(any(feature = "board-baosec", feature = "board-baosor"))] - let mut i2c = unsafe { cramium_hal::udma::I2c::new_with_ifram(i2c_channel, 400_000, perclk, i2c_ifram) }; + let mut i2c = unsafe { + cramium_hal::udma::I2c::new_with_ifram(i2c_channel, 400_000, perclk, i2c_ifram, &udma_global) + }; // setup PMIC #[cfg(any(feature = "board-baosec", feature = "board-baosor"))] { diff --git a/services/bao-video/src/main.rs b/services/bao-video/src/main.rs index e83ae2dfa..a04de63fe 100644 --- a/services/bao-video/src/main.rs +++ b/services/bao-video/src/main.rs @@ -1,7 +1,9 @@ use cramium_hal::iox::{IoxPort, IoxValue}; use cramium_hal::minigfx::*; use cramium_hal::sh1107::{Mono, Oled128x128}; -use cramium_hal::udma::{PeriphId, Udma}; +use cramium_hal::udma::PeriphId; +use num_traits::ToPrimitive; +use utralib::utra; mod gfx; mod homography; @@ -51,6 +53,32 @@ pub fn blit_to_display(sh1107: &mut Oled128x128, frame: &[u8], display_cleared: } } +#[derive(num_derive::FromPrimitive, num_derive::ToPrimitive, Debug)] +enum Opcode { + CamIrq, + InvalidCall, +} + +#[repr(align(32))] +struct CamIrq { + csr: utralib::CSR, + cid: u32, +} + +fn handle_irq(_irq_no: usize, arg: *mut usize) { + let cam_irq: &mut CamIrq = unsafe { &mut *(arg as *mut CamIrq) }; + // clear the pending interrupt - assume it's just the camera for now + let pending = cam_irq.csr.r(utra::irqarray8::EV_PENDING); + cam_irq.csr.wo(utra::irqarray8::EV_PENDING, pending); + + // activate the handler + xous::try_send_message( + cam_irq.cid, + xous::Message::new_scalar(Opcode::CamIrq.to_usize().unwrap(), pending as usize, 0, 0, 0), + ) + .ok(); +} + fn main() -> ! { let stack_size = 1 * 1024 * 1024; std::thread::Builder::new().stack_size(stack_size).spawn(wrapped_main).unwrap().join().unwrap() @@ -60,6 +88,9 @@ fn wrapped_main() -> ! { log_server::init_wait().unwrap(); log::set_max_level(log::LevelFilter::Info); + let xns = xous_names::XousNames::new().unwrap(); + let sid = xns.register_name("bao video subsystem", None).expect("can't register server"); + let tt = ticktimer::Ticktimer::new().unwrap(); let iox = cram_hal_service::IoxHal::new(); @@ -96,290 +127,359 @@ fn wrapped_main() -> ! { #[cfg(feature = "decongest-udma")] log::info!("Decongest udma option enabled."); + // register interrupt handler + let irq = xous::syscall::map_memory( + xous::MemoryAddress::new(utra::irqarray8::HW_IRQARRAY8_BASE), + None, + 4096, + xous::MemoryFlags::R | xous::MemoryFlags::W, + ) + .expect("couldn't map IRQ CSR range"); + let mut irq_csr = utralib::CSR::new(irq.as_mut_ptr() as *mut u32); + irq_csr.wo(utra::irqarray8::EV_PENDING, 0xFFFF); // clear any pending interrupts + + let cid = xous::connect(sid).unwrap(); // self-connection always succeeds + let cam_irq = CamIrq { csr: utralib::CSR::new(irq.as_mut_ptr() as *mut u32), cid }; + let irq_arg = &cam_irq as *const CamIrq as *mut usize; + log::debug!("irq_arg: {:x}", irq_arg as usize); + xous::claim_interrupt(utra::irqarray8::IRQARRAY8_IRQ, handle_irq, irq_arg).expect("couldn't claim IRQ8"); + // enable camera Rx IRQ + irq_csr.wfo(utra::irqarray8::EV_ENABLE_CAM_RX, 1); + + // kick off the first acquisition synchronous to the frame sync. With NTO/DAR-704 fix we + // could turn on the sync_sof field and skip this step. + while iox.get_gpio_pin_value(IoxPort::PB, 9) == IoxValue::High {} + cam.capture_async(); + let mut frames = 0; let mut frame = [0u8; IMAGE_WIDTH * IMAGE_HEIGHT]; let mut decode_success; - while iox.get_gpio_pin_value(IoxPort::PB, 9) == IoxValue::High {} + let mut msg_opt = None; loop { - #[cfg(not(feature = "decongest-udma"))] - cam.capture_async(); - - let mut candidates = Vec::::new(); - decode_success = false; - log::info!("------------- SEARCH {} -----------", frames); - let finder_width = qr::find_finders(&mut candidates, &frame, BW_THRESH, IMAGE_WIDTH) as isize; - if candidates.len() == 3 { - let candidates_orig = candidates.clone(); - let mut x_candidates: [Point; 3] = [Point::new(0, 0); 3]; - // apply homography to generate a new buffer for processing - let mut aligned = Vec::new(); - let mut qr_pixels: Option = None; - if let Some(mut qr_corners) = qr::QrCorners::from_finders( - &candidates.try_into().unwrap(), - Point::new(IMAGE_WIDTH as isize, IMAGE_HEIGHT as isize), - // add a search margin on the finder width - (finder_width + (qr::FINDER_SEARCH_MARGIN * finder_width) / (1 + 1 + 3 + 1 + 1)) as usize, - ) { - let dims = Point::new(IMAGE_WIDTH as isize, IMAGE_HEIGHT as isize); - let mut il = qr::ImageRoi::new(&mut frame, dims, BW_THRESH); - let (src, dst) = qr_corners.mapping(&mut il, qr::HOMOGRAPHY_MARGIN); - let mut src_f: [(f32, f32); 4] = [(0.0, 0.0); 4]; - let mut dst_f: [(f32, f32); 4] = [(0.0, 0.0); 4]; - let mut all_found = true; - for (s, s_f32) in src.iter().zip(src_f.iter_mut()) { - if let Some(p) = s { - *s_f32 = p.to_f32(); - } else { - all_found = false; - } - } - for (d, d_f32) in dst.iter().zip(dst_f.iter_mut()) { - if let Some(p) = d { - *d_f32 = p.to_f32(); - } else { - all_found = false; + xous::reply_and_receive_next(sid, &mut msg_opt).unwrap(); + let msg = msg_opt.as_mut().unwrap(); + let opcode = num_traits::FromPrimitive::from_usize(msg.body.id()).unwrap_or(Opcode::InvalidCall); + log::debug!("{:?}", opcode); + match opcode { + Opcode::CamIrq => { + #[cfg(not(feature = "decongest-udma"))] + cam.capture_async(); + + // copy the camera data to our FB + let fb: &[u32] = cam.rx_buf(); + // fb is an array of IMAGE_WIDTH x IMAGE_HEIGHT x u16 + // frame is an array of IMAGE_WIDTH x IMAGE_HEIGHT x u8 + // Take only the "Y" channel out of the fb array and write it to frame, but do it + // such that we are fetching a u32 each read from fb as this matches the native + // width of the bus (because fb is non-cacheable reading u16 ends up fetching the + // same word twice, then masking it at the CPU side in hardware). Also, the fb + // is slow to access relative to main memory. + // + // Also, commit the data to `frame` in inverse line order, e.g. flip the image + // vertically. + for (y_src, line) in fb.chunks(IMAGE_WIDTH / 2).enumerate() { + for (x_src, &u32src) in line.iter().enumerate() { + frame[(IMAGE_HEIGHT - y_src - 1) * IMAGE_WIDTH + 2 * x_src] = (u32src & 0xff) as u8; + frame[(IMAGE_HEIGHT - y_src - 1) * IMAGE_WIDTH + 2 * x_src + 1] = + ((u32src >> 16) & 0xff) as u8; } } + frames += 1; + + let mut candidates = Vec::::new(); + decode_success = false; + log::info!("------------- SEARCH {} -----------", frames); + let finder_width = qr::find_finders(&mut candidates, &frame, BW_THRESH, IMAGE_WIDTH) as isize; + if candidates.len() == 3 { + let candidates_orig = candidates.clone(); + let mut x_candidates: [Point; 3] = [Point::new(0, 0); 3]; + // apply homography to generate a new buffer for processing + let mut aligned = Vec::new(); + let mut qr_pixels: Option = None; + if let Some(mut qr_corners) = qr::QrCorners::from_finders( + &candidates.try_into().unwrap(), + Point::new(IMAGE_WIDTH as isize, IMAGE_HEIGHT as isize), + // add a search margin on the finder width + (finder_width + (qr::FINDER_SEARCH_MARGIN * finder_width) / (1 + 1 + 3 + 1 + 1)) + as usize, + ) { + let dims = Point::new(IMAGE_WIDTH as isize, IMAGE_HEIGHT as isize); + let mut il = qr::ImageRoi::new(&mut frame, dims, BW_THRESH); + let (src, dst) = qr_corners.mapping(&mut il, qr::HOMOGRAPHY_MARGIN); + let mut src_f: [(f32, f32); 4] = [(0.0, 0.0); 4]; + let mut dst_f: [(f32, f32); 4] = [(0.0, 0.0); 4]; + let mut all_found = true; + for (s, s_f32) in src.iter().zip(src_f.iter_mut()) { + if let Some(p) = s { + *s_f32 = p.to_f32(); + } else { + all_found = false; + } + } + for (d, d_f32) in dst.iter().zip(dst_f.iter_mut()) { + if let Some(p) = d { + *d_f32 = p.to_f32(); + } else { + all_found = false; + } + } - if all_found { - if let Some(h) = homography::find_homography(src_f, dst_f) { - if let Some(h_inv) = h.try_inverse() { - log::info!("{:?}", h_inv); - let h_inv_fp = homography::matrix3_to_fixp(h_inv); - log::info!("{:?}", h_inv_fp); - - aligned = vec![0u8; qr_corners.qr_pixels() * qr_corners.qr_pixels()]; - // iterate through pixels and apply homography - for y in 0..qr_corners.qr_pixels() { - for x in 0..qr_corners.qr_pixels() { - let (x_src, y_src) = - homography::apply_fixp_homography(&h_inv_fp, (x as i32, y as i32)); - if (x_src as i32 >= 0) - && ((x_src as i32) < dims.x as i32) - && (y_src as i32 >= 0) - && ((y_src as i32) < dims.y as i32) - { - // println!("{},{} -> {},{}", x_src as i32, y_src as i32, x, y); - aligned[qr_corners.qr_pixels() * y as usize + x as usize] = - frame[IMAGE_WIDTH * y_src as usize + x_src as usize]; - } else { - aligned[qr_corners.qr_pixels() * y as usize + x as usize] = 255; + if all_found { + if let Some(h) = homography::find_homography(src_f, dst_f) { + if let Some(h_inv) = h.try_inverse() { + log::info!("{:?}", h_inv); + let h_inv_fp = homography::matrix3_to_fixp(h_inv); + log::info!("{:?}", h_inv_fp); + + aligned = vec![0u8; qr_corners.qr_pixels() * qr_corners.qr_pixels()]; + // iterate through pixels and apply homography + for y in 0..qr_corners.qr_pixels() { + for x in 0..qr_corners.qr_pixels() { + let (x_src, y_src) = homography::apply_fixp_homography( + &h_inv_fp, + (x as i32, y as i32), + ); + if (x_src as i32 >= 0) + && ((x_src as i32) < dims.x as i32) + && (y_src as i32 >= 0) + && ((y_src as i32) < dims.y as i32) + { + // println!("{},{} -> {},{}", x_src as i32, y_src as i32, x, + // y); + aligned[qr_corners.qr_pixels() * y as usize + x as usize] = + frame[IMAGE_WIDTH * y_src as usize + x_src as usize]; + } else { + aligned[qr_corners.qr_pixels() * y as usize + x as usize] = + 255; + } + } } - } - } - // we can also know the location of the finders by transforming them - let h_fp = homography::matrix3_to_fixp(h); - for (i, &c) in candidates_orig.iter().enumerate() { - let (x, y) = - homography::apply_fixp_homography(&h_fp, (c.x as i32, c.y as i32)); - x_candidates[i] = Point::new(x as isize, y as isize); + // we can also know the location of the finders by transforming them + let h_fp = homography::matrix3_to_fixp(h); + for (i, &c) in candidates_orig.iter().enumerate() { + let (x, y) = homography::apply_fixp_homography( + &h_fp, + (c.x as i32, c.y as i32), + ); + x_candidates[i] = Point::new(x as isize, y as isize); + } + qr_pixels = Some(qr_corners.qr_pixels()); + } } - qr_pixels = Some(qr_corners.qr_pixels()); } } - } - } - if let Some(qr_width) = qr_pixels { - // show the transformed/aligned frame - frame.fill(255); - for (dst_line, src_line) in frame.chunks_mut(IMAGE_WIDTH).zip(aligned.chunks(qr_width)) { - // "center up" the QR in the middle by the estimated margin - // this is just a perceptual trick to prevent users from shifting the position of the - // camera - for (dst, &src) in - dst_line[qr::HOMOGRAPHY_MARGIN.abs() as usize..].iter_mut().zip(src_line.iter()) - { - *dst = src; - } - } - blit_to_display(&mut sh1107, &frame, true); + if let Some(qr_width) = qr_pixels { + // show the transformed/aligned frame + frame.fill(255); + for (dst_line, src_line) in + frame.chunks_mut(IMAGE_WIDTH).zip(aligned.chunks(qr_width)) + { + // "center up" the QR in the middle by the estimated margin + // this is just a perceptual trick to prevent users from shifting the position of + // the camera + for (dst, &src) in dst_line[qr::HOMOGRAPHY_MARGIN.abs() as usize..] + .iter_mut() + .zip(src_line.iter()) + { + *dst = src; + } + } + blit_to_display(&mut sh1107, &frame, true); - // we now have a QR code in "canonical" orientation, with a - // known width in pixels - for &x in x_candidates.iter() { - log::info!("transformed finder location {:?}", x); - } + // we now have a QR code in "canonical" orientation, with a + // known width in pixels + for &x in x_candidates.iter() { + log::info!("transformed finder location {:?}", x); + } - // Confirm that the finders coordinates are valid - let mut checked_candidates = Vec::::new(); - let x_finder_width = - qr::find_finders(&mut checked_candidates, &aligned, BW_THRESH, qr_width as _) as isize; - log::info!("x_finder width: {}", x_finder_width); - - // check that the new coordinates are within delta pixels of the original - const XFORM_DELTA: isize = 2; - let mut deltas = Vec::::new(); - for c in checked_candidates { - log::info!("x_point: {:?}", c); - for &xformed in x_candidates.iter() { - let delta = xformed - c; - log::info!("delta: {:?}", delta); - if delta.x.abs() <= XFORM_DELTA && delta.y.abs() <= XFORM_DELTA { - deltas.push(delta); + // Confirm that the finders coordinates are valid + let mut checked_candidates = Vec::::new(); + let x_finder_width = + qr::find_finders(&mut checked_candidates, &aligned, BW_THRESH, qr_width as _) + as isize; + log::info!("x_finder width: {}", x_finder_width); + + // check that the new coordinates are within delta pixels of the original + const XFORM_DELTA: isize = 2; + let mut deltas = Vec::::new(); + for c in checked_candidates { + log::info!("x_point: {:?}", c); + for &xformed in x_candidates.iter() { + let delta = xformed - c; + log::info!("delta: {:?}", delta); + if delta.x.abs() <= XFORM_DELTA && delta.y.abs() <= XFORM_DELTA { + deltas.push(delta); + } + } } - } - } - if deltas.len() == 3 { - let (version, modules) = qr::guess_code_version( - x_finder_width as usize, - (qr_width as isize + qr::HOMOGRAPHY_MARGIN * 2) as usize, - ); + if deltas.len() == 3 { + let (version, modules) = qr::guess_code_version( + x_finder_width as usize, + (qr_width as isize + qr::HOMOGRAPHY_MARGIN * 2) as usize, + ); - log::info!("image dims: {}", qr_width); - log::info!("guessed version: {}, modules: {}", version, modules); - log::info!( - "QR symbol width in pixels: {}", - qr_width - 2 * (qr::HOMOGRAPHY_MARGIN.abs() as usize) - ); + log::info!("image dims: {}", qr_width); + log::info!("guessed version: {}, modules: {}", version, modules); + log::info!( + "QR symbol width in pixels: {}", + qr_width - 2 * (qr::HOMOGRAPHY_MARGIN.abs() as usize) + ); - let qr = - qr::ImageRoi::new(&mut aligned, Point::new(qr_width as _, qr_width as _), BW_THRESH); - let grid = - modules::stream_to_grid(&qr, qr_width, modules, qr::HOMOGRAPHY_MARGIN.abs() as usize); + let qr = qr::ImageRoi::new( + &mut aligned, + Point::new(qr_width as _, qr_width as _), + BW_THRESH, + ); + let grid = modules::stream_to_grid( + &qr, + qr_width, + modules, + qr::HOMOGRAPHY_MARGIN.abs() as usize, + ); - println!("grid len {}", grid.len()); - for y in 0..modules { - for x in 0..modules { - if grid[y * modules + x] { - print!("X"); - } else { - print!(" "); + println!("grid len {}", grid.len()); + for y in 0..modules { + for x in 0..modules { + if grid[y * modules + x] { + print!("X"); + } else { + print!(" "); + } + } + println!(" {:2}", y); } - } - println!(" {:2}", y); - } - let simple = - rqrr::SimpleGrid::from_func(modules, |x, y| grid[(modules - 1) - x + y * modules]); - let grid = rqrr::Grid::new(simple); - match grid.decode() { - Ok((meta, content)) => { - log::info!("meta: {:?}", meta); - log::info!("************ {} ***********", content); - decode_success = true; + let simple = rqrr::SimpleGrid::from_func(modules, |x, y| { + grid[(modules - 1) - x + y * modules] + }); + let grid = rqrr::Grid::new(simple); + match grid.decode() { + Ok((meta, content)) => { + log::info!("meta: {:?}", meta); + log::info!("************ {} ***********", content); + decode_success = true; + gfx::msg( + &mut sh1107, + &format!("{:?}", meta), + Point::new(0, 0), + Mono::White.into(), + Mono::Black.into(), + ); + gfx::msg( + &mut sh1107, + &format!("{:?}", content), + Point::new(0, 64), + Mono::White.into(), + Mono::Black.into(), + ); + } + Err(e) => { + log::info!("{:?}", e); + gfx::msg( + &mut sh1107, + &format!("{:?}", e), + Point::new(0, 0), + Mono::White.into(), + Mono::Black.into(), + ); + } + } + } else { + log::info!("Transformed image did not survive sanity check!"); gfx::msg( &mut sh1107, - &format!("{:?}", meta), + "Hold device steady...", Point::new(0, 0), Mono::White.into(), Mono::Black.into(), ); - gfx::msg( - &mut sh1107, - &format!("{:?}", content), - Point::new(0, 64), - Mono::White.into(), - Mono::Black.into(), - ); } - Err(e) => { - log::info!("{:?}", e); - gfx::msg( - &mut sh1107, - &format!("{:?}", e), - Point::new(0, 0), - Mono::White.into(), - Mono::Black.into(), - ); + } else { + blit_to_display(&mut sh1107, &frame, true); + for c in candidates_orig.iter() { + log::debug!("****** candidate: {}, {} ******", c.x, c.y); + // remap image to screen coordinates (it's 2:1) + let c_screen = *c / 2; + // flip coordinates to match the camera data + // c_screen = Point::new(c_screen.x, sh1107.dimensions().y - 1 - c_screen.y); + qr::draw_crosshair(&mut sh1107, c_screen); } + gfx::msg( + &mut sh1107, + "Align the QR code...", + Point::new(0, 0), + Mono::White.into(), + Mono::Black.into(), + ); } } else { - log::info!("Transformed image did not survive sanity check!"); + // blit raw camera fb to sh1107 + blit_to_display(&mut sh1107, &frame, true); gfx::msg( &mut sh1107, - "Hold device steady...", + "Scan QR code...", Point::new(0, 0), Mono::White.into(), Mono::Black.into(), ); } - } else { - blit_to_display(&mut sh1107, &frame, true); - for c in candidates_orig.iter() { - log::debug!("****** candidate: {}, {} ******", c.x, c.y); - // remap image to screen coordinates (it's 2:1) - let c_screen = *c / 2; - // flip coordinates to match the camera data - // c_screen = Point::new(c_screen.x, sh1107.dimensions().y - 1 - c_screen.y); - qr::draw_crosshair(&mut sh1107, c_screen); + + // swap the double buffer and update to the display + sh1107.buffer_swap(); + sh1107.draw(); + if decode_success { + tt.sleep_ms(2000).ok(); } - gfx::msg( - &mut sh1107, - "Align the QR code...", - Point::new(0, 0), - Mono::White.into(), - Mono::Black.into(), - ); - } - } else { - // blit raw camera fb to sh1107 - blit_to_display(&mut sh1107, &frame, true); - gfx::msg( - &mut sh1107, - "Scan QR code...", - Point::new(0, 0), - Mono::White.into(), - Mono::Black.into(), - ); - } - // swap the double buffer and update to the display - sh1107.buffer_swap(); - sh1107.draw(); - if decode_success { - tt.sleep_ms(2000).ok(); - } + // clear the front buffer + sh1107.clear(); + + // re-initiate the capture. This is done at the bottom of the loop because UDMA + // congestion leads to system instability. When this problem is solved, we would + // actually want to re-initiate the capture immediately (or leave it on continuous mode) + // to allow capture to process concurrently with the code. However, there is a bug + // in the SPIM block that prevents proper usage with high bus contention that should + // be fixed in NTO. + const TIMEOUT_MS: u64 = 100; + #[cfg(feature = "decongest-udma")] + { + let start = tt.elapsed_ms(); + let mut now = tt.elapsed_ms(); + // this is required because if we initiate the capture in the middle + // of a frame, we get an offset result. This should be fixed by DAR-704 + // on NTO if the pull request is accepted; in which case, we can just rely + // on setting bit 30 of the CFG_GLOBAL register which will cause any + // RX start request to align to the beginning of a frame automatically. + while iox.get_gpio_pin_value(IoxPort::PB, 9) == IoxValue::High + && ((now - start) < TIMEOUT_MS) + { + now = tt.elapsed_ms(); + } + if now - start >= TIMEOUT_MS { + log::info!("Timeout before capture_async()!"); + } + cam.capture_async(); + } - // clear the front buffer - sh1107.clear(); - - const TIMEOUT_MS: u64 = 100; - #[cfg(feature = "decongest-udma")] - { - let start = tt.elapsed_ms(); - let mut now = tt.elapsed_ms(); - // don't parallelize the camera capture to avoid triggering a hardware bug - // in the SPIM block. - while iox.get_gpio_pin_value(IoxPort::PB, 9) == IoxValue::High && ((now - start) < TIMEOUT_MS) { - now = tt.elapsed_ms(); - } - if now - start >= TIMEOUT_MS { - log::info!("Timeout before capture_async()!"); + // this is no longer the case because we're relying on interrupts to wake us up. + /* + // wait for the transfer to finish + let start = tt.elapsed_ms(); + let mut now = tt.elapsed_ms(); + use cramium_hal::udma::Udma; + while cam.udma_busy(cramium_hal::udma::Bank::Rx) && ((now - start) < TIMEOUT_MS) { + now = tt.elapsed_ms(); + // busy-wait to get better time resolution on when the frame ends + } + if now - start >= TIMEOUT_MS { + log::info!("Timeout before rx_buf()!"); + } + */ } - cam.capture_async(); - } - - // wait for the transfer to finish - let start = tt.elapsed_ms(); - let mut now = tt.elapsed_ms(); - while cam.udma_busy(cramium_hal::udma::Bank::Rx) && ((now - start) < TIMEOUT_MS) { - now = tt.elapsed_ms(); - // busy-wait to get better time resolution on when the frame ends - } - if now - start >= TIMEOUT_MS { - log::info!("Timeout before rx_buf()!"); - } - let fb: &[u32] = cam.rx_buf(); - - // fb is an array of IMAGE_WIDTH x IMAGE_HEIGHT x u16 - // frame is an array of IMAGE_WIDTH x IMAGE_HEIGHT x u8 - // Take only the "Y" channel out of the fb array and write it to frame, but do it - // such that we are fetching a u32 each read from fb as this matches the native - // width of the bus (because fb is non-cacheable reading u16 ends up fetching the - // same word twice, then masking it at the CPU side in hardware). Also, the fb - // is slow to access relative to main memory. - // - // Also, commit the data to `frame` in inverse line order, e.g. flip the image - // vertically. - for (y_src, line) in fb.chunks(IMAGE_WIDTH / 2).enumerate() { - for (x_src, &u32src) in line.iter().enumerate() { - frame[(IMAGE_HEIGHT - y_src - 1) * IMAGE_WIDTH + 2 * x_src] = (u32src & 0xff) as u8; - frame[(IMAGE_HEIGHT - y_src - 1) * IMAGE_WIDTH + 2 * x_src + 1] = - ((u32src >> 16) & 0xff) as u8; + Opcode::InvalidCall => { + log::error!("Invalid call to bao video server: {:?}", msg); } } - - frames += 1; } } diff --git a/services/cram-hal-service/Cargo.toml b/services/cram-hal-service/Cargo.toml index 2ec8d1bd8..e263336bf 100644 --- a/services/cram-hal-service/Cargo.toml +++ b/services/cram-hal-service/Cargo.toml @@ -42,6 +42,7 @@ pio-memlcd = [] rawserial = [] pinger = [] swap = [] +mpw = ["cramium-hal/mpw"] # add this feature to enable pre-emption quantum-timer = ["utralib", "pio"] default = ["app-uart"] diff --git a/services/cram-hal-service/src/api.rs b/services/cram-hal-service/src/api.rs index 6573037ed..0db7e6785 100644 --- a/services/cram-hal-service/src/api.rs +++ b/services/cram-hal-service/src/api.rs @@ -44,6 +44,9 @@ pub enum Opcode { /// I2C operations I2c = 9, + /// Peripheral reset + PeriphReset = 10, + /// Exit server Quit = 255, diff --git a/services/cram-hal-service/src/lib.rs b/services/cram-hal-service/src/lib.rs index 4f78f8771..814d1f2a4 100644 --- a/services/cram-hal-service/src/lib.rs +++ b/services/cram-hal-service/src/lib.rs @@ -66,6 +66,20 @@ impl UdmaGlobal { ) .expect("Couldn't setup UDMA event mapping"); } + + pub fn reset(&self, peripheral: PeriphId) { + xous::send_message( + self.conn, + xous::Message::new_blocking_scalar( + Opcode::PeriphReset.to_usize().unwrap(), + peripheral as u32 as usize, + 0, + 0, + 0, + ), + ) + .expect("Couldn't setup UDMA clock"); + } } impl UdmaGlobalConfig for UdmaGlobal { @@ -79,4 +93,6 @@ impl UdmaGlobalConfig for UdmaGlobal { ) { self.udma_event_map(peripheral, event_type, to_channel); } + + fn reset(&self, peripheral: PeriphId) { self.reset(peripheral); } } diff --git a/services/cram-hal-service/src/main.rs b/services/cram-hal-service/src/main.rs index dbb83acc0..ae93b4338 100644 --- a/services/cram-hal-service/src/main.rs +++ b/services/cram-hal-service/src/main.rs @@ -166,7 +166,13 @@ fn main() { ) }; let mut i2c = unsafe { - cramium_hal::udma::I2c::new_with_ifram(i2c_channel, 400_000, cram_hal_service::PERCLK, i2c_ifram) + cramium_hal::udma::I2c::new_with_ifram( + i2c_channel, + 400_000, + cram_hal_service::PERCLK, + i2c_ifram, + &udma_global, + ) }; // -------------------- begin timer workaround code @@ -371,6 +377,12 @@ fn main() { udma_global.map_event_with_offset(periph, event_offset, to_channel); } } + Opcode::PeriphReset => { + if let Some(scalar) = msg.body.scalar_message() { + let periph: PeriphId = num_traits::FromPrimitive::from_usize(scalar.arg1).unwrap(); + udma_global.reset(periph); + } + } Opcode::I2c => { let mut buf = unsafe { xous_ipc::Buffer::from_memory_message_mut(msg.body.memory_message_mut().unwrap()) diff --git a/utralib/cramium/daric.svd b/utralib/cramium/daric.svd index 39c77f127..8685b3c7f 100644 --- a/utralib/cramium/daric.svd +++ b/utralib/cramium/daric.svd @@ -2104,18 +2104,18 @@ position to clear the flag]]> - SFR_AHBS + SFR_APBS 0x0008 0x00 32 - cr_ahbsopt + cr_apbsopt 4 [4:0] 0 - + @@ -6974,411 +6974,2236 @@ position to clear the flag]]> - CORESUB_SRAMTRM - 0x40014000 - CORESUB_SRAMTRM + SDDC + 0x50121000 + SDDC - SFR_CACHE - + SFR_IO + 0x0000 0x00 32 - sfr_cache - 2 - [2:0] + sfr_io + 1 + [1:0] 0 - + - SFR_ITCM - + SFR_AR + 0x0004 0x00 32 - sfr_itcm - 4 - [4:0] + sfr_ar + 31 + [31:0] 0 - + - SFR_DTCM - - 0x0008 + CR_OCR + + 0x0010 0x00 32 - sfr_dtcm - 4 - [4:0] + cr_ocr + 23 + [23:0] 0 - + - SFR_SRAM0 - - 0x000c + CR_RDFFTHRES + + 0x0014 0x00 32 - sfr_sram0 - 4 - [4:0] + cr_rdffthres + 7 + [7:0] 0 - + - SFR_SRAM1 - - 0x0010 + CR_REV + + 0x0018 0x00 32 - sfr_sram1 - 4 - [4:0] + cfg_reg_sd_spec_revision + 7 + [7:0] 0 - + + + + cfg_reg_cccr_sdio_revision + 15 + [15:8] + 8 + - SFR_VEXRAM - - 0x0014 + CR_BACSA + + 0x001c 0x00 32 - sfr_vexram - 2 - [2:0] + cfg_base_addr_csa + 17 + [17:0] 0 - + - SFR_SRAMERR - + CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0 + 0x0020 0x00 32 - srambankerr - 3 - [3:0] + cfg_base_addr_io_func0 + 17 + [17:0] 0 - + - - - 0 - 0x24 - registers - - - - MDMA - 0x40012000 - MDMA - - SFR_EVSEL_CR_EVSEL0 - - 0x0000 + CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1 + + 0x0024 0x00 32 - cr_evsel0 - 7 - [7:0] + cfg_base_addr_io_func1 + 17 + [17:0] 0 - + - SFR_EVSEL_CR_EVSEL1 - - 0x0004 + CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2 + + 0x0028 0x00 32 - cr_evsel1 - 7 - [7:0] + cfg_base_addr_io_func2 + 17 + [17:0] 0 - + - SFR_EVSEL_CR_EVSEL2 - - 0x0008 + CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3 + + 0x002c 0x00 32 - cr_evsel2 - 7 - [7:0] + cfg_base_addr_io_func3 + 17 + [17:0] 0 - + - SFR_EVSEL_CR_EVSEL3 - - 0x000c + CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4 + + 0x0030 0x00 32 - cr_evsel3 - 7 - [7:0] + cfg_base_addr_io_func4 + 17 + [17:0] 0 - + - SFR_EVSEL_CR_EVSEL4 - - 0x0010 + CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5 + + 0x0034 0x00 32 - cr_evsel4 - 7 - [7:0] + cfg_base_addr_io_func5 + 17 + [17:0] 0 - + - SFR_EVSEL_CR_EVSEL5 - - 0x0014 + CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6 + + 0x0038 0x00 32 - cr_evsel5 - 7 - [7:0] + cfg_base_addr_io_func6 + 17 + [17:0] 0 - + - SFR_EVSEL_CR_EVSEL6 - - 0x0018 + CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7 + + 0x003c 0x00 32 - cr_evsel6 - 7 - [7:0] + cfg_base_addr_io_func7 + 17 + [17:0] 0 - + - SFR_EVSEL_CR_EVSEL7 - - 0x001c + CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0 + + 0x0040 0x00 32 - cr_evsel7 - 7 - [7:0] + cfg_reg_func_cis_ptr0 + 16 + [16:0] 0 - + - SFR_CR_CR_MDMAREQ0 - - 0x0020 + CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1 + + 0x0044 0x00 32 - cr_mdmareq0 - 4 - [4:0] + cfg_reg_func_cis_ptr1 + 16 + [16:0] 0 - + - SFR_CR_CR_MDMAREQ1 - - 0x0024 + CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2 + + 0x0048 0x00 32 - cr_mdmareq1 - 4 - [4:0] + cfg_reg_func_cis_ptr2 + 16 + [16:0] 0 - + - SFR_CR_CR_MDMAREQ2 - - 0x0028 + CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3 + + 0x004c 0x00 32 - cr_mdmareq2 - 4 - [4:0] + cfg_reg_func_cis_ptr3 + 16 + [16:0] 0 - + - SFR_CR_CR_MDMAREQ3 - - 0x002c + CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4 + + 0x0050 0x00 32 - cr_mdmareq3 - 4 - [4:0] + cfg_reg_func_cis_ptr4 + 16 + [16:0] 0 - + - SFR_CR_CR_MDMAREQ4 - - 0x0030 + CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5 + + 0x0054 0x00 32 - cr_mdmareq4 - 4 - [4:0] + cfg_reg_func_cis_ptr5 + 16 + [16:0] 0 - + - SFR_CR_CR_MDMAREQ5 - - 0x0034 + CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6 + + 0x0058 0x00 32 - cr_mdmareq5 - 4 - [4:0] + cfg_reg_func_cis_ptr6 + 16 + [16:0] 0 - + - SFR_CR_CR_MDMAREQ6 - - 0x0038 + CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7 + + 0x005c 0x00 32 - cr_mdmareq6 - 4 - [4:0] + cfg_reg_func_cis_ptr7 + 16 + [16:0] 0 - + - SFR_CR_CR_MDMAREQ7 - - 0x003c + CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0 + + 0x0060 0x00 32 - cr_mdmareq7 - 4 - [4:0] + cfg_reg_func_ext_std_code0 + 7 + [7:0] 0 - + - SFR_SR_SR_MDMAREQ0 - - 0x0040 + CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1 + + 0x0064 0x00 32 - sr_mdmareq0 - 4 - [4:0] + cfg_reg_func_ext_std_code1 + 7 + [7:0] 0 - + - SFR_SR_SR_MDMAREQ1 - - 0x0044 + CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2 + + 0x0068 + 0x00 + 32 + + + cfg_reg_func_ext_std_code2 + 7 + [7:0] + 0 + + + + + + CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3 + + 0x006c + 0x00 + 32 + + + cfg_reg_func_ext_std_code3 + 7 + [7:0] + 0 + + + + + + CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4 + + 0x0070 + 0x00 + 32 + + + cfg_reg_func_ext_std_code4 + 7 + [7:0] + 0 + + + + + + CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5 + + 0x0074 + 0x00 + 32 + + + cfg_reg_func_ext_std_code5 + 7 + [7:0] + 0 + + + + + + CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6 + + 0x0078 + 0x00 + 32 + + + cfg_reg_func_ext_std_code6 + 7 + [7:0] + 0 + + + + + + CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7 + + 0x007c + 0x00 + 32 + + + cfg_reg_func_ext_std_code7 + 7 + [7:0] + 0 + + + + + + CR_WRITE_PROTECT + + 0x0080 + 0x00 + 32 + + + cr_write_protect + 0 + [0:0] + 0 + + + + + + CR_REG_DSR + + 0x0084 + 0x00 + 32 + + + cr_reg_dsr + 15 + [15:0] + 0 + + + + + + CR_REG_CID_CFG_REG_CID0 + + 0x0088 + 0x00 + 32 + + + cfg_reg_cid0 + 31 + [31:0] + 0 + + + + + + CR_REG_CID_CFG_REG_CID1 + + 0x008c + 0x00 + 32 + + + cfg_reg_cid1 + 31 + [31:0] + 0 + + + + + + CR_REG_CID_CFG_REG_CID2 + + 0x0090 + 0x00 + 32 + + + cfg_reg_cid2 + 31 + [31:0] + 0 + + + + + + CR_REG_CID_CFG_REG_CID3 + + 0x0094 + 0x00 + 32 + + + cfg_reg_cid3 + 31 + [31:0] + 0 + + + + + + CR_REG_CSD_CFG_REG_CSD0 + + 0x0098 + 0x00 + 32 + + + cfg_reg_csd0 + 31 + [31:0] + 0 + + + + + + CR_REG_CSD_CFG_REG_CSD1 + + 0x009c + 0x00 + 32 + + + cfg_reg_csd1 + 31 + [31:0] + 0 + + + + + + CR_REG_CSD_CFG_REG_CSD2 + + 0x00a0 + 0x00 + 32 + + + cfg_reg_csd2 + 31 + [31:0] + 0 + + + + + + CR_REG_CSD_CFG_REG_CSD3 + + 0x00a4 + 0x00 + 32 + + + cfg_reg_csd3 + 31 + [31:0] + 0 + + + + + + CR_REG_SCR_CFG_REG_SCR0 + + 0x00a8 + 0x00 + 32 + + + cfg_reg_scr0 + 31 + [31:0] + 0 + + + + + + CR_REG_SCR_CFG_REG_SCR1 + + 0x00ac + 0x00 + 32 + + + cfg_reg_scr1 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS0 + + 0x00b0 + 0x00 + 32 + + + cfg_reg_sd_status0 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS1 + + 0x00b4 + 0x00 + 32 + + + cfg_reg_sd_status1 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS2 + + 0x00b8 + 0x00 + 32 + + + cfg_reg_sd_status2 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS3 + + 0x00bc + 0x00 + 32 + + + cfg_reg_sd_status3 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS4 + + 0x00c0 + 0x00 + 32 + + + cfg_reg_sd_status4 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS5 + + 0x00c4 + 0x00 + 32 + + + cfg_reg_sd_status5 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS6 + + 0x00c8 + 0x00 + 32 + + + cfg_reg_sd_status6 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS7 + + 0x00cc + 0x00 + 32 + + + cfg_reg_sd_status7 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS8 + + 0x00d0 + 0x00 + 32 + + + cfg_reg_sd_status8 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS9 + + 0x00d4 + 0x00 + 32 + + + cfg_reg_sd_status9 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS10 + + 0x00d8 + 0x00 + 32 + + + cfg_reg_sd_status10 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS11 + + 0x00dc + 0x00 + 32 + + + cfg_reg_sd_status11 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS12 + + 0x00e0 + 0x00 + 32 + + + cfg_reg_sd_status12 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS13 + + 0x00e4 + 0x00 + 32 + + + cfg_reg_sd_status13 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS14 + + 0x00e8 + 0x00 + 32 + + + cfg_reg_sd_status14 + 31 + [31:0] + 0 + + + + + + CR_REG_SD_STATUS_CFG_REG_SD_STATUS15 + + 0x00ec + 0x00 + 32 + + + cfg_reg_sd_status15 + 31 + [31:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0 + + 0x0100 + 0x00 + 32 + + + cfg_base_addr_mem_func0 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1 + + 0x0104 + 0x00 + 32 + + + cfg_base_addr_mem_func1 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2 + + 0x0108 + 0x00 + 32 + + + cfg_base_addr_mem_func2 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3 + + 0x010c + 0x00 + 32 + + + cfg_base_addr_mem_func3 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4 + + 0x0110 + 0x00 + 32 + + + cfg_base_addr_mem_func4 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5 + + 0x0114 + 0x00 + 32 + + + cfg_base_addr_mem_func5 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6 + + 0x0118 + 0x00 + 32 + + + cfg_base_addr_mem_func6 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7 + + 0x011c + 0x00 + 32 + + + cfg_base_addr_mem_func7 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8 + + 0x0120 + 0x00 + 32 + + + cfg_base_addr_mem_func8 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9 + + 0x0124 + 0x00 + 32 + + + cfg_base_addr_mem_func9 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10 + + 0x0128 + 0x00 + 32 + + + cfg_base_addr_mem_func10 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11 + + 0x012c + 0x00 + 32 + + + cfg_base_addr_mem_func11 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12 + + 0x0130 + 0x00 + 32 + + + cfg_base_addr_mem_func12 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13 + + 0x0134 + 0x00 + 32 + + + cfg_base_addr_mem_func13 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14 + + 0x0138 + 0x00 + 32 + + + cfg_base_addr_mem_func14 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15 + + 0x013c + 0x00 + 32 + + + cfg_base_addr_mem_func15 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16 + + 0x0140 + 0x00 + 32 + + + cfg_base_addr_mem_func16 + 17 + [17:0] + 0 + + + + + + CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17 + + 0x0144 + 0x00 + 32 + + + cfg_base_addr_mem_func17 + 17 + [17:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0 + + 0x0148 + 0x00 + 32 + + + cfg_reg_func_isdio_interface_code0 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1 + + 0x014c + 0x00 + 32 + + + cfg_reg_func_isdio_interface_code1 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2 + + 0x0150 + 0x00 + 32 + + + cfg_reg_func_isdio_interface_code2 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3 + + 0x0154 + 0x00 + 32 + + + cfg_reg_func_isdio_interface_code3 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4 + + 0x0158 + 0x00 + 32 + + + cfg_reg_func_isdio_interface_code4 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5 + + 0x015c + 0x00 + 32 + + + cfg_reg_func_isdio_interface_code5 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6 + + 0x0160 + 0x00 + 32 + + + cfg_reg_func_isdio_interface_code6 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0 + + 0x0168 + 0x00 + 32 + + + cfg_reg_func_manufact_code0 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1 + + 0x016c + 0x00 + 32 + + + cfg_reg_func_manufact_code1 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2 + + 0x0170 + 0x00 + 32 + + + cfg_reg_func_manufact_code2 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3 + + 0x0174 + 0x00 + 32 + + + cfg_reg_func_manufact_code3 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4 + + 0x0178 + 0x00 + 32 + + + cfg_reg_func_manufact_code4 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5 + + 0x017c + 0x00 + 32 + + + cfg_reg_func_manufact_code5 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6 + + 0x0180 + 0x00 + 32 + + + cfg_reg_func_manufact_code6 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0 + + 0x0188 + 0x00 + 32 + + + cfg_reg_func_manufact_info0 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1 + + 0x018c + 0x00 + 32 + + + cfg_reg_func_manufact_info1 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2 + + 0x0190 + 0x00 + 32 + + + cfg_reg_func_manufact_info2 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3 + + 0x0194 + 0x00 + 32 + + + cfg_reg_func_manufact_info3 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4 + + 0x0198 + 0x00 + 32 + + + cfg_reg_func_manufact_info4 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5 + + 0x019c + 0x00 + 32 + + + cfg_reg_func_manufact_info5 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6 + + 0x01a0 + 0x00 + 32 + + + cfg_reg_func_manufact_info6 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0 + + 0x01a8 + 0x00 + 32 + + + cfg_reg_func_isdio_type_sup_code0 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1 + + 0x01ac + 0x00 + 32 + + + cfg_reg_func_isdio_type_sup_code1 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2 + + 0x01b0 + 0x00 + 32 + + + cfg_reg_func_isdio_type_sup_code2 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3 + + 0x01b4 + 0x00 + 32 + + + cfg_reg_func_isdio_type_sup_code3 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4 + + 0x01b8 + 0x00 + 32 + + + cfg_reg_func_isdio_type_sup_code4 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5 + + 0x01bc + 0x00 + 32 + + + cfg_reg_func_isdio_type_sup_code5 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6 + + 0x01c0 + 0x00 + 32 + + + cfg_reg_func_isdio_type_sup_code6 + 7 + [7:0] + 0 + + + + + + CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0 + + 0x01c8 + 0x00 + 32 + + + cfg_reg_func_info0 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1 + + 0x01cc + 0x00 + 32 + + + cfg_reg_func_info1 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2 + + 0x01d0 + 0x00 + 32 + + + cfg_reg_func_info2 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3 + + 0x01d4 + 0x00 + 32 + + + cfg_reg_func_info3 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4 + + 0x01d8 + 0x00 + 32 + + + cfg_reg_func_info4 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5 + + 0x01dc + 0x00 + 32 + + + cfg_reg_func_info5 + 15 + [15:0] + 0 + + + + + + CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6 + + 0x01e0 + 0x00 + 32 + + + cfg_reg_func_info6 + 15 + [15:0] + 0 + + + + + + CR_REG_UHS_1_SUPPORT + + 0x01f0 + 0x00 + 32 + + + cfg_reg_max_current + 15 + [15:0] + 0 + + + + cfg_reg_data_strc_version + 23 + [23:16] + 16 + + + + cfg_reg_uhs_1_support + 31 + [31:24] + 24 + + + + + + + 0 + 0x1f4 + registers + + + + CORESUB_SRAMTRM + 0x40014000 + CORESUB_SRAMTRM + + + SFR_CACHE + + 0x0000 + 0x00 + 32 + + + sfr_cache + 2 + [2:0] + 0 + + + + + + SFR_ITCM + + 0x0004 + 0x00 + 32 + + + sfr_itcm + 4 + [4:0] + 0 + + + + + + SFR_DTCM + + 0x0008 + 0x00 + 32 + + + sfr_dtcm + 4 + [4:0] + 0 + + + + + + SFR_SRAM0 + + 0x000c + 0x00 + 32 + + + sfr_sram0 + 4 + [4:0] + 0 + + + + + + SFR_SRAM1 + + 0x0010 + 0x00 + 32 + + + sfr_sram1 + 4 + [4:0] + 0 + + + + + + SFR_VEXRAM + + 0x0014 + 0x00 + 32 + + + sfr_vexram + 2 + [2:0] + 0 + + + + + + SFR_SRAMERR + + 0x0020 + 0x00 + 32 + + + srambankerr + 3 + [3:0] + 0 + + + + + + + 0 + 0x24 + registers + + + + MDMA + 0x40012000 + MDMA + + + SFR_EVSEL_CR_EVSEL0 + + 0x0000 + 0x00 + 32 + + + cr_evsel0 + 7 + [7:0] + 0 + + + + + + SFR_EVSEL_CR_EVSEL1 + + 0x0004 + 0x00 + 32 + + + cr_evsel1 + 7 + [7:0] + 0 + + + + + + SFR_EVSEL_CR_EVSEL2 + + 0x0008 + 0x00 + 32 + + + cr_evsel2 + 7 + [7:0] + 0 + + + + + + SFR_EVSEL_CR_EVSEL3 + + 0x000c + 0x00 + 32 + + + cr_evsel3 + 7 + [7:0] + 0 + + + + + + SFR_EVSEL_CR_EVSEL4 + + 0x0010 + 0x00 + 32 + + + cr_evsel4 + 7 + [7:0] + 0 + + + + + + SFR_EVSEL_CR_EVSEL5 + + 0x0014 + 0x00 + 32 + + + cr_evsel5 + 7 + [7:0] + 0 + + + + + + SFR_EVSEL_CR_EVSEL6 + + 0x0018 + 0x00 + 32 + + + cr_evsel6 + 7 + [7:0] + 0 + + + + + + SFR_EVSEL_CR_EVSEL7 + + 0x001c + 0x00 + 32 + + + cr_evsel7 + 7 + [7:0] + 0 + + + + + + SFR_CR_CR_MDMAREQ0 + + 0x0020 + 0x00 + 32 + + + cr_mdmareq0 + 4 + [4:0] + 0 + + + + + + SFR_CR_CR_MDMAREQ1 + + 0x0024 + 0x00 + 32 + + + cr_mdmareq1 + 4 + [4:0] + 0 + + + + + + SFR_CR_CR_MDMAREQ2 + + 0x0028 + 0x00 + 32 + + + cr_mdmareq2 + 4 + [4:0] + 0 + + + + + + SFR_CR_CR_MDMAREQ3 + + 0x002c + 0x00 + 32 + + + cr_mdmareq3 + 4 + [4:0] + 0 + + + + + + SFR_CR_CR_MDMAREQ4 + + 0x0030 + 0x00 + 32 + + + cr_mdmareq4 + 4 + [4:0] + 0 + + + + + + SFR_CR_CR_MDMAREQ5 + + 0x0034 + 0x00 + 32 + + + cr_mdmareq5 + 4 + [4:0] + 0 + + + + + + SFR_CR_CR_MDMAREQ6 + + 0x0038 + 0x00 + 32 + + + cr_mdmareq6 + 4 + [4:0] + 0 + + + + + + SFR_CR_CR_MDMAREQ7 + + 0x003c + 0x00 + 32 + + + cr_mdmareq7 + 4 + [4:0] + 0 + + + + + + SFR_SR_SR_MDMAREQ0 + + 0x0040 + 0x00 + 32 + + + sr_mdmareq0 + 4 + [4:0] + 0 + + + + + + SFR_SR_SR_MDMAREQ1 + + 0x0044 0x00 32 @@ -7387,549 +9212,1921 @@ respective bit position to clear the flag]]> 4 [4:0] 0 - + + + + + + SFR_SR_SR_MDMAREQ2 + + 0x0048 + 0x00 + 32 + + + sr_mdmareq2 + 4 + [4:0] + 0 + + + + + + SFR_SR_SR_MDMAREQ3 + + 0x004c + 0x00 + 32 + + + sr_mdmareq3 + 4 + [4:0] + 0 + + + + + + SFR_SR_SR_MDMAREQ4 + + 0x0050 + 0x00 + 32 + + + sr_mdmareq4 + 4 + [4:0] + 0 + + + + + + SFR_SR_SR_MDMAREQ5 + + 0x0054 + 0x00 + 32 + + + sr_mdmareq5 + 4 + [4:0] + 0 + + + + + + SFR_SR_SR_MDMAREQ6 + + 0x0058 + 0x00 + 32 + + + sr_mdmareq6 + 4 + [4:0] + 0 + + + + + + SFR_SR_SR_MDMAREQ7 + + 0x005c + 0x00 + 32 + + + sr_mdmareq7 + 4 + [4:0] + 0 + + + + + + + 0 + 0x60 + registers + + + + QFC + 0x40010000 + QFC + + + SFR_IO + + 0x0000 + 0x00 + 32 + + + sfr_io + 7 + [7:0] + 0 + + + + + + SFR_AR + + 0x0004 + 0x00 + 32 + + + sfr_ar + 31 + [31:0] + 0 + + + + + + SFR_IODRV + + 0x0008 + 0x00 + 32 + + + paddrvsel + 11 + [11:0] + 0 + + + + + + CR_XIP_ADDRMODE + + 0x0010 + 0x00 + 32 + + + cr_xip_addrmode + 1 + [1:0] + 0 + + + + + + CR_XIP_OPCODE + + 0x0014 + 0x00 + 32 + + + cr_xip_opcode + 31 + [31:0] + 0 + + + + + + CR_XIP_WIDTH + + 0x0018 + 0x00 + 32 + + + cr_xip_width + 5 + [5:0] + 0 + + + + + + CR_XIP_SSEL + + 0x001c + 0x00 + 32 + + + cr_xip_ssel + 6 + [6:0] + 0 + + + + + + CR_XIP_DUMCYC + + 0x0020 + 0x00 + 32 + + + cr_xip_dumcyc + 15 + [15:0] + 0 + + + + + + CR_XIP_CFG + + 0x0024 + 0x00 + 32 + + + cr_xip_cfg + 14 + [14:0] + 0 + + + + + + CR_AESKEY_AESKEYIN0 + + 0x0040 + 0x00 + 32 + + + aeskeyin0 + 31 + [31:0] + 0 + + + + + + CR_AESKEY_AESKEYIN1 + + 0x0044 + 0x00 + 32 + + + aeskeyin1 + 31 + [31:0] + 0 + + + + + + CR_AESKEY_AESKEYIN2 + + 0x0048 + 0x00 + 32 + + + aeskeyin2 + 31 + [31:0] + 0 + + + + + + CR_AESKEY_AESKEYIN3 + + 0x004c + 0x00 + 32 + + + aeskeyin3 + 31 + [31:0] + 0 + + + + + + CR_AESENA + + 0x0050 + 0x00 + 32 + + + cr_aesena + 0 + [0:0] + 0 + + + + + + + 0 + 0x54 + registers + + + + MBOX_APB + 0x40013000 + MBOX_APB + + + SFR_WDATA + + 0x0000 + 0x00 + 32 + + + sfr_wdata + 31 + [31:0] + 0 + + + + + + SFR_RDATA + + 0x0004 + 0x00 + 32 + + + sfr_rdata + 31 + [31:0] + 0 + + + + + + SFR_STATUS + + 0x0008 + 0x00 + 32 + + + rx_avail + 0 + [0:0] + 0 + + + + tx_free + 1 + [1:1] + 1 + + + + abort_in_progress + 2 + [2:2] + 2 + + + + abort_ack + 3 + [3:3] + 3 + + + + tx_err + 4 + [4:4] + 4 + + + + rx_err + 5 + [5:5] + 5 + + + + + + SFR_ABORT + + 0x0018 + 0x00 + 32 + + + sfr_abort + 31 + [31:0] + 0 + + + + + + SFR_DONE + + 0x001c + 0x00 + 32 + + + sfr_done + 31 + [31:0] + 0 + + + + + + + 0 + 0x20 + registers + + + + RRC + 0x40000000 + RRC + + + SFR_RRCCR + + 0x0000 + 0x00 + 32 + + + sfr_rrccr + 1 + [1:0] + 0 + + + + + + SFR_RRCFD + + 0x0004 + 0x00 + 32 + + + sfr_rrcfd + 4 + [4:0] + 0 + + + + + + SFR_RRCSR + + 0x0008 + 0x00 + 32 + + + sfr_rrcsr + 9 + [9:0] + 0 + + + + + + SFR_RRCFR + + 0x000c + 0x00 + 32 + + + sfr_rrcfr + 3 + [3:0] + 0 + + + + + + SFR_RRCAR + + 0x0010 + 0x00 + 32 + + + sfr_rrcar + 31 + [31:0] + 0 + + + + + + SFR_RRCSR_SET0 + + 0x0014 + 0x00 + 32 + + + trc_set_failure + 31 + [31:0] + 0 + + + + + + SFR_RRCSR_SET1 + + 0x0018 + 0x00 + 32 + + + trc_set_failure + 31 + [31:0] + 0 + + + + + + SFR_RRCSR_RST0 + + 0x001c + 0x00 + 32 + + + trc_reset_failure + 31 + [31:0] + 0 + + + + + + SFR_RRCSR_RST1 + + 0x0020 + 0x00 + 32 + + + trc_reset_failure + 31 + [31:0] + 0 + + + + + + SFR_RRCSR_RD0 + + 0x0024 + 0x00 + 32 + + + trc_fourth_read_failure + 31 + [31:0] + 0 + + + + + + SFR_RRCSR_RD1 + + 0x0028 + 0x00 + 32 + + + trc_fourth_read_failure + 31 + [31:0] + 0 + + + + + + + 0 + 0x2c + registers + + + + GLUECHAIN + 0x40054000 + GLUECHAIN + + + SFR_GCMASK + + 0x0000 + 0x00 + 32 + + + cr_gcmask + 31 + [31:0] + 0 + + + + + + SFR_GCSR + + 0x0004 + 0x00 + 32 + + + gluereg + 31 + [31:0] + 0 + + + + + + SFR_GCRST + + 0x0008 + 0x00 + 32 + + + gluerst + 31 + [31:0] + 0 + + + + + + SFR_GCTEST + + 0x000c + 0x00 + 32 + + + gluetest + 31 + [31:0] + 0 + + + + + + + 0 + 0x10 + registers + + + + MESH + 0x40052000 + MESH + + + SFR_MLDRV_CR_MLDRV0 + + 0x0000 + 0x00 + 32 + + + cr_mldrv0 + 31 + [31:0] + 0 + + + + + + SFR_MLIE_CR_MLIE0 + + 0x0004 + 0x00 + 32 + + + cr_mlie0 + 31 + [31:0] + 0 + + + + + + SFR_MLSR_SR_MLSR0 + + 0x0008 + 0x00 + 32 + + + sr_mlsr0 + 31 + [31:0] + 0 + + + + + + SFR_MLSR_SR_MLSR1 + + 0x000c + 0x00 + 32 + + + sr_mlsr1 + 31 + [31:0] + 0 + + + + + + SFR_MLSR_SR_MLSR2 + + 0x0010 + 0x00 + 32 + + + sr_mlsr2 + 31 + [31:0] + 0 + + + + + + SFR_MLSR_SR_MLSR3 + + 0x0014 + 0x00 + 32 + + + sr_mlsr3 + 31 + [31:0] + 0 + + + + + + SFR_MLSR_SR_MLSR4 + + 0x0018 + 0x00 + 32 + + + sr_mlsr4 + 31 + [31:0] + 0 + + + + + + SFR_MLSR_SR_MLSR5 + + 0x001c + 0x00 + 32 + + + sr_mlsr5 + 31 + [31:0] + 0 + + + + + + SFR_MLSR_SR_MLSR6 + + 0x0020 + 0x00 + 32 + + + sr_mlsr6 + 31 + [31:0] + 0 + + + + + + SFR_MLSR_SR_MLSR7 + + 0x0024 + 0x00 + 32 + + + sr_mlsr7 + 31 + [31:0] + 0 + + + + + + + 0 + 0x28 + registers + + + + SENSORC + 0x40053000 + SENSORC + + + SFR_VDMASK0 + + 0x0000 + 0x00 + 32 + + + cr_vdmask0 + 7 + [7:0] + 0 + + + + + + SFR_VDMASK1 + + 0x0004 + 0x00 + 32 + + + cr_vdmask1 + 7 + [7:0] + 0 + + + + + + SFR_VDSR + + 0x0008 + 0x00 + 32 + + + vdflag + 7 + [7:0] + 0 + + + + + + SFR_VDFR + + 0x000c + 0x00 + 32 + + + vdflag + 7 + [7:0] + 0 + + + + + + SFR_LDMASK + + 0x0010 + 0x00 + 32 + + + cr_ldmask + 3 + [3:0] + 0 + + + + + + SFR_LDSR + + 0x0014 + 0x00 + 32 + + + sr_ldsr + 3 + [3:0] + 0 + + + + + + SFR_LDCFG + + 0x0018 + 0x00 + 32 + + + sfr_ldcfg + 3 + [3:0] + 0 + + + + + + SFR_VDCFG_CR_VDCFG0 + + 0x0020 + 0x00 + 32 + + + cr_vdcfg0 + 3 + [3:0] + 0 + - SFR_SR_SR_MDMAREQ2 - + SFR_VDCFG_CR_VDCFG1 + + 0x0024 + 0x00 + 32 + + + cr_vdcfg1 + 3 + [3:0] + 0 + + + + + + SFR_VDCFG_CR_VDCFG2 + + 0x0028 + 0x00 + 32 + + + cr_vdcfg2 + 3 + [3:0] + 0 + + + + + + SFR_VDCFG_CR_VDCFG3 + + 0x002c + 0x00 + 32 + + + cr_vdcfg3 + 3 + [3:0] + 0 + + + + + + SFR_VDCFG_CR_VDCFG4 + + 0x0030 + 0x00 + 32 + + + cr_vdcfg4 + 3 + [3:0] + 0 + + + + + + SFR_VDCFG_CR_VDCFG5 + + 0x0034 + 0x00 + 32 + + + cr_vdcfg5 + 3 + [3:0] + 0 + + + + + + SFR_VDCFG_CR_VDCFG6 + + 0x0038 + 0x00 + 32 + + + cr_vdcfg6 + 3 + [3:0] + 0 + + + + + + SFR_VDCFG_CR_VDCFG7 + + 0x003c + 0x00 + 32 + + + cr_vdcfg7 + 3 + [3:0] + 0 + + + + + + SFR_VDIP_ENA + + 0x0040 + 0x00 + 32 + + + vdena + 3 + [3:0] + 0 + + + + + + SFR_VDIP_TEST + + 0x0044 + 0x00 + 32 + + + vdtst + 7 + [7:0] + 0 + + + + + + SFR_LDIP_TEST + 0x0048 0x00 32 - sr_mdmareq2 - 4 - [4:0] + ldtst + 3 + [3:0] + 0 + + + + + + SFR_LDIP_FD + + 0x004c + 0x00 + 32 + + + sfr_ldip_fd + 15 + [15:0] + 0 + + + + + + + 0 + 0x50 + registers + + + + AOBUREG + 0x40065000 + AOBUREG + + + SFR_BUREG_CR_BUREGS0 + + 0x0000 + 0x00 + 32 + + + cr_buregs0 + 31 + [31:0] + 0 + + + + + + SFR_BUREG_CR_BUREGS1 + + 0x0004 + 0x00 + 32 + + + cr_buregs1 + 31 + [31:0] + 0 + + + + + + SFR_BUREG_CR_BUREGS2 + + 0x0008 + 0x00 + 32 + + + cr_buregs2 + 31 + [31:0] + 0 + + + + + + SFR_BUREG_CR_BUREGS3 + + 0x000c + 0x00 + 32 + + + cr_buregs3 + 31 + [31:0] + 0 + + + + + + SFR_BUREG_CR_BUREGS4 + + 0x0010 + 0x00 + 32 + + + cr_buregs4 + 31 + [31:0] + 0 + + + + + + SFR_BUREG_CR_BUREGS5 + + 0x0014 + 0x00 + 32 + + + cr_buregs5 + 31 + [31:0] + 0 + + + + + + SFR_BUREG_CR_BUREGS6 + + 0x0018 + 0x00 + 32 + + + cr_buregs6 + 31 + [31:0] + 0 + + + + + + SFR_BUREG_CR_BUREGS7 + + 0x001c + 0x00 + 32 + + + cr_buregs7 + 31 + [31:0] + 0 + + + + + + + 0 + 0x20 + registers + + + + AO_SYSCTRL + 0x40060000 + AO_SYSCTRL + + + CR_CLK32KSEL + + 0x0000 + 0x00 + 32 + + + cr_clk32ksel + 0 + [0:0] 0 - + - SFR_SR_SR_MDMAREQ3 - - 0x004c + CR_CLK1HZFD + + 0x0004 0x00 32 - sr_mdmareq3 - 4 - [4:0] + cr_clk1hzfd + 13 + [13:0] 0 - + - SFR_SR_SR_MDMAREQ4 - - 0x0050 + CR_WKUPMASK + + 0x0008 0x00 32 - sr_mdmareq4 - 4 - [4:0] + cr_wkupmask + 9 + [9:0] 0 - + - SFR_SR_SR_MDMAREQ5 - - 0x0054 + CR_RSTCRMASK + + 0x000c 0x00 32 - sr_mdmareq5 + cr_rstcrmask 4 [4:0] 0 - + - SFR_SR_SR_MDMAREQ6 - - 0x0058 + SFR_PMUCR + + 0x0010 0x00 32 - sr_mdmareq6 - 4 - [4:0] + sfrpmucr + 7 + [7:0] 0 - + - SFR_SR_SR_MDMAREQ7 - - 0x005c + SFR_PMUCRLP + + 0x0014 0x00 32 - sr_mdmareq7 - 4 - [4:0] + sfrpmucrlp + 7 + [7:0] 0 - + - - - 0 - 0x60 - registers - - - - QFC - 0x40010000 - QFC - - SFR_IO - - 0x0000 + SFR_PMUCRPD + + 0x0018 0x00 32 - sfr_io + sfrpmucrpd 7 [7:0] 0 - + - SFR_AR - - 0x0004 + SFR_PMUDFT + + 0x001c 0x00 32 - sfr_ar - 31 - [31:0] + sfrpmudft + 5 + [5:0] 0 - + - SFR_IODRV - - 0x0008 + SFR_PMUTRM0 + + 0x0020 0x00 32 - paddrvsel - 11 - [11:0] + sfrpmutrm + 31 + [31:0] 0 - + - CR_XIP_ADDRMODE - - 0x0010 + SFR_PMUTRM1 + + 0x0024 0x00 32 - cr_xip_addrmode + sfrpmutrm 1 [1:0] 0 - + - CR_XIP_OPCODE - - 0x0014 + SFR_PMUTRMLP0 + + 0x0028 0x00 32 - cr_xip_opcode + sfrpmutrmlp 31 [31:0] 0 - + - CR_XIP_WIDTH - - 0x0018 + SFR_PMUTRMLP1 + + 0x002c 0x00 32 - cr_xip_width - 5 - [5:0] + sfrpmutrmlp + 1 + [1:0] 0 - + - CR_XIP_SSEL - - 0x001c + SFR_OSCCR + + 0x0034 0x00 32 - cr_xip_ssel - 6 - [6:0] + sfrosccr + 0 + [0:0] 0 - + - - - - CR_XIP_DUMCYC - - 0x0020 - 0x00 - 32 - - cr_xip_dumcyc - 15 - [15:0] - 0 - + sfrosctrm + 1 + [1:1] + 1 + + + + sfrosccrlp + 2 + [2:2] + 2 + + + + sfrosctrmlp + 3 + [3:3] + 3 + + + + sfrosccrpd + 4 + [4:4] + 4 + - CR_XIP_CFG - - 0x0024 + SFR_PMUSR + + 0x0038 0x00 32 - cr_xip_cfg - 14 - [14:0] + sfr_pmusr + 4 + [4:0] 0 - + - CR_AESKEY_AESKEYIN0 - - 0x0040 + SFR_PMUFR + + 0x003c 0x00 32 - aeskeyin0 - 31 - [31:0] + sfr_pmufr + 4 + [4:0] 0 - + - CR_AESKEY_AESKEYIN1 - - 0x0044 + SFR_AOFR + + 0x0040 0x00 32 - aeskeyin1 - 31 - [31:0] + sfr_aofr + 9 + [9:0] 0 - + - CR_AESKEY_AESKEYIN2 - - 0x0048 + SFR_PMUPDAR + + 0x0044 0x00 32 - aeskeyin2 + sfr_pmupdar 31 [31:0] 0 - + - CR_AESKEY_AESKEYIN3 - - 0x004c + AR_AOPERI_CLRINT + + 0x0050 0x00 32 - aeskeyin3 + ar_aoperi_clrint 31 [31:0] 0 - + - CR_AESENA - - 0x0050 + SFR_IOX + + 0x0060 0x00 32 - cr_aesena + sfr_iox 0 [0:0] 0 - + 0 - 0x54 + 0x64 registers - MBOX_APB - 0x40013000 - MBOX_APB + DKPC + 0x40064000 + DKPC - SFR_WDATA - + SFR_CFG0 + 0x0000 0x00 32 - sfr_wdata - 31 - [31:0] - 0 - - - - - - SFR_RDATA - - 0x0004 - 0x00 - 32 - - - sfr_rdata - 31 - [31:0] - 0 - - - - - - SFR_STATUS - - 0x0008 - 0x00 - 32 - - - rx_avail + KPOPO0 0 [0:0] 0 - + - tx_free + KPOPO1 1 [1:1] 1 - + - abort_in_progress + KPOOE0 2 [2:2] 2 - + - abort_ack + KPOOE1 3 [3:3] 3 - + - tx_err + dkpcen 4 [4:4] 4 - + - rx_err + autosleepen 5 [5:5] 5 - + - SFR_ABORT - - 0x0018 + SFR_CFG1 + + 0x0004 0x00 32 - sfr_abort - 31 - [31:0] + cfg_step + 7 + [7:0] 0 - + + + + cfg_filter + 15 + [15:8] + 8 + + + + cfg_cnt1ms + 23 + [23:16] + 16 + - SFR_DONE - - 0x001c + SFR_CFG2 + + 0x0008 0x00 32 - sfr_done + cfg_cnt 31 [31:0] 0 - + - - - 0 - 0x20 - registers - - - - GLUECHAIN - 0x40054000 - GLUECHAIN - - SFR_GCMASK - - 0x0000 + SFR_CFG3 + + 0x000c 0x00 32 - cr_gcmask - 31 - [31:0] + kpnoderiseen + 0 + [0:0] 0 - + + + + kpnodefallen + 1 + [1:1] + 1 + - SFR_GCSR - - 0x0004 + SFR_SR0 + + 0x0010 0x00 32 - gluereg - 31 - [31:0] + kpnodereg + 0 + [0:0] 0 - + + + + kpi0_pi + 1 + [1:1] + 1 + + + + kpi1_pi + 2 + [2:2] + 2 + + + + kpi2_pi + 3 + [3:3] + 3 + + + + kpi3_pi + 4 + [4:4] + 4 + - SFR_GCRST - - 0x0008 + SFR_SR1 + + 0x0014 0x00 32 - gluerst - 31 - [31:0] + sfr_sr1 + 0 + [0:0] 0 - + - SFR_GCTEST - - 0x000c + SFR_CFG4 + + 0x0030 0x00 32 - gluetest - 31 - [31:0] + sfr_cfg4 + 15 + [15:0] 0 - + 0 - 0x10 + 0x34 registers @@ -10192,13 +13389,6 @@ respective bit position to clear the flag]]> 4 - - r_rx_clr - 6 - [6:6] - 6 - - @@ -10254,13 +13444,6 @@ respective bit position to clear the flag]]> 4 - - r_tx_clr - 6 - [6:6] - 6 - - @@ -10316,13 +13499,6 @@ respective bit position to clear the flag]]> 4 - - r_cmd_clr - 6 - [6:6] - 6 - - @@ -10348,22 +13524,6 @@ respective bit position to clear the flag]]> - - REG_SETUP - - 0x0034 - 0x00 - 32 - - - r_do_rst - 0 - [0:0] - 0 - - - - REG_ACK @@ -10445,13 +13605,6 @@ respective bit position to clear the flag]]> 4 - - r_rx_clr - 6 - [6:6] - 6 - - @@ -10507,13 +13660,6 @@ respective bit position to clear the flag]]> 4 - - r_tx_clr - 6 - [6:6] - 6 - - @@ -10569,13 +13715,6 @@ respective bit position to clear the flag]]> 4 - - r_cmd_clr - 6 - [6:6] - 6 - - @@ -10601,22 +13740,6 @@ respective bit position to clear the flag]]> - - REG_SETUP - - 0x0034 - 0x00 - 32 - - - r_do_rst - 0 - [0:0] - 0 - - - - REG_ACK @@ -10698,13 +13821,6 @@ respective bit position to clear the flag]]> 4 - - r_rx_clr - 6 - [6:6] - 6 - - @@ -10760,13 +13876,6 @@ respective bit position to clear the flag]]> 4 - - r_tx_clr - 6 - [6:6] - 6 - - @@ -10822,13 +13931,6 @@ respective bit position to clear the flag]]> 4 - - r_cmd_clr - 6 - [6:6] - 6 - - @@ -10854,22 +13956,6 @@ respective bit position to clear the flag]]> - - REG_SETUP - - 0x0034 - 0x00 - 32 - - - r_do_rst - 0 - [0:0] - 0 - - - - REG_ACK @@ -10951,13 +14037,6 @@ respective bit position to clear the flag]]> 4 - - r_rx_clr - 6 - [6:6] - 6 - - @@ -11013,13 +14092,6 @@ respective bit position to clear the flag]]> 4 - - r_tx_clr - 6 - [6:6] - 6 - - @@ -11075,13 +14147,6 @@ respective bit position to clear the flag]]> 4 - - r_cmd_clr - 6 - [6:6] - 6 - - @@ -11107,22 +14172,6 @@ respective bit position to clear the flag]]> - - REG_SETUP - - 0x0034 - 0x00 - 32 - - - r_do_rst - 0 - [0:0] - 0 - - - - REG_ACK @@ -14345,6 +17394,11 @@ respective bit position to clear the flag]]> 0x40010000 0x00010000 + + RRC + 0x40000000 + 0x00010000 + SECSUB 0x40050000 @@ -14360,6 +17414,16 @@ respective bit position to clear the flag]]> 0x50124000 0x00001000 + + AO + 0x40060000 + 0x00010000 + + + AOPERI + 0x40061000 + 0x00003000 + SEG_LKEY 0x40020000 @@ -14520,11 +17584,6 @@ respective bit position to clear the flag]]> 0x5012F000 0x00001000 - - AOC - 0x40060000 - 0x00001000 - BIO_IMEM0 0x50125000 diff --git a/utralib/src/generated/cramium_soc.rs b/utralib/src/generated/cramium_soc.rs index e9a1402be..3a95ab17e 100644 --- a/utralib/src/generated/cramium_soc.rs +++ b/utralib/src/generated/cramium_soc.rs @@ -254,12 +254,18 @@ pub const HW_IFSUB_MEM: usize = 0x50120000; pub const HW_IFSUB_MEM_LEN: usize = 12288; pub const HW_CORESUB_MEM: usize = 0x40010000; pub const HW_CORESUB_MEM_LEN: usize = 65536; +pub const HW_RRC_MEM: usize = 0x40000000; +pub const HW_RRC_MEM_LEN: usize = 65536; pub const HW_SECSUB_MEM: usize = 0x40050000; pub const HW_SECSUB_MEM_LEN: usize = 65536; pub const HW_PIO_MEM: usize = 0x50123000; pub const HW_PIO_MEM_LEN: usize = 4096; pub const HW_BIO_BDMA_MEM: usize = 0x50124000; pub const HW_BIO_BDMA_MEM_LEN: usize = 4096; +pub const HW_AO_MEM: usize = 0x40060000; +pub const HW_AO_MEM_LEN: usize = 65536; +pub const HW_AOPERI_MEM: usize = 0x40061000; +pub const HW_AOPERI_MEM_LEN: usize = 12288; pub const HW_SEG_LKEY_MEM: usize = 0x40020000; pub const HW_SEG_LKEY_MEM_LEN: usize = 256; pub const HW_SEG_KEY_MEM: usize = 0x40020100; @@ -324,8 +330,6 @@ pub const HW_MBOX_APB_MEM: usize = 0x40013000; pub const HW_MBOX_APB_MEM_LEN: usize = 4096; pub const HW_IOX_MEM: usize = 0x5012f000; pub const HW_IOX_MEM_LEN: usize = 4096; -pub const HW_AOC_MEM: usize = 0x40060000; -pub const HW_AOC_MEM_LEN: usize = 4096; pub const HW_BIO_IMEM0_MEM: usize = 0x50125000; pub const HW_BIO_IMEM0_MEM_LEN: usize = 4096; pub const HW_BIO_IMEM1_MEM: usize = 0x50126000; @@ -390,11 +394,18 @@ pub const HW_APB_THRU_BASE : usize = 0x50122000; pub const HW_BIO_BDMA_BASE : usize = 0x50124000; pub const HW_IOX_BASE : usize = 0x5012f000; pub const HW_PWM_BASE : usize = 0x50120000; +pub const HW_SDDC_BASE : usize = 0x50121000; pub const HW_CORESUB_SRAMTRM_BASE : usize = 0x40014000; pub const HW_MDMA_BASE : usize = 0x40012000; pub const HW_QFC_BASE : usize = 0x40010000; pub const HW_MBOX_APB_BASE : usize = 0x40013000; +pub const HW_RRC_BASE : usize = 0x40000000; pub const HW_GLUECHAIN_BASE : usize = 0x40054000; +pub const HW_MESH_BASE : usize = 0x40052000; +pub const HW_SENSORC_BASE : usize = 0x40053000; +pub const HW_AOBUREG_BASE : usize = 0x40065000; +pub const HW_AO_SYSCTRL_BASE : usize = 0x40060000; +pub const HW_DKPC_BASE : usize = 0x40064000; pub const HW_UDMA_CTRL_BASE : usize = 0x50100000; pub const HW_UDMA_UART_0_BASE : usize = 0x50101000; pub const HW_UDMA_UART_1_BASE : usize = 0x50102000; @@ -2454,8 +2465,8 @@ pub mod utra { pub const SFR_SUBEN: crate::Register = crate::Register::new(1, 0xffff); pub const SFR_SUBEN_CR_SUBEN: crate::Field = crate::Field::new(16, 0, SFR_SUBEN); - pub const SFR_AHBS: crate::Register = crate::Register::new(2, 0x1f); - pub const SFR_AHBS_CR_AHBSOPT: crate::Field = crate::Field::new(5, 0, SFR_AHBS); + pub const SFR_APBS: crate::Register = crate::Register::new(2, 0x1f); + pub const SFR_APBS_CR_APBSOPT: crate::Field = crate::Field::new(5, 0, SFR_APBS); pub const SFR_SRBUSY: crate::Register = crate::Register::new(4, 0xffff); pub const SFR_SRBUSY_SR_BUSY: crate::Field = crate::Field::new(16, 0, SFR_SRBUSY); @@ -3372,6 +3383,351 @@ pub mod utra { pub const HW_PWM_BASE: usize = 0x50120000; } + pub mod sddc { + pub const SDDC_NUMREGS: usize = 112; + + pub const SFR_IO: crate::Register = crate::Register::new(0, 0x3); + pub const SFR_IO_SFR_IO: crate::Field = crate::Field::new(2, 0, SFR_IO); + + pub const SFR_AR: crate::Register = crate::Register::new(1, 0xffffffff); + pub const SFR_AR_SFR_AR: crate::Field = crate::Field::new(32, 0, SFR_AR); + + pub const CR_OCR: crate::Register = crate::Register::new(4, 0xffffff); + pub const CR_OCR_CR_OCR: crate::Field = crate::Field::new(24, 0, CR_OCR); + + pub const CR_RDFFTHRES: crate::Register = crate::Register::new(5, 0xff); + pub const CR_RDFFTHRES_CR_RDFFTHRES: crate::Field = crate::Field::new(8, 0, CR_RDFFTHRES); + + pub const CR_REV: crate::Register = crate::Register::new(6, 0xffff); + pub const CR_REV_CFG_REG_SD_SPEC_REVISION: crate::Field = crate::Field::new(8, 0, CR_REV); + pub const CR_REV_CFG_REG_CCCR_SDIO_REVISION: crate::Field = crate::Field::new(8, 8, CR_REV); + + pub const CR_BACSA: crate::Register = crate::Register::new(7, 0x3ffff); + pub const CR_BACSA_CFG_BASE_ADDR_CSA: crate::Field = crate::Field::new(18, 0, CR_BACSA); + + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0: crate::Register = crate::Register::new(8, 0x3ffff); + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0_CFG_BASE_ADDR_IO_FUNC0: crate::Field = crate::Field::new(18, 0, CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0); + + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1: crate::Register = crate::Register::new(9, 0x3ffff); + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1_CFG_BASE_ADDR_IO_FUNC1: crate::Field = crate::Field::new(18, 0, CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1); + + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2: crate::Register = crate::Register::new(10, 0x3ffff); + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2_CFG_BASE_ADDR_IO_FUNC2: crate::Field = crate::Field::new(18, 0, CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2); + + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3: crate::Register = crate::Register::new(11, 0x3ffff); + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3_CFG_BASE_ADDR_IO_FUNC3: crate::Field = crate::Field::new(18, 0, CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3); + + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4: crate::Register = crate::Register::new(12, 0x3ffff); + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4_CFG_BASE_ADDR_IO_FUNC4: crate::Field = crate::Field::new(18, 0, CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4); + + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5: crate::Register = crate::Register::new(13, 0x3ffff); + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5_CFG_BASE_ADDR_IO_FUNC5: crate::Field = crate::Field::new(18, 0, CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5); + + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6: crate::Register = crate::Register::new(14, 0x3ffff); + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6_CFG_BASE_ADDR_IO_FUNC6: crate::Field = crate::Field::new(18, 0, CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6); + + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7: crate::Register = crate::Register::new(15, 0x3ffff); + pub const CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7_CFG_BASE_ADDR_IO_FUNC7: crate::Field = crate::Field::new(18, 0, CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7); + + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0: crate::Register = crate::Register::new(16, 0x1ffff); + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0_CFG_REG_FUNC_CIS_PTR0: crate::Field = crate::Field::new(17, 0, CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0); + + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1: crate::Register = crate::Register::new(17, 0x1ffff); + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1_CFG_REG_FUNC_CIS_PTR1: crate::Field = crate::Field::new(17, 0, CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1); + + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2: crate::Register = crate::Register::new(18, 0x1ffff); + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2_CFG_REG_FUNC_CIS_PTR2: crate::Field = crate::Field::new(17, 0, CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2); + + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3: crate::Register = crate::Register::new(19, 0x1ffff); + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3_CFG_REG_FUNC_CIS_PTR3: crate::Field = crate::Field::new(17, 0, CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3); + + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4: crate::Register = crate::Register::new(20, 0x1ffff); + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4_CFG_REG_FUNC_CIS_PTR4: crate::Field = crate::Field::new(17, 0, CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4); + + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5: crate::Register = crate::Register::new(21, 0x1ffff); + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5_CFG_REG_FUNC_CIS_PTR5: crate::Field = crate::Field::new(17, 0, CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5); + + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6: crate::Register = crate::Register::new(22, 0x1ffff); + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6_CFG_REG_FUNC_CIS_PTR6: crate::Field = crate::Field::new(17, 0, CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6); + + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7: crate::Register = crate::Register::new(23, 0x1ffff); + pub const CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7_CFG_REG_FUNC_CIS_PTR7: crate::Field = crate::Field::new(17, 0, CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7); + + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0: crate::Register = crate::Register::new(24, 0xff); + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0_CFG_REG_FUNC_EXT_STD_CODE0: crate::Field = crate::Field::new(8, 0, CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0); + + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1: crate::Register = crate::Register::new(25, 0xff); + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1_CFG_REG_FUNC_EXT_STD_CODE1: crate::Field = crate::Field::new(8, 0, CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1); + + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2: crate::Register = crate::Register::new(26, 0xff); + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2_CFG_REG_FUNC_EXT_STD_CODE2: crate::Field = crate::Field::new(8, 0, CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2); + + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3: crate::Register = crate::Register::new(27, 0xff); + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3_CFG_REG_FUNC_EXT_STD_CODE3: crate::Field = crate::Field::new(8, 0, CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3); + + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4: crate::Register = crate::Register::new(28, 0xff); + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4_CFG_REG_FUNC_EXT_STD_CODE4: crate::Field = crate::Field::new(8, 0, CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4); + + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5: crate::Register = crate::Register::new(29, 0xff); + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5_CFG_REG_FUNC_EXT_STD_CODE5: crate::Field = crate::Field::new(8, 0, CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5); + + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6: crate::Register = crate::Register::new(30, 0xff); + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6_CFG_REG_FUNC_EXT_STD_CODE6: crate::Field = crate::Field::new(8, 0, CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6); + + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7: crate::Register = crate::Register::new(31, 0xff); + pub const CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7_CFG_REG_FUNC_EXT_STD_CODE7: crate::Field = crate::Field::new(8, 0, CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7); + + pub const CR_WRITE_PROTECT: crate::Register = crate::Register::new(32, 0x1); + pub const CR_WRITE_PROTECT_CR_WRITE_PROTECT: crate::Field = crate::Field::new(1, 0, CR_WRITE_PROTECT); + + pub const CR_REG_DSR: crate::Register = crate::Register::new(33, 0xffff); + pub const CR_REG_DSR_CR_REG_DSR: crate::Field = crate::Field::new(16, 0, CR_REG_DSR); + + pub const CR_REG_CID_CFG_REG_CID0: crate::Register = crate::Register::new(34, 0xffffffff); + pub const CR_REG_CID_CFG_REG_CID0_CFG_REG_CID0: crate::Field = crate::Field::new(32, 0, CR_REG_CID_CFG_REG_CID0); + + pub const CR_REG_CID_CFG_REG_CID1: crate::Register = crate::Register::new(35, 0xffffffff); + pub const CR_REG_CID_CFG_REG_CID1_CFG_REG_CID1: crate::Field = crate::Field::new(32, 0, CR_REG_CID_CFG_REG_CID1); + + pub const CR_REG_CID_CFG_REG_CID2: crate::Register = crate::Register::new(36, 0xffffffff); + pub const CR_REG_CID_CFG_REG_CID2_CFG_REG_CID2: crate::Field = crate::Field::new(32, 0, CR_REG_CID_CFG_REG_CID2); + + pub const CR_REG_CID_CFG_REG_CID3: crate::Register = crate::Register::new(37, 0xffffffff); + pub const CR_REG_CID_CFG_REG_CID3_CFG_REG_CID3: crate::Field = crate::Field::new(32, 0, CR_REG_CID_CFG_REG_CID3); + + pub const CR_REG_CSD_CFG_REG_CSD0: crate::Register = crate::Register::new(38, 0xffffffff); + pub const CR_REG_CSD_CFG_REG_CSD0_CFG_REG_CSD0: crate::Field = crate::Field::new(32, 0, CR_REG_CSD_CFG_REG_CSD0); + + pub const CR_REG_CSD_CFG_REG_CSD1: crate::Register = crate::Register::new(39, 0xffffffff); + pub const CR_REG_CSD_CFG_REG_CSD1_CFG_REG_CSD1: crate::Field = crate::Field::new(32, 0, CR_REG_CSD_CFG_REG_CSD1); + + pub const CR_REG_CSD_CFG_REG_CSD2: crate::Register = crate::Register::new(40, 0xffffffff); + pub const CR_REG_CSD_CFG_REG_CSD2_CFG_REG_CSD2: crate::Field = crate::Field::new(32, 0, CR_REG_CSD_CFG_REG_CSD2); + + pub const CR_REG_CSD_CFG_REG_CSD3: crate::Register = crate::Register::new(41, 0xffffffff); + pub const CR_REG_CSD_CFG_REG_CSD3_CFG_REG_CSD3: crate::Field = crate::Field::new(32, 0, CR_REG_CSD_CFG_REG_CSD3); + + pub const CR_REG_SCR_CFG_REG_SCR0: crate::Register = crate::Register::new(42, 0xffffffff); + pub const CR_REG_SCR_CFG_REG_SCR0_CFG_REG_SCR0: crate::Field = crate::Field::new(32, 0, CR_REG_SCR_CFG_REG_SCR0); + + pub const CR_REG_SCR_CFG_REG_SCR1: crate::Register = crate::Register::new(43, 0xffffffff); + pub const CR_REG_SCR_CFG_REG_SCR1_CFG_REG_SCR1: crate::Field = crate::Field::new(32, 0, CR_REG_SCR_CFG_REG_SCR1); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS0: crate::Register = crate::Register::new(44, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS0_CFG_REG_SD_STATUS0: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS0); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS1: crate::Register = crate::Register::new(45, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS1_CFG_REG_SD_STATUS1: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS1); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS2: crate::Register = crate::Register::new(46, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS2_CFG_REG_SD_STATUS2: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS2); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS3: crate::Register = crate::Register::new(47, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS3_CFG_REG_SD_STATUS3: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS3); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS4: crate::Register = crate::Register::new(48, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS4_CFG_REG_SD_STATUS4: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS4); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS5: crate::Register = crate::Register::new(49, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS5_CFG_REG_SD_STATUS5: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS5); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS6: crate::Register = crate::Register::new(50, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS6_CFG_REG_SD_STATUS6: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS6); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS7: crate::Register = crate::Register::new(51, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS7_CFG_REG_SD_STATUS7: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS7); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS8: crate::Register = crate::Register::new(52, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS8_CFG_REG_SD_STATUS8: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS8); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS9: crate::Register = crate::Register::new(53, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS9_CFG_REG_SD_STATUS9: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS9); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS10: crate::Register = crate::Register::new(54, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS10_CFG_REG_SD_STATUS10: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS10); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS11: crate::Register = crate::Register::new(55, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS11_CFG_REG_SD_STATUS11: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS11); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS12: crate::Register = crate::Register::new(56, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS12_CFG_REG_SD_STATUS12: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS12); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS13: crate::Register = crate::Register::new(57, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS13_CFG_REG_SD_STATUS13: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS13); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS14: crate::Register = crate::Register::new(58, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS14_CFG_REG_SD_STATUS14: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS14); + + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS15: crate::Register = crate::Register::new(59, 0xffffffff); + pub const CR_REG_SD_STATUS_CFG_REG_SD_STATUS15_CFG_REG_SD_STATUS15: crate::Field = crate::Field::new(32, 0, CR_REG_SD_STATUS_CFG_REG_SD_STATUS15); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0: crate::Register = crate::Register::new(64, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0_CFG_BASE_ADDR_MEM_FUNC0: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1: crate::Register = crate::Register::new(65, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1_CFG_BASE_ADDR_MEM_FUNC1: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2: crate::Register = crate::Register::new(66, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2_CFG_BASE_ADDR_MEM_FUNC2: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3: crate::Register = crate::Register::new(67, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3_CFG_BASE_ADDR_MEM_FUNC3: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4: crate::Register = crate::Register::new(68, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4_CFG_BASE_ADDR_MEM_FUNC4: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5: crate::Register = crate::Register::new(69, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5_CFG_BASE_ADDR_MEM_FUNC5: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6: crate::Register = crate::Register::new(70, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6_CFG_BASE_ADDR_MEM_FUNC6: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7: crate::Register = crate::Register::new(71, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7_CFG_BASE_ADDR_MEM_FUNC7: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8: crate::Register = crate::Register::new(72, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8_CFG_BASE_ADDR_MEM_FUNC8: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9: crate::Register = crate::Register::new(73, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9_CFG_BASE_ADDR_MEM_FUNC9: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10: crate::Register = crate::Register::new(74, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10_CFG_BASE_ADDR_MEM_FUNC10: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11: crate::Register = crate::Register::new(75, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11_CFG_BASE_ADDR_MEM_FUNC11: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12: crate::Register = crate::Register::new(76, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12_CFG_BASE_ADDR_MEM_FUNC12: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13: crate::Register = crate::Register::new(77, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13_CFG_BASE_ADDR_MEM_FUNC13: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14: crate::Register = crate::Register::new(78, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14_CFG_BASE_ADDR_MEM_FUNC14: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15: crate::Register = crate::Register::new(79, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15_CFG_BASE_ADDR_MEM_FUNC15: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16: crate::Register = crate::Register::new(80, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16_CFG_BASE_ADDR_MEM_FUNC16: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16); + + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17: crate::Register = crate::Register::new(81, 0x3ffff); + pub const CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17_CFG_BASE_ADDR_MEM_FUNC17: crate::Field = crate::Field::new(18, 0, CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17); + + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0: crate::Register = crate::Register::new(82, 0xff); + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0); + + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1: crate::Register = crate::Register::new(83, 0xff); + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1); + + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2: crate::Register = crate::Register::new(84, 0xff); + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2); + + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3: crate::Register = crate::Register::new(85, 0xff); + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3); + + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4: crate::Register = crate::Register::new(86, 0xff); + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4); + + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5: crate::Register = crate::Register::new(87, 0xff); + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5); + + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6: crate::Register = crate::Register::new(88, 0xff); + pub const CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6); + + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0: crate::Register = crate::Register::new(90, 0xffff); + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0_CFG_REG_FUNC_MANUFACT_CODE0: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0); + + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1: crate::Register = crate::Register::new(91, 0xffff); + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1_CFG_REG_FUNC_MANUFACT_CODE1: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1); + + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2: crate::Register = crate::Register::new(92, 0xffff); + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2_CFG_REG_FUNC_MANUFACT_CODE2: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2); + + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3: crate::Register = crate::Register::new(93, 0xffff); + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3_CFG_REG_FUNC_MANUFACT_CODE3: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3); + + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4: crate::Register = crate::Register::new(94, 0xffff); + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4_CFG_REG_FUNC_MANUFACT_CODE4: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4); + + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5: crate::Register = crate::Register::new(95, 0xffff); + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5_CFG_REG_FUNC_MANUFACT_CODE5: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5); + + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6: crate::Register = crate::Register::new(96, 0xffff); + pub const CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6_CFG_REG_FUNC_MANUFACT_CODE6: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6); + + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0: crate::Register = crate::Register::new(98, 0xffff); + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0_CFG_REG_FUNC_MANUFACT_INFO0: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0); + + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1: crate::Register = crate::Register::new(99, 0xffff); + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1_CFG_REG_FUNC_MANUFACT_INFO1: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1); + + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2: crate::Register = crate::Register::new(100, 0xffff); + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2_CFG_REG_FUNC_MANUFACT_INFO2: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2); + + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3: crate::Register = crate::Register::new(101, 0xffff); + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3_CFG_REG_FUNC_MANUFACT_INFO3: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3); + + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4: crate::Register = crate::Register::new(102, 0xffff); + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4_CFG_REG_FUNC_MANUFACT_INFO4: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4); + + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5: crate::Register = crate::Register::new(103, 0xffff); + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5_CFG_REG_FUNC_MANUFACT_INFO5: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5); + + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6: crate::Register = crate::Register::new(104, 0xffff); + pub const CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6_CFG_REG_FUNC_MANUFACT_INFO6: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6); + + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0: crate::Register = crate::Register::new(106, 0xff); + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0); + + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1: crate::Register = crate::Register::new(107, 0xff); + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1); + + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2: crate::Register = crate::Register::new(108, 0xff); + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2); + + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3: crate::Register = crate::Register::new(109, 0xff); + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3); + + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4: crate::Register = crate::Register::new(110, 0xff); + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4); + + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5: crate::Register = crate::Register::new(111, 0xff); + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5); + + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6: crate::Register = crate::Register::new(112, 0xff); + pub const CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6: crate::Field = crate::Field::new(8, 0, CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6); + + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0: crate::Register = crate::Register::new(114, 0xffff); + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0_CFG_REG_FUNC_INFO0: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0); + + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1: crate::Register = crate::Register::new(115, 0xffff); + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1_CFG_REG_FUNC_INFO1: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1); + + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2: crate::Register = crate::Register::new(116, 0xffff); + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2_CFG_REG_FUNC_INFO2: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2); + + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3: crate::Register = crate::Register::new(117, 0xffff); + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3_CFG_REG_FUNC_INFO3: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3); + + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4: crate::Register = crate::Register::new(118, 0xffff); + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4_CFG_REG_FUNC_INFO4: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4); + + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5: crate::Register = crate::Register::new(119, 0xffff); + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5_CFG_REG_FUNC_INFO5: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5); + + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6: crate::Register = crate::Register::new(120, 0xffff); + pub const CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6_CFG_REG_FUNC_INFO6: crate::Field = crate::Field::new(16, 0, CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6); + + pub const CR_REG_UHS_1_SUPPORT: crate::Register = crate::Register::new(124, 0xffffffff); + pub const CR_REG_UHS_1_SUPPORT_CFG_REG_MAX_CURRENT: crate::Field = crate::Field::new(16, 0, CR_REG_UHS_1_SUPPORT); + pub const CR_REG_UHS_1_SUPPORT_CFG_REG_DATA_STRC_VERSION: crate::Field = crate::Field::new(8, 16, CR_REG_UHS_1_SUPPORT); + pub const CR_REG_UHS_1_SUPPORT_CFG_REG_UHS_1_SUPPORT: crate::Field = crate::Field::new(8, 24, CR_REG_UHS_1_SUPPORT); + + pub const HW_SDDC_BASE: usize = 0x50121000; + } + pub mod coresub_sramtrm { pub const CORESUB_SRAMTRM_NUMREGS: usize = 7; @@ -3551,6 +3907,45 @@ pub mod utra { pub const HW_MBOX_APB_BASE: usize = 0x40013000; } + pub mod rrc { + pub const RRC_NUMREGS: usize = 11; + + pub const SFR_RRCCR: crate::Register = crate::Register::new(0, 0x3); + pub const SFR_RRCCR_SFR_RRCCR: crate::Field = crate::Field::new(2, 0, SFR_RRCCR); + + pub const SFR_RRCFD: crate::Register = crate::Register::new(1, 0x1f); + pub const SFR_RRCFD_SFR_RRCFD: crate::Field = crate::Field::new(5, 0, SFR_RRCFD); + + pub const SFR_RRCSR: crate::Register = crate::Register::new(2, 0x3ff); + pub const SFR_RRCSR_SFR_RRCSR: crate::Field = crate::Field::new(10, 0, SFR_RRCSR); + + pub const SFR_RRCFR: crate::Register = crate::Register::new(3, 0xf); + pub const SFR_RRCFR_SFR_RRCFR: crate::Field = crate::Field::new(4, 0, SFR_RRCFR); + + pub const SFR_RRCAR: crate::Register = crate::Register::new(4, 0xffffffff); + pub const SFR_RRCAR_SFR_RRCAR: crate::Field = crate::Field::new(32, 0, SFR_RRCAR); + + pub const SFR_RRCSR_SET0: crate::Register = crate::Register::new(5, 0xffffffff); + pub const SFR_RRCSR_SET0_TRC_SET_FAILURE: crate::Field = crate::Field::new(32, 0, SFR_RRCSR_SET0); + + pub const SFR_RRCSR_SET1: crate::Register = crate::Register::new(6, 0xffffffff); + pub const SFR_RRCSR_SET1_TRC_SET_FAILURE: crate::Field = crate::Field::new(32, 0, SFR_RRCSR_SET1); + + pub const SFR_RRCSR_RST0: crate::Register = crate::Register::new(7, 0xffffffff); + pub const SFR_RRCSR_RST0_TRC_RESET_FAILURE: crate::Field = crate::Field::new(32, 0, SFR_RRCSR_RST0); + + pub const SFR_RRCSR_RST1: crate::Register = crate::Register::new(8, 0xffffffff); + pub const SFR_RRCSR_RST1_TRC_RESET_FAILURE: crate::Field = crate::Field::new(32, 0, SFR_RRCSR_RST1); + + pub const SFR_RRCSR_RD0: crate::Register = crate::Register::new(9, 0xffffffff); + pub const SFR_RRCSR_RD0_TRC_FOURTH_READ_FAILURE: crate::Field = crate::Field::new(32, 0, SFR_RRCSR_RD0); + + pub const SFR_RRCSR_RD1: crate::Register = crate::Register::new(10, 0xffffffff); + pub const SFR_RRCSR_RD1_TRC_FOURTH_READ_FAILURE: crate::Field = crate::Field::new(32, 0, SFR_RRCSR_RD1); + + pub const HW_RRC_BASE: usize = 0x40000000; + } + pub mod gluechain { pub const GLUECHAIN_NUMREGS: usize = 4; @@ -3569,6 +3964,241 @@ pub mod utra { pub const HW_GLUECHAIN_BASE: usize = 0x40054000; } + pub mod mesh { + pub const MESH_NUMREGS: usize = 10; + + pub const SFR_MLDRV_CR_MLDRV0: crate::Register = crate::Register::new(0, 0xffffffff); + pub const SFR_MLDRV_CR_MLDRV0_CR_MLDRV0: crate::Field = crate::Field::new(32, 0, SFR_MLDRV_CR_MLDRV0); + + pub const SFR_MLIE_CR_MLIE0: crate::Register = crate::Register::new(1, 0xffffffff); + pub const SFR_MLIE_CR_MLIE0_CR_MLIE0: crate::Field = crate::Field::new(32, 0, SFR_MLIE_CR_MLIE0); + + pub const SFR_MLSR_SR_MLSR0: crate::Register = crate::Register::new(2, 0xffffffff); + pub const SFR_MLSR_SR_MLSR0_SR_MLSR0: crate::Field = crate::Field::new(32, 0, SFR_MLSR_SR_MLSR0); + + pub const SFR_MLSR_SR_MLSR1: crate::Register = crate::Register::new(3, 0xffffffff); + pub const SFR_MLSR_SR_MLSR1_SR_MLSR1: crate::Field = crate::Field::new(32, 0, SFR_MLSR_SR_MLSR1); + + pub const SFR_MLSR_SR_MLSR2: crate::Register = crate::Register::new(4, 0xffffffff); + pub const SFR_MLSR_SR_MLSR2_SR_MLSR2: crate::Field = crate::Field::new(32, 0, SFR_MLSR_SR_MLSR2); + + pub const SFR_MLSR_SR_MLSR3: crate::Register = crate::Register::new(5, 0xffffffff); + pub const SFR_MLSR_SR_MLSR3_SR_MLSR3: crate::Field = crate::Field::new(32, 0, SFR_MLSR_SR_MLSR3); + + pub const SFR_MLSR_SR_MLSR4: crate::Register = crate::Register::new(6, 0xffffffff); + pub const SFR_MLSR_SR_MLSR4_SR_MLSR4: crate::Field = crate::Field::new(32, 0, SFR_MLSR_SR_MLSR4); + + pub const SFR_MLSR_SR_MLSR5: crate::Register = crate::Register::new(7, 0xffffffff); + pub const SFR_MLSR_SR_MLSR5_SR_MLSR5: crate::Field = crate::Field::new(32, 0, SFR_MLSR_SR_MLSR5); + + pub const SFR_MLSR_SR_MLSR6: crate::Register = crate::Register::new(8, 0xffffffff); + pub const SFR_MLSR_SR_MLSR6_SR_MLSR6: crate::Field = crate::Field::new(32, 0, SFR_MLSR_SR_MLSR6); + + pub const SFR_MLSR_SR_MLSR7: crate::Register = crate::Register::new(9, 0xffffffff); + pub const SFR_MLSR_SR_MLSR7_SR_MLSR7: crate::Field = crate::Field::new(32, 0, SFR_MLSR_SR_MLSR7); + + pub const HW_MESH_BASE: usize = 0x40052000; + } + + pub mod sensorc { + pub const SENSORC_NUMREGS: usize = 19; + + pub const SFR_VDMASK0: crate::Register = crate::Register::new(0, 0xff); + pub const SFR_VDMASK0_CR_VDMASK0: crate::Field = crate::Field::new(8, 0, SFR_VDMASK0); + + pub const SFR_VDMASK1: crate::Register = crate::Register::new(1, 0xff); + pub const SFR_VDMASK1_CR_VDMASK1: crate::Field = crate::Field::new(8, 0, SFR_VDMASK1); + + pub const SFR_VDSR: crate::Register = crate::Register::new(2, 0xff); + pub const SFR_VDSR_VDFLAG: crate::Field = crate::Field::new(8, 0, SFR_VDSR); + + pub const SFR_VDFR: crate::Register = crate::Register::new(3, 0xff); + pub const SFR_VDFR_VDFLAG: crate::Field = crate::Field::new(8, 0, SFR_VDFR); + + pub const SFR_LDMASK: crate::Register = crate::Register::new(4, 0xf); + pub const SFR_LDMASK_CR_LDMASK: crate::Field = crate::Field::new(4, 0, SFR_LDMASK); + + pub const SFR_LDSR: crate::Register = crate::Register::new(5, 0xf); + pub const SFR_LDSR_SR_LDSR: crate::Field = crate::Field::new(4, 0, SFR_LDSR); + + pub const SFR_LDCFG: crate::Register = crate::Register::new(6, 0xf); + pub const SFR_LDCFG_SFR_LDCFG: crate::Field = crate::Field::new(4, 0, SFR_LDCFG); + + pub const SFR_VDCFG_CR_VDCFG0: crate::Register = crate::Register::new(8, 0xf); + pub const SFR_VDCFG_CR_VDCFG0_CR_VDCFG0: crate::Field = crate::Field::new(4, 0, SFR_VDCFG_CR_VDCFG0); + + pub const SFR_VDCFG_CR_VDCFG1: crate::Register = crate::Register::new(9, 0xf); + pub const SFR_VDCFG_CR_VDCFG1_CR_VDCFG1: crate::Field = crate::Field::new(4, 0, SFR_VDCFG_CR_VDCFG1); + + pub const SFR_VDCFG_CR_VDCFG2: crate::Register = crate::Register::new(10, 0xf); + pub const SFR_VDCFG_CR_VDCFG2_CR_VDCFG2: crate::Field = crate::Field::new(4, 0, SFR_VDCFG_CR_VDCFG2); + + pub const SFR_VDCFG_CR_VDCFG3: crate::Register = crate::Register::new(11, 0xf); + pub const SFR_VDCFG_CR_VDCFG3_CR_VDCFG3: crate::Field = crate::Field::new(4, 0, SFR_VDCFG_CR_VDCFG3); + + pub const SFR_VDCFG_CR_VDCFG4: crate::Register = crate::Register::new(12, 0xf); + pub const SFR_VDCFG_CR_VDCFG4_CR_VDCFG4: crate::Field = crate::Field::new(4, 0, SFR_VDCFG_CR_VDCFG4); + + pub const SFR_VDCFG_CR_VDCFG5: crate::Register = crate::Register::new(13, 0xf); + pub const SFR_VDCFG_CR_VDCFG5_CR_VDCFG5: crate::Field = crate::Field::new(4, 0, SFR_VDCFG_CR_VDCFG5); + + pub const SFR_VDCFG_CR_VDCFG6: crate::Register = crate::Register::new(14, 0xf); + pub const SFR_VDCFG_CR_VDCFG6_CR_VDCFG6: crate::Field = crate::Field::new(4, 0, SFR_VDCFG_CR_VDCFG6); + + pub const SFR_VDCFG_CR_VDCFG7: crate::Register = crate::Register::new(15, 0xf); + pub const SFR_VDCFG_CR_VDCFG7_CR_VDCFG7: crate::Field = crate::Field::new(4, 0, SFR_VDCFG_CR_VDCFG7); + + pub const SFR_VDIP_ENA: crate::Register = crate::Register::new(16, 0xf); + pub const SFR_VDIP_ENA_VDENA: crate::Field = crate::Field::new(4, 0, SFR_VDIP_ENA); + + pub const SFR_VDIP_TEST: crate::Register = crate::Register::new(17, 0xff); + pub const SFR_VDIP_TEST_VDTST: crate::Field = crate::Field::new(8, 0, SFR_VDIP_TEST); + + pub const SFR_LDIP_TEST: crate::Register = crate::Register::new(18, 0xf); + pub const SFR_LDIP_TEST_LDTST: crate::Field = crate::Field::new(4, 0, SFR_LDIP_TEST); + + pub const SFR_LDIP_FD: crate::Register = crate::Register::new(19, 0xffff); + pub const SFR_LDIP_FD_SFR_LDIP_FD: crate::Field = crate::Field::new(16, 0, SFR_LDIP_FD); + + pub const HW_SENSORC_BASE: usize = 0x40053000; + } + + pub mod aobureg { + pub const AOBUREG_NUMREGS: usize = 8; + + pub const SFR_BUREG_CR_BUREGS0: crate::Register = crate::Register::new(0, 0xffffffff); + pub const SFR_BUREG_CR_BUREGS0_CR_BUREGS0: crate::Field = crate::Field::new(32, 0, SFR_BUREG_CR_BUREGS0); + + pub const SFR_BUREG_CR_BUREGS1: crate::Register = crate::Register::new(1, 0xffffffff); + pub const SFR_BUREG_CR_BUREGS1_CR_BUREGS1: crate::Field = crate::Field::new(32, 0, SFR_BUREG_CR_BUREGS1); + + pub const SFR_BUREG_CR_BUREGS2: crate::Register = crate::Register::new(2, 0xffffffff); + pub const SFR_BUREG_CR_BUREGS2_CR_BUREGS2: crate::Field = crate::Field::new(32, 0, SFR_BUREG_CR_BUREGS2); + + pub const SFR_BUREG_CR_BUREGS3: crate::Register = crate::Register::new(3, 0xffffffff); + pub const SFR_BUREG_CR_BUREGS3_CR_BUREGS3: crate::Field = crate::Field::new(32, 0, SFR_BUREG_CR_BUREGS3); + + pub const SFR_BUREG_CR_BUREGS4: crate::Register = crate::Register::new(4, 0xffffffff); + pub const SFR_BUREG_CR_BUREGS4_CR_BUREGS4: crate::Field = crate::Field::new(32, 0, SFR_BUREG_CR_BUREGS4); + + pub const SFR_BUREG_CR_BUREGS5: crate::Register = crate::Register::new(5, 0xffffffff); + pub const SFR_BUREG_CR_BUREGS5_CR_BUREGS5: crate::Field = crate::Field::new(32, 0, SFR_BUREG_CR_BUREGS5); + + pub const SFR_BUREG_CR_BUREGS6: crate::Register = crate::Register::new(6, 0xffffffff); + pub const SFR_BUREG_CR_BUREGS6_CR_BUREGS6: crate::Field = crate::Field::new(32, 0, SFR_BUREG_CR_BUREGS6); + + pub const SFR_BUREG_CR_BUREGS7: crate::Register = crate::Register::new(7, 0xffffffff); + pub const SFR_BUREG_CR_BUREGS7_CR_BUREGS7: crate::Field = crate::Field::new(32, 0, SFR_BUREG_CR_BUREGS7); + + pub const HW_AOBUREG_BASE: usize = 0x40065000; + } + + pub mod ao_sysctrl { + pub const AO_SYSCTRL_NUMREGS: usize = 19; + + pub const CR_CLK32KSEL: crate::Register = crate::Register::new(0, 0x1); + pub const CR_CLK32KSEL_CR_CLK32KSEL: crate::Field = crate::Field::new(1, 0, CR_CLK32KSEL); + + pub const CR_CLK1HZFD: crate::Register = crate::Register::new(1, 0x3fff); + pub const CR_CLK1HZFD_CR_CLK1HZFD: crate::Field = crate::Field::new(14, 0, CR_CLK1HZFD); + + pub const CR_WKUPMASK: crate::Register = crate::Register::new(2, 0x3ff); + pub const CR_WKUPMASK_CR_WKUPMASK: crate::Field = crate::Field::new(10, 0, CR_WKUPMASK); + + pub const CR_RSTCRMASK: crate::Register = crate::Register::new(3, 0x1f); + pub const CR_RSTCRMASK_CR_RSTCRMASK: crate::Field = crate::Field::new(5, 0, CR_RSTCRMASK); + + pub const SFR_PMUCR: crate::Register = crate::Register::new(4, 0xff); + pub const SFR_PMUCR_SFRPMUCR: crate::Field = crate::Field::new(8, 0, SFR_PMUCR); + + pub const SFR_PMUCRLP: crate::Register = crate::Register::new(5, 0xff); + pub const SFR_PMUCRLP_SFRPMUCRLP: crate::Field = crate::Field::new(8, 0, SFR_PMUCRLP); + + pub const SFR_PMUCRPD: crate::Register = crate::Register::new(6, 0xff); + pub const SFR_PMUCRPD_SFRPMUCRPD: crate::Field = crate::Field::new(8, 0, SFR_PMUCRPD); + + pub const SFR_PMUDFT: crate::Register = crate::Register::new(7, 0x3f); + pub const SFR_PMUDFT_SFRPMUDFT: crate::Field = crate::Field::new(6, 0, SFR_PMUDFT); + + pub const SFR_PMUTRM0: crate::Register = crate::Register::new(8, 0xffffffff); + pub const SFR_PMUTRM0_SFRPMUTRM: crate::Field = crate::Field::new(32, 0, SFR_PMUTRM0); + + pub const SFR_PMUTRM1: crate::Register = crate::Register::new(9, 0x3); + pub const SFR_PMUTRM1_SFRPMUTRM: crate::Field = crate::Field::new(2, 0, SFR_PMUTRM1); + + pub const SFR_PMUTRMLP0: crate::Register = crate::Register::new(10, 0xffffffff); + pub const SFR_PMUTRMLP0_SFRPMUTRMLP: crate::Field = crate::Field::new(32, 0, SFR_PMUTRMLP0); + + pub const SFR_PMUTRMLP1: crate::Register = crate::Register::new(11, 0x3); + pub const SFR_PMUTRMLP1_SFRPMUTRMLP: crate::Field = crate::Field::new(2, 0, SFR_PMUTRMLP1); + + pub const SFR_OSCCR: crate::Register = crate::Register::new(13, 0x1f); + pub const SFR_OSCCR_SFROSCCR: crate::Field = crate::Field::new(1, 0, SFR_OSCCR); + pub const SFR_OSCCR_SFROSCTRM: crate::Field = crate::Field::new(1, 1, SFR_OSCCR); + pub const SFR_OSCCR_SFROSCCRLP: crate::Field = crate::Field::new(1, 2, SFR_OSCCR); + pub const SFR_OSCCR_SFROSCTRMLP: crate::Field = crate::Field::new(1, 3, SFR_OSCCR); + pub const SFR_OSCCR_SFROSCCRPD: crate::Field = crate::Field::new(1, 4, SFR_OSCCR); + + pub const SFR_PMUSR: crate::Register = crate::Register::new(14, 0x1f); + pub const SFR_PMUSR_SFR_PMUSR: crate::Field = crate::Field::new(5, 0, SFR_PMUSR); + + pub const SFR_PMUFR: crate::Register = crate::Register::new(15, 0x1f); + pub const SFR_PMUFR_SFR_PMUFR: crate::Field = crate::Field::new(5, 0, SFR_PMUFR); + + pub const SFR_AOFR: crate::Register = crate::Register::new(16, 0x3ff); + pub const SFR_AOFR_SFR_AOFR: crate::Field = crate::Field::new(10, 0, SFR_AOFR); + + pub const SFR_PMUPDAR: crate::Register = crate::Register::new(17, 0xffffffff); + pub const SFR_PMUPDAR_SFR_PMUPDAR: crate::Field = crate::Field::new(32, 0, SFR_PMUPDAR); + + pub const AR_AOPERI_CLRINT: crate::Register = crate::Register::new(20, 0xffffffff); + pub const AR_AOPERI_CLRINT_AR_AOPERI_CLRINT: crate::Field = crate::Field::new(32, 0, AR_AOPERI_CLRINT); + + pub const SFR_IOX: crate::Register = crate::Register::new(24, 0x1); + pub const SFR_IOX_SFR_IOX: crate::Field = crate::Field::new(1, 0, SFR_IOX); + + pub const HW_AO_SYSCTRL_BASE: usize = 0x40060000; + } + + pub mod dkpc { + pub const DKPC_NUMREGS: usize = 7; + + pub const SFR_CFG0: crate::Register = crate::Register::new(0, 0x3f); + pub const SFR_CFG0_KPOPO0: crate::Field = crate::Field::new(1, 0, SFR_CFG0); + pub const SFR_CFG0_KPOPO1: crate::Field = crate::Field::new(1, 1, SFR_CFG0); + pub const SFR_CFG0_KPOOE0: crate::Field = crate::Field::new(1, 2, SFR_CFG0); + pub const SFR_CFG0_KPOOE1: crate::Field = crate::Field::new(1, 3, SFR_CFG0); + pub const SFR_CFG0_DKPCEN: crate::Field = crate::Field::new(1, 4, SFR_CFG0); + pub const SFR_CFG0_AUTOSLEEPEN: crate::Field = crate::Field::new(1, 5, SFR_CFG0); + + pub const SFR_CFG1: crate::Register = crate::Register::new(1, 0xffffff); + pub const SFR_CFG1_CFG_STEP: crate::Field = crate::Field::new(8, 0, SFR_CFG1); + pub const SFR_CFG1_CFG_FILTER: crate::Field = crate::Field::new(8, 8, SFR_CFG1); + pub const SFR_CFG1_CFG_CNT1MS: crate::Field = crate::Field::new(8, 16, SFR_CFG1); + + pub const SFR_CFG2: crate::Register = crate::Register::new(2, 0xffffffff); + pub const SFR_CFG2_CFG_CNT: crate::Field = crate::Field::new(32, 0, SFR_CFG2); + + pub const SFR_CFG3: crate::Register = crate::Register::new(3, 0x3); + pub const SFR_CFG3_KPNODERISEEN: crate::Field = crate::Field::new(1, 0, SFR_CFG3); + pub const SFR_CFG3_KPNODEFALLEN: crate::Field = crate::Field::new(1, 1, SFR_CFG3); + + pub const SFR_SR0: crate::Register = crate::Register::new(4, 0x1f); + pub const SFR_SR0_KPNODEREG: crate::Field = crate::Field::new(1, 0, SFR_SR0); + pub const SFR_SR0_KPI0_PI: crate::Field = crate::Field::new(1, 1, SFR_SR0); + pub const SFR_SR0_KPI1_PI: crate::Field = crate::Field::new(1, 2, SFR_SR0); + pub const SFR_SR0_KPI2_PI: crate::Field = crate::Field::new(1, 3, SFR_SR0); + pub const SFR_SR0_KPI3_PI: crate::Field = crate::Field::new(1, 4, SFR_SR0); + + pub const SFR_SR1: crate::Register = crate::Register::new(5, 0x1); + pub const SFR_SR1_SFR_SR1: crate::Field = crate::Field::new(1, 0, SFR_SR1); + + pub const SFR_CFG4: crate::Register = crate::Register::new(12, 0xffff); + pub const SFR_CFG4_SFR_CFG4: crate::Field = crate::Field::new(16, 0, SFR_CFG4); + + pub const HW_DKPC_BASE: usize = 0x40064000; + } + pub mod udma_ctrl { pub const UDMA_CTRL_NUMREGS: usize = 3; @@ -3988,7 +4618,7 @@ pub mod utra { } pub mod udma_i2c_0 { - pub const UDMA_I2C_0_NUMREGS: usize = 12; + pub const UDMA_I2C_0_NUMREGS: usize = 11; pub const REG_RX_SADDR: crate::Register = crate::Register::new(0, 0xfff); pub const REG_RX_SADDR_R_RX_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_RX_SADDR); @@ -3996,10 +4626,9 @@ pub mod utra { pub const REG_RX_SIZE: crate::Register = crate::Register::new(1, 0xffff); pub const REG_RX_SIZE_R_RX_SIZE: crate::Field = crate::Field::new(16, 0, REG_RX_SIZE); - pub const REG_RX_CFG: crate::Register = crate::Register::new(2, 0x51); + pub const REG_RX_CFG: crate::Register = crate::Register::new(2, 0x11); pub const REG_RX_CFG_R_RX_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_RX_CFG); pub const REG_RX_CFG_R_RX_EN: crate::Field = crate::Field::new(1, 4, REG_RX_CFG); - pub const REG_RX_CFG_R_RX_CLR: crate::Field = crate::Field::new(1, 6, REG_RX_CFG); pub const REG_TX_SADDR: crate::Register = crate::Register::new(4, 0xfff); pub const REG_TX_SADDR_R_TX_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_TX_SADDR); @@ -4007,10 +4636,9 @@ pub mod utra { pub const REG_TX_SIZE: crate::Register = crate::Register::new(5, 0xffff); pub const REG_TX_SIZE_R_TX_SIZE: crate::Field = crate::Field::new(16, 0, REG_TX_SIZE); - pub const REG_TX_CFG: crate::Register = crate::Register::new(6, 0x51); + pub const REG_TX_CFG: crate::Register = crate::Register::new(6, 0x11); pub const REG_TX_CFG_R_TX_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_TX_CFG); pub const REG_TX_CFG_R_TX_EN: crate::Field = crate::Field::new(1, 4, REG_TX_CFG); - pub const REG_TX_CFG_R_TX_CLR: crate::Field = crate::Field::new(1, 6, REG_TX_CFG); pub const REG_CMD_SADDR: crate::Register = crate::Register::new(8, 0xfff); pub const REG_CMD_SADDR_R_CMD_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_CMD_SADDR); @@ -4018,18 +4646,14 @@ pub mod utra { pub const REG_CMD_SIZE: crate::Register = crate::Register::new(9, 0xffff); pub const REG_CMD_SIZE_R_CMD_SIZE: crate::Field = crate::Field::new(16, 0, REG_CMD_SIZE); - pub const REG_CMD_CFG: crate::Register = crate::Register::new(10, 0x51); + pub const REG_CMD_CFG: crate::Register = crate::Register::new(10, 0x11); pub const REG_CMD_CFG_R_CMD_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_CMD_CFG); pub const REG_CMD_CFG_R_CMD_EN: crate::Field = crate::Field::new(1, 4, REG_CMD_CFG); - pub const REG_CMD_CFG_R_CMD_CLR: crate::Field = crate::Field::new(1, 6, REG_CMD_CFG); pub const REG_STATUS: crate::Register = crate::Register::new(12, 0x3); pub const REG_STATUS_R_BUSY: crate::Field = crate::Field::new(1, 0, REG_STATUS); pub const REG_STATUS_R_AL: crate::Field = crate::Field::new(1, 1, REG_STATUS); - pub const REG_SETUP: crate::Register = crate::Register::new(13, 0x1); - pub const REG_SETUP_R_DO_RST: crate::Field = crate::Field::new(1, 0, REG_SETUP); - pub const REG_ACK: crate::Register = crate::Register::new(14, 0x1); pub const REG_ACK_R_NACK: crate::Field = crate::Field::new(1, 0, REG_ACK); @@ -4037,7 +4661,7 @@ pub mod utra { } pub mod udma_i2c_1 { - pub const UDMA_I2C_1_NUMREGS: usize = 12; + pub const UDMA_I2C_1_NUMREGS: usize = 11; pub const REG_RX_SADDR: crate::Register = crate::Register::new(0, 0xfff); pub const REG_RX_SADDR_R_RX_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_RX_SADDR); @@ -4045,10 +4669,9 @@ pub mod utra { pub const REG_RX_SIZE: crate::Register = crate::Register::new(1, 0xffff); pub const REG_RX_SIZE_R_RX_SIZE: crate::Field = crate::Field::new(16, 0, REG_RX_SIZE); - pub const REG_RX_CFG: crate::Register = crate::Register::new(2, 0x51); + pub const REG_RX_CFG: crate::Register = crate::Register::new(2, 0x11); pub const REG_RX_CFG_R_RX_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_RX_CFG); pub const REG_RX_CFG_R_RX_EN: crate::Field = crate::Field::new(1, 4, REG_RX_CFG); - pub const REG_RX_CFG_R_RX_CLR: crate::Field = crate::Field::new(1, 6, REG_RX_CFG); pub const REG_TX_SADDR: crate::Register = crate::Register::new(4, 0xfff); pub const REG_TX_SADDR_R_TX_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_TX_SADDR); @@ -4056,10 +4679,9 @@ pub mod utra { pub const REG_TX_SIZE: crate::Register = crate::Register::new(5, 0xffff); pub const REG_TX_SIZE_R_TX_SIZE: crate::Field = crate::Field::new(16, 0, REG_TX_SIZE); - pub const REG_TX_CFG: crate::Register = crate::Register::new(6, 0x51); + pub const REG_TX_CFG: crate::Register = crate::Register::new(6, 0x11); pub const REG_TX_CFG_R_TX_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_TX_CFG); pub const REG_TX_CFG_R_TX_EN: crate::Field = crate::Field::new(1, 4, REG_TX_CFG); - pub const REG_TX_CFG_R_TX_CLR: crate::Field = crate::Field::new(1, 6, REG_TX_CFG); pub const REG_CMD_SADDR: crate::Register = crate::Register::new(8, 0xfff); pub const REG_CMD_SADDR_R_CMD_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_CMD_SADDR); @@ -4067,18 +4689,14 @@ pub mod utra { pub const REG_CMD_SIZE: crate::Register = crate::Register::new(9, 0xffff); pub const REG_CMD_SIZE_R_CMD_SIZE: crate::Field = crate::Field::new(16, 0, REG_CMD_SIZE); - pub const REG_CMD_CFG: crate::Register = crate::Register::new(10, 0x51); + pub const REG_CMD_CFG: crate::Register = crate::Register::new(10, 0x11); pub const REG_CMD_CFG_R_CMD_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_CMD_CFG); pub const REG_CMD_CFG_R_CMD_EN: crate::Field = crate::Field::new(1, 4, REG_CMD_CFG); - pub const REG_CMD_CFG_R_CMD_CLR: crate::Field = crate::Field::new(1, 6, REG_CMD_CFG); pub const REG_STATUS: crate::Register = crate::Register::new(12, 0x3); pub const REG_STATUS_R_BUSY: crate::Field = crate::Field::new(1, 0, REG_STATUS); pub const REG_STATUS_R_AL: crate::Field = crate::Field::new(1, 1, REG_STATUS); - pub const REG_SETUP: crate::Register = crate::Register::new(13, 0x1); - pub const REG_SETUP_R_DO_RST: crate::Field = crate::Field::new(1, 0, REG_SETUP); - pub const REG_ACK: crate::Register = crate::Register::new(14, 0x1); pub const REG_ACK_R_NACK: crate::Field = crate::Field::new(1, 0, REG_ACK); @@ -4086,7 +4704,7 @@ pub mod utra { } pub mod udma_i2c_2 { - pub const UDMA_I2C_2_NUMREGS: usize = 12; + pub const UDMA_I2C_2_NUMREGS: usize = 11; pub const REG_RX_SADDR: crate::Register = crate::Register::new(0, 0xfff); pub const REG_RX_SADDR_R_RX_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_RX_SADDR); @@ -4094,10 +4712,9 @@ pub mod utra { pub const REG_RX_SIZE: crate::Register = crate::Register::new(1, 0xffff); pub const REG_RX_SIZE_R_RX_SIZE: crate::Field = crate::Field::new(16, 0, REG_RX_SIZE); - pub const REG_RX_CFG: crate::Register = crate::Register::new(2, 0x51); + pub const REG_RX_CFG: crate::Register = crate::Register::new(2, 0x11); pub const REG_RX_CFG_R_RX_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_RX_CFG); pub const REG_RX_CFG_R_RX_EN: crate::Field = crate::Field::new(1, 4, REG_RX_CFG); - pub const REG_RX_CFG_R_RX_CLR: crate::Field = crate::Field::new(1, 6, REG_RX_CFG); pub const REG_TX_SADDR: crate::Register = crate::Register::new(4, 0xfff); pub const REG_TX_SADDR_R_TX_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_TX_SADDR); @@ -4105,10 +4722,9 @@ pub mod utra { pub const REG_TX_SIZE: crate::Register = crate::Register::new(5, 0xffff); pub const REG_TX_SIZE_R_TX_SIZE: crate::Field = crate::Field::new(16, 0, REG_TX_SIZE); - pub const REG_TX_CFG: crate::Register = crate::Register::new(6, 0x51); + pub const REG_TX_CFG: crate::Register = crate::Register::new(6, 0x11); pub const REG_TX_CFG_R_TX_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_TX_CFG); pub const REG_TX_CFG_R_TX_EN: crate::Field = crate::Field::new(1, 4, REG_TX_CFG); - pub const REG_TX_CFG_R_TX_CLR: crate::Field = crate::Field::new(1, 6, REG_TX_CFG); pub const REG_CMD_SADDR: crate::Register = crate::Register::new(8, 0xfff); pub const REG_CMD_SADDR_R_CMD_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_CMD_SADDR); @@ -4116,18 +4732,14 @@ pub mod utra { pub const REG_CMD_SIZE: crate::Register = crate::Register::new(9, 0xffff); pub const REG_CMD_SIZE_R_CMD_SIZE: crate::Field = crate::Field::new(16, 0, REG_CMD_SIZE); - pub const REG_CMD_CFG: crate::Register = crate::Register::new(10, 0x51); + pub const REG_CMD_CFG: crate::Register = crate::Register::new(10, 0x11); pub const REG_CMD_CFG_R_CMD_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_CMD_CFG); pub const REG_CMD_CFG_R_CMD_EN: crate::Field = crate::Field::new(1, 4, REG_CMD_CFG); - pub const REG_CMD_CFG_R_CMD_CLR: crate::Field = crate::Field::new(1, 6, REG_CMD_CFG); pub const REG_STATUS: crate::Register = crate::Register::new(12, 0x3); pub const REG_STATUS_R_BUSY: crate::Field = crate::Field::new(1, 0, REG_STATUS); pub const REG_STATUS_R_AL: crate::Field = crate::Field::new(1, 1, REG_STATUS); - pub const REG_SETUP: crate::Register = crate::Register::new(13, 0x1); - pub const REG_SETUP_R_DO_RST: crate::Field = crate::Field::new(1, 0, REG_SETUP); - pub const REG_ACK: crate::Register = crate::Register::new(14, 0x1); pub const REG_ACK_R_NACK: crate::Field = crate::Field::new(1, 0, REG_ACK); @@ -4135,7 +4747,7 @@ pub mod utra { } pub mod udma_i2c_3 { - pub const UDMA_I2C_3_NUMREGS: usize = 12; + pub const UDMA_I2C_3_NUMREGS: usize = 11; pub const REG_RX_SADDR: crate::Register = crate::Register::new(0, 0xfff); pub const REG_RX_SADDR_R_RX_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_RX_SADDR); @@ -4143,10 +4755,9 @@ pub mod utra { pub const REG_RX_SIZE: crate::Register = crate::Register::new(1, 0xffff); pub const REG_RX_SIZE_R_RX_SIZE: crate::Field = crate::Field::new(16, 0, REG_RX_SIZE); - pub const REG_RX_CFG: crate::Register = crate::Register::new(2, 0x51); + pub const REG_RX_CFG: crate::Register = crate::Register::new(2, 0x11); pub const REG_RX_CFG_R_RX_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_RX_CFG); pub const REG_RX_CFG_R_RX_EN: crate::Field = crate::Field::new(1, 4, REG_RX_CFG); - pub const REG_RX_CFG_R_RX_CLR: crate::Field = crate::Field::new(1, 6, REG_RX_CFG); pub const REG_TX_SADDR: crate::Register = crate::Register::new(4, 0xfff); pub const REG_TX_SADDR_R_TX_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_TX_SADDR); @@ -4154,10 +4765,9 @@ pub mod utra { pub const REG_TX_SIZE: crate::Register = crate::Register::new(5, 0xffff); pub const REG_TX_SIZE_R_TX_SIZE: crate::Field = crate::Field::new(16, 0, REG_TX_SIZE); - pub const REG_TX_CFG: crate::Register = crate::Register::new(6, 0x51); + pub const REG_TX_CFG: crate::Register = crate::Register::new(6, 0x11); pub const REG_TX_CFG_R_TX_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_TX_CFG); pub const REG_TX_CFG_R_TX_EN: crate::Field = crate::Field::new(1, 4, REG_TX_CFG); - pub const REG_TX_CFG_R_TX_CLR: crate::Field = crate::Field::new(1, 6, REG_TX_CFG); pub const REG_CMD_SADDR: crate::Register = crate::Register::new(8, 0xfff); pub const REG_CMD_SADDR_R_CMD_STARTADDR: crate::Field = crate::Field::new(12, 0, REG_CMD_SADDR); @@ -4165,18 +4775,14 @@ pub mod utra { pub const REG_CMD_SIZE: crate::Register = crate::Register::new(9, 0xffff); pub const REG_CMD_SIZE_R_CMD_SIZE: crate::Field = crate::Field::new(16, 0, REG_CMD_SIZE); - pub const REG_CMD_CFG: crate::Register = crate::Register::new(10, 0x51); + pub const REG_CMD_CFG: crate::Register = crate::Register::new(10, 0x11); pub const REG_CMD_CFG_R_CMD_CONTINUOUS: crate::Field = crate::Field::new(1, 0, REG_CMD_CFG); pub const REG_CMD_CFG_R_CMD_EN: crate::Field = crate::Field::new(1, 4, REG_CMD_CFG); - pub const REG_CMD_CFG_R_CMD_CLR: crate::Field = crate::Field::new(1, 6, REG_CMD_CFG); pub const REG_STATUS: crate::Register = crate::Register::new(12, 0x3); pub const REG_STATUS_R_BUSY: crate::Field = crate::Field::new(1, 0, REG_STATUS); pub const REG_STATUS_R_AL: crate::Field = crate::Field::new(1, 1, REG_STATUS); - pub const REG_SETUP: crate::Register = crate::Register::new(13, 0x1); - pub const REG_SETUP_R_DO_RST: crate::Field = crate::Field::new(1, 0, REG_SETUP); - pub const REG_ACK: crate::Register = crate::Register::new(14, 0x1); pub const REG_ACK_R_NACK: crate::Field = crate::Field::new(1, 0, REG_ACK); @@ -12140,13 +12746,13 @@ mod tests { baz |= sce_glbsfr_csr.ms(utra::sce_glbsfr::SFR_SUBEN_CR_SUBEN, 1); sce_glbsfr_csr.wfo(utra::sce_glbsfr::SFR_SUBEN_CR_SUBEN, baz); - let foo = sce_glbsfr_csr.r(utra::sce_glbsfr::SFR_AHBS); - sce_glbsfr_csr.wo(utra::sce_glbsfr::SFR_AHBS, foo); - let bar = sce_glbsfr_csr.rf(utra::sce_glbsfr::SFR_AHBS_CR_AHBSOPT); - sce_glbsfr_csr.rmwf(utra::sce_glbsfr::SFR_AHBS_CR_AHBSOPT, bar); - let mut baz = sce_glbsfr_csr.zf(utra::sce_glbsfr::SFR_AHBS_CR_AHBSOPT, bar); - baz |= sce_glbsfr_csr.ms(utra::sce_glbsfr::SFR_AHBS_CR_AHBSOPT, 1); - sce_glbsfr_csr.wfo(utra::sce_glbsfr::SFR_AHBS_CR_AHBSOPT, baz); + let foo = sce_glbsfr_csr.r(utra::sce_glbsfr::SFR_APBS); + sce_glbsfr_csr.wo(utra::sce_glbsfr::SFR_APBS, foo); + let bar = sce_glbsfr_csr.rf(utra::sce_glbsfr::SFR_APBS_CR_APBSOPT); + sce_glbsfr_csr.rmwf(utra::sce_glbsfr::SFR_APBS_CR_APBSOPT, bar); + let mut baz = sce_glbsfr_csr.zf(utra::sce_glbsfr::SFR_APBS_CR_APBSOPT, bar); + baz |= sce_glbsfr_csr.ms(utra::sce_glbsfr::SFR_APBS_CR_APBSOPT, 1); + sce_glbsfr_csr.wfo(utra::sce_glbsfr::SFR_APBS_CR_APBSOPT, baz); let foo = sce_glbsfr_csr.r(utra::sce_glbsfr::SFR_SRBUSY); sce_glbsfr_csr.wo(utra::sce_glbsfr::SFR_SRBUSY, foo); @@ -14736,6 +15342,924 @@ mod tests { pwm_csr.wfo(utra::pwm::REG_PREFD3_LSCLK_PREFD_3, baz); } + #[test] + #[ignore] + fn compile_check_sddc_csr() { + use super::*; + let mut sddc_csr = CSR::new(HW_SDDC_BASE as *mut u32); + + let foo = sddc_csr.r(utra::sddc::SFR_IO); + sddc_csr.wo(utra::sddc::SFR_IO, foo); + let bar = sddc_csr.rf(utra::sddc::SFR_IO_SFR_IO); + sddc_csr.rmwf(utra::sddc::SFR_IO_SFR_IO, bar); + let mut baz = sddc_csr.zf(utra::sddc::SFR_IO_SFR_IO, bar); + baz |= sddc_csr.ms(utra::sddc::SFR_IO_SFR_IO, 1); + sddc_csr.wfo(utra::sddc::SFR_IO_SFR_IO, baz); + + let foo = sddc_csr.r(utra::sddc::SFR_AR); + sddc_csr.wo(utra::sddc::SFR_AR, foo); + let bar = sddc_csr.rf(utra::sddc::SFR_AR_SFR_AR); + sddc_csr.rmwf(utra::sddc::SFR_AR_SFR_AR, bar); + let mut baz = sddc_csr.zf(utra::sddc::SFR_AR_SFR_AR, bar); + baz |= sddc_csr.ms(utra::sddc::SFR_AR_SFR_AR, 1); + sddc_csr.wfo(utra::sddc::SFR_AR_SFR_AR, baz); + + let foo = sddc_csr.r(utra::sddc::CR_OCR); + sddc_csr.wo(utra::sddc::CR_OCR, foo); + let bar = sddc_csr.rf(utra::sddc::CR_OCR_CR_OCR); + sddc_csr.rmwf(utra::sddc::CR_OCR_CR_OCR, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_OCR_CR_OCR, bar); + baz |= sddc_csr.ms(utra::sddc::CR_OCR_CR_OCR, 1); + sddc_csr.wfo(utra::sddc::CR_OCR_CR_OCR, baz); + + let foo = sddc_csr.r(utra::sddc::CR_RDFFTHRES); + sddc_csr.wo(utra::sddc::CR_RDFFTHRES, foo); + let bar = sddc_csr.rf(utra::sddc::CR_RDFFTHRES_CR_RDFFTHRES); + sddc_csr.rmwf(utra::sddc::CR_RDFFTHRES_CR_RDFFTHRES, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_RDFFTHRES_CR_RDFFTHRES, bar); + baz |= sddc_csr.ms(utra::sddc::CR_RDFFTHRES_CR_RDFFTHRES, 1); + sddc_csr.wfo(utra::sddc::CR_RDFFTHRES_CR_RDFFTHRES, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REV); + sddc_csr.wo(utra::sddc::CR_REV, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REV_CFG_REG_SD_SPEC_REVISION); + sddc_csr.rmwf(utra::sddc::CR_REV_CFG_REG_SD_SPEC_REVISION, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REV_CFG_REG_SD_SPEC_REVISION, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REV_CFG_REG_SD_SPEC_REVISION, 1); + sddc_csr.wfo(utra::sddc::CR_REV_CFG_REG_SD_SPEC_REVISION, baz); + let bar = sddc_csr.rf(utra::sddc::CR_REV_CFG_REG_CCCR_SDIO_REVISION); + sddc_csr.rmwf(utra::sddc::CR_REV_CFG_REG_CCCR_SDIO_REVISION, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REV_CFG_REG_CCCR_SDIO_REVISION, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REV_CFG_REG_CCCR_SDIO_REVISION, 1); + sddc_csr.wfo(utra::sddc::CR_REV_CFG_REG_CCCR_SDIO_REVISION, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BACSA); + sddc_csr.wo(utra::sddc::CR_BACSA, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BACSA_CFG_BASE_ADDR_CSA); + sddc_csr.rmwf(utra::sddc::CR_BACSA_CFG_BASE_ADDR_CSA, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BACSA_CFG_BASE_ADDR_CSA, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BACSA_CFG_BASE_ADDR_CSA, 1); + sddc_csr.wfo(utra::sddc::CR_BACSA_CFG_BASE_ADDR_CSA, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0); + sddc_csr.wo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0_CFG_BASE_ADDR_IO_FUNC0); + sddc_csr.rmwf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0_CFG_BASE_ADDR_IO_FUNC0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0_CFG_BASE_ADDR_IO_FUNC0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0_CFG_BASE_ADDR_IO_FUNC0, 1); + sddc_csr.wfo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0_CFG_BASE_ADDR_IO_FUNC0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1); + sddc_csr.wo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1_CFG_BASE_ADDR_IO_FUNC1); + sddc_csr.rmwf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1_CFG_BASE_ADDR_IO_FUNC1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1_CFG_BASE_ADDR_IO_FUNC1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1_CFG_BASE_ADDR_IO_FUNC1, 1); + sddc_csr.wfo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1_CFG_BASE_ADDR_IO_FUNC1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2); + sddc_csr.wo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2_CFG_BASE_ADDR_IO_FUNC2); + sddc_csr.rmwf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2_CFG_BASE_ADDR_IO_FUNC2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2_CFG_BASE_ADDR_IO_FUNC2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2_CFG_BASE_ADDR_IO_FUNC2, 1); + sddc_csr.wfo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2_CFG_BASE_ADDR_IO_FUNC2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3); + sddc_csr.wo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3_CFG_BASE_ADDR_IO_FUNC3); + sddc_csr.rmwf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3_CFG_BASE_ADDR_IO_FUNC3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3_CFG_BASE_ADDR_IO_FUNC3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3_CFG_BASE_ADDR_IO_FUNC3, 1); + sddc_csr.wfo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3_CFG_BASE_ADDR_IO_FUNC3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4); + sddc_csr.wo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4_CFG_BASE_ADDR_IO_FUNC4); + sddc_csr.rmwf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4_CFG_BASE_ADDR_IO_FUNC4, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4_CFG_BASE_ADDR_IO_FUNC4, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4_CFG_BASE_ADDR_IO_FUNC4, 1); + sddc_csr.wfo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4_CFG_BASE_ADDR_IO_FUNC4, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5); + sddc_csr.wo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5_CFG_BASE_ADDR_IO_FUNC5); + sddc_csr.rmwf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5_CFG_BASE_ADDR_IO_FUNC5, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5_CFG_BASE_ADDR_IO_FUNC5, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5_CFG_BASE_ADDR_IO_FUNC5, 1); + sddc_csr.wfo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5_CFG_BASE_ADDR_IO_FUNC5, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6); + sddc_csr.wo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6_CFG_BASE_ADDR_IO_FUNC6); + sddc_csr.rmwf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6_CFG_BASE_ADDR_IO_FUNC6, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6_CFG_BASE_ADDR_IO_FUNC6, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6_CFG_BASE_ADDR_IO_FUNC6, 1); + sddc_csr.wfo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6_CFG_BASE_ADDR_IO_FUNC6, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7); + sddc_csr.wo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7_CFG_BASE_ADDR_IO_FUNC7); + sddc_csr.rmwf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7_CFG_BASE_ADDR_IO_FUNC7, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7_CFG_BASE_ADDR_IO_FUNC7, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7_CFG_BASE_ADDR_IO_FUNC7, 1); + sddc_csr.wfo(utra::sddc::CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7_CFG_BASE_ADDR_IO_FUNC7, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0); + sddc_csr.wo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0_CFG_REG_FUNC_CIS_PTR0); + sddc_csr.rmwf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0_CFG_REG_FUNC_CIS_PTR0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0_CFG_REG_FUNC_CIS_PTR0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0_CFG_REG_FUNC_CIS_PTR0, 1); + sddc_csr.wfo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0_CFG_REG_FUNC_CIS_PTR0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1); + sddc_csr.wo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1_CFG_REG_FUNC_CIS_PTR1); + sddc_csr.rmwf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1_CFG_REG_FUNC_CIS_PTR1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1_CFG_REG_FUNC_CIS_PTR1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1_CFG_REG_FUNC_CIS_PTR1, 1); + sddc_csr.wfo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1_CFG_REG_FUNC_CIS_PTR1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2); + sddc_csr.wo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2_CFG_REG_FUNC_CIS_PTR2); + sddc_csr.rmwf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2_CFG_REG_FUNC_CIS_PTR2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2_CFG_REG_FUNC_CIS_PTR2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2_CFG_REG_FUNC_CIS_PTR2, 1); + sddc_csr.wfo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2_CFG_REG_FUNC_CIS_PTR2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3); + sddc_csr.wo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3_CFG_REG_FUNC_CIS_PTR3); + sddc_csr.rmwf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3_CFG_REG_FUNC_CIS_PTR3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3_CFG_REG_FUNC_CIS_PTR3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3_CFG_REG_FUNC_CIS_PTR3, 1); + sddc_csr.wfo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3_CFG_REG_FUNC_CIS_PTR3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4); + sddc_csr.wo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4_CFG_REG_FUNC_CIS_PTR4); + sddc_csr.rmwf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4_CFG_REG_FUNC_CIS_PTR4, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4_CFG_REG_FUNC_CIS_PTR4, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4_CFG_REG_FUNC_CIS_PTR4, 1); + sddc_csr.wfo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4_CFG_REG_FUNC_CIS_PTR4, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5); + sddc_csr.wo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5_CFG_REG_FUNC_CIS_PTR5); + sddc_csr.rmwf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5_CFG_REG_FUNC_CIS_PTR5, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5_CFG_REG_FUNC_CIS_PTR5, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5_CFG_REG_FUNC_CIS_PTR5, 1); + sddc_csr.wfo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5_CFG_REG_FUNC_CIS_PTR5, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6); + sddc_csr.wo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6_CFG_REG_FUNC_CIS_PTR6); + sddc_csr.rmwf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6_CFG_REG_FUNC_CIS_PTR6, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6_CFG_REG_FUNC_CIS_PTR6, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6_CFG_REG_FUNC_CIS_PTR6, 1); + sddc_csr.wfo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6_CFG_REG_FUNC_CIS_PTR6, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7); + sddc_csr.wo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7_CFG_REG_FUNC_CIS_PTR7); + sddc_csr.rmwf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7_CFG_REG_FUNC_CIS_PTR7, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7_CFG_REG_FUNC_CIS_PTR7, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7_CFG_REG_FUNC_CIS_PTR7, 1); + sddc_csr.wfo(utra::sddc::CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7_CFG_REG_FUNC_CIS_PTR7, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0); + sddc_csr.wo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0_CFG_REG_FUNC_EXT_STD_CODE0); + sddc_csr.rmwf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0_CFG_REG_FUNC_EXT_STD_CODE0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0_CFG_REG_FUNC_EXT_STD_CODE0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0_CFG_REG_FUNC_EXT_STD_CODE0, 1); + sddc_csr.wfo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0_CFG_REG_FUNC_EXT_STD_CODE0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1); + sddc_csr.wo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1_CFG_REG_FUNC_EXT_STD_CODE1); + sddc_csr.rmwf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1_CFG_REG_FUNC_EXT_STD_CODE1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1_CFG_REG_FUNC_EXT_STD_CODE1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1_CFG_REG_FUNC_EXT_STD_CODE1, 1); + sddc_csr.wfo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1_CFG_REG_FUNC_EXT_STD_CODE1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2); + sddc_csr.wo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2_CFG_REG_FUNC_EXT_STD_CODE2); + sddc_csr.rmwf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2_CFG_REG_FUNC_EXT_STD_CODE2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2_CFG_REG_FUNC_EXT_STD_CODE2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2_CFG_REG_FUNC_EXT_STD_CODE2, 1); + sddc_csr.wfo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2_CFG_REG_FUNC_EXT_STD_CODE2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3); + sddc_csr.wo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3_CFG_REG_FUNC_EXT_STD_CODE3); + sddc_csr.rmwf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3_CFG_REG_FUNC_EXT_STD_CODE3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3_CFG_REG_FUNC_EXT_STD_CODE3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3_CFG_REG_FUNC_EXT_STD_CODE3, 1); + sddc_csr.wfo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3_CFG_REG_FUNC_EXT_STD_CODE3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4); + sddc_csr.wo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4_CFG_REG_FUNC_EXT_STD_CODE4); + sddc_csr.rmwf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4_CFG_REG_FUNC_EXT_STD_CODE4, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4_CFG_REG_FUNC_EXT_STD_CODE4, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4_CFG_REG_FUNC_EXT_STD_CODE4, 1); + sddc_csr.wfo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4_CFG_REG_FUNC_EXT_STD_CODE4, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5); + sddc_csr.wo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5_CFG_REG_FUNC_EXT_STD_CODE5); + sddc_csr.rmwf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5_CFG_REG_FUNC_EXT_STD_CODE5, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5_CFG_REG_FUNC_EXT_STD_CODE5, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5_CFG_REG_FUNC_EXT_STD_CODE5, 1); + sddc_csr.wfo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5_CFG_REG_FUNC_EXT_STD_CODE5, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6); + sddc_csr.wo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6_CFG_REG_FUNC_EXT_STD_CODE6); + sddc_csr.rmwf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6_CFG_REG_FUNC_EXT_STD_CODE6, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6_CFG_REG_FUNC_EXT_STD_CODE6, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6_CFG_REG_FUNC_EXT_STD_CODE6, 1); + sddc_csr.wfo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6_CFG_REG_FUNC_EXT_STD_CODE6, baz); + + let foo = sddc_csr.r(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7); + sddc_csr.wo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7, foo); + let bar = sddc_csr.rf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7_CFG_REG_FUNC_EXT_STD_CODE7); + sddc_csr.rmwf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7_CFG_REG_FUNC_EXT_STD_CODE7, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7_CFG_REG_FUNC_EXT_STD_CODE7, bar); + baz |= sddc_csr.ms(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7_CFG_REG_FUNC_EXT_STD_CODE7, 1); + sddc_csr.wfo(utra::sddc::CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7_CFG_REG_FUNC_EXT_STD_CODE7, baz); + + let foo = sddc_csr.r(utra::sddc::CR_WRITE_PROTECT); + sddc_csr.wo(utra::sddc::CR_WRITE_PROTECT, foo); + let bar = sddc_csr.rf(utra::sddc::CR_WRITE_PROTECT_CR_WRITE_PROTECT); + sddc_csr.rmwf(utra::sddc::CR_WRITE_PROTECT_CR_WRITE_PROTECT, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_WRITE_PROTECT_CR_WRITE_PROTECT, bar); + baz |= sddc_csr.ms(utra::sddc::CR_WRITE_PROTECT_CR_WRITE_PROTECT, 1); + sddc_csr.wfo(utra::sddc::CR_WRITE_PROTECT_CR_WRITE_PROTECT, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_DSR); + sddc_csr.wo(utra::sddc::CR_REG_DSR, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_DSR_CR_REG_DSR); + sddc_csr.rmwf(utra::sddc::CR_REG_DSR_CR_REG_DSR, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_DSR_CR_REG_DSR, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_DSR_CR_REG_DSR, 1); + sddc_csr.wfo(utra::sddc::CR_REG_DSR_CR_REG_DSR, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_CID_CFG_REG_CID0); + sddc_csr.wo(utra::sddc::CR_REG_CID_CFG_REG_CID0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_CID_CFG_REG_CID0_CFG_REG_CID0); + sddc_csr.rmwf(utra::sddc::CR_REG_CID_CFG_REG_CID0_CFG_REG_CID0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_CID_CFG_REG_CID0_CFG_REG_CID0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_CID_CFG_REG_CID0_CFG_REG_CID0, 1); + sddc_csr.wfo(utra::sddc::CR_REG_CID_CFG_REG_CID0_CFG_REG_CID0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_CID_CFG_REG_CID1); + sddc_csr.wo(utra::sddc::CR_REG_CID_CFG_REG_CID1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_CID_CFG_REG_CID1_CFG_REG_CID1); + sddc_csr.rmwf(utra::sddc::CR_REG_CID_CFG_REG_CID1_CFG_REG_CID1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_CID_CFG_REG_CID1_CFG_REG_CID1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_CID_CFG_REG_CID1_CFG_REG_CID1, 1); + sddc_csr.wfo(utra::sddc::CR_REG_CID_CFG_REG_CID1_CFG_REG_CID1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_CID_CFG_REG_CID2); + sddc_csr.wo(utra::sddc::CR_REG_CID_CFG_REG_CID2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_CID_CFG_REG_CID2_CFG_REG_CID2); + sddc_csr.rmwf(utra::sddc::CR_REG_CID_CFG_REG_CID2_CFG_REG_CID2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_CID_CFG_REG_CID2_CFG_REG_CID2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_CID_CFG_REG_CID2_CFG_REG_CID2, 1); + sddc_csr.wfo(utra::sddc::CR_REG_CID_CFG_REG_CID2_CFG_REG_CID2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_CID_CFG_REG_CID3); + sddc_csr.wo(utra::sddc::CR_REG_CID_CFG_REG_CID3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_CID_CFG_REG_CID3_CFG_REG_CID3); + sddc_csr.rmwf(utra::sddc::CR_REG_CID_CFG_REG_CID3_CFG_REG_CID3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_CID_CFG_REG_CID3_CFG_REG_CID3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_CID_CFG_REG_CID3_CFG_REG_CID3, 1); + sddc_csr.wfo(utra::sddc::CR_REG_CID_CFG_REG_CID3_CFG_REG_CID3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_CSD_CFG_REG_CSD0); + sddc_csr.wo(utra::sddc::CR_REG_CSD_CFG_REG_CSD0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_CSD_CFG_REG_CSD0_CFG_REG_CSD0); + sddc_csr.rmwf(utra::sddc::CR_REG_CSD_CFG_REG_CSD0_CFG_REG_CSD0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_CSD_CFG_REG_CSD0_CFG_REG_CSD0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_CSD_CFG_REG_CSD0_CFG_REG_CSD0, 1); + sddc_csr.wfo(utra::sddc::CR_REG_CSD_CFG_REG_CSD0_CFG_REG_CSD0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_CSD_CFG_REG_CSD1); + sddc_csr.wo(utra::sddc::CR_REG_CSD_CFG_REG_CSD1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_CSD_CFG_REG_CSD1_CFG_REG_CSD1); + sddc_csr.rmwf(utra::sddc::CR_REG_CSD_CFG_REG_CSD1_CFG_REG_CSD1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_CSD_CFG_REG_CSD1_CFG_REG_CSD1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_CSD_CFG_REG_CSD1_CFG_REG_CSD1, 1); + sddc_csr.wfo(utra::sddc::CR_REG_CSD_CFG_REG_CSD1_CFG_REG_CSD1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_CSD_CFG_REG_CSD2); + sddc_csr.wo(utra::sddc::CR_REG_CSD_CFG_REG_CSD2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_CSD_CFG_REG_CSD2_CFG_REG_CSD2); + sddc_csr.rmwf(utra::sddc::CR_REG_CSD_CFG_REG_CSD2_CFG_REG_CSD2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_CSD_CFG_REG_CSD2_CFG_REG_CSD2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_CSD_CFG_REG_CSD2_CFG_REG_CSD2, 1); + sddc_csr.wfo(utra::sddc::CR_REG_CSD_CFG_REG_CSD2_CFG_REG_CSD2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_CSD_CFG_REG_CSD3); + sddc_csr.wo(utra::sddc::CR_REG_CSD_CFG_REG_CSD3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_CSD_CFG_REG_CSD3_CFG_REG_CSD3); + sddc_csr.rmwf(utra::sddc::CR_REG_CSD_CFG_REG_CSD3_CFG_REG_CSD3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_CSD_CFG_REG_CSD3_CFG_REG_CSD3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_CSD_CFG_REG_CSD3_CFG_REG_CSD3, 1); + sddc_csr.wfo(utra::sddc::CR_REG_CSD_CFG_REG_CSD3_CFG_REG_CSD3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SCR_CFG_REG_SCR0); + sddc_csr.wo(utra::sddc::CR_REG_SCR_CFG_REG_SCR0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SCR_CFG_REG_SCR0_CFG_REG_SCR0); + sddc_csr.rmwf(utra::sddc::CR_REG_SCR_CFG_REG_SCR0_CFG_REG_SCR0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SCR_CFG_REG_SCR0_CFG_REG_SCR0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SCR_CFG_REG_SCR0_CFG_REG_SCR0, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SCR_CFG_REG_SCR0_CFG_REG_SCR0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SCR_CFG_REG_SCR1); + sddc_csr.wo(utra::sddc::CR_REG_SCR_CFG_REG_SCR1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SCR_CFG_REG_SCR1_CFG_REG_SCR1); + sddc_csr.rmwf(utra::sddc::CR_REG_SCR_CFG_REG_SCR1_CFG_REG_SCR1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SCR_CFG_REG_SCR1_CFG_REG_SCR1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SCR_CFG_REG_SCR1_CFG_REG_SCR1, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SCR_CFG_REG_SCR1_CFG_REG_SCR1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS0); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS0_CFG_REG_SD_STATUS0); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS0_CFG_REG_SD_STATUS0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS0_CFG_REG_SD_STATUS0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS0_CFG_REG_SD_STATUS0, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS0_CFG_REG_SD_STATUS0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS1); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS1_CFG_REG_SD_STATUS1); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS1_CFG_REG_SD_STATUS1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS1_CFG_REG_SD_STATUS1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS1_CFG_REG_SD_STATUS1, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS1_CFG_REG_SD_STATUS1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS2); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS2_CFG_REG_SD_STATUS2); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS2_CFG_REG_SD_STATUS2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS2_CFG_REG_SD_STATUS2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS2_CFG_REG_SD_STATUS2, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS2_CFG_REG_SD_STATUS2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS3); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS3_CFG_REG_SD_STATUS3); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS3_CFG_REG_SD_STATUS3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS3_CFG_REG_SD_STATUS3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS3_CFG_REG_SD_STATUS3, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS3_CFG_REG_SD_STATUS3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS4); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS4, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS4_CFG_REG_SD_STATUS4); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS4_CFG_REG_SD_STATUS4, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS4_CFG_REG_SD_STATUS4, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS4_CFG_REG_SD_STATUS4, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS4_CFG_REG_SD_STATUS4, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS5); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS5, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS5_CFG_REG_SD_STATUS5); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS5_CFG_REG_SD_STATUS5, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS5_CFG_REG_SD_STATUS5, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS5_CFG_REG_SD_STATUS5, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS5_CFG_REG_SD_STATUS5, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS6); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS6, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS6_CFG_REG_SD_STATUS6); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS6_CFG_REG_SD_STATUS6, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS6_CFG_REG_SD_STATUS6, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS6_CFG_REG_SD_STATUS6, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS6_CFG_REG_SD_STATUS6, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS7); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS7, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS7_CFG_REG_SD_STATUS7); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS7_CFG_REG_SD_STATUS7, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS7_CFG_REG_SD_STATUS7, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS7_CFG_REG_SD_STATUS7, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS7_CFG_REG_SD_STATUS7, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS8); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS8, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS8_CFG_REG_SD_STATUS8); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS8_CFG_REG_SD_STATUS8, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS8_CFG_REG_SD_STATUS8, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS8_CFG_REG_SD_STATUS8, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS8_CFG_REG_SD_STATUS8, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS9); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS9, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS9_CFG_REG_SD_STATUS9); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS9_CFG_REG_SD_STATUS9, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS9_CFG_REG_SD_STATUS9, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS9_CFG_REG_SD_STATUS9, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS9_CFG_REG_SD_STATUS9, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS10); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS10, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS10_CFG_REG_SD_STATUS10); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS10_CFG_REG_SD_STATUS10, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS10_CFG_REG_SD_STATUS10, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS10_CFG_REG_SD_STATUS10, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS10_CFG_REG_SD_STATUS10, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS11); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS11, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS11_CFG_REG_SD_STATUS11); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS11_CFG_REG_SD_STATUS11, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS11_CFG_REG_SD_STATUS11, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS11_CFG_REG_SD_STATUS11, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS11_CFG_REG_SD_STATUS11, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS12); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS12, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS12_CFG_REG_SD_STATUS12); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS12_CFG_REG_SD_STATUS12, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS12_CFG_REG_SD_STATUS12, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS12_CFG_REG_SD_STATUS12, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS12_CFG_REG_SD_STATUS12, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS13); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS13, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS13_CFG_REG_SD_STATUS13); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS13_CFG_REG_SD_STATUS13, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS13_CFG_REG_SD_STATUS13, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS13_CFG_REG_SD_STATUS13, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS13_CFG_REG_SD_STATUS13, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS14); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS14, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS14_CFG_REG_SD_STATUS14); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS14_CFG_REG_SD_STATUS14, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS14_CFG_REG_SD_STATUS14, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS14_CFG_REG_SD_STATUS14, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS14_CFG_REG_SD_STATUS14, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS15); + sddc_csr.wo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS15, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS15_CFG_REG_SD_STATUS15); + sddc_csr.rmwf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS15_CFG_REG_SD_STATUS15, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS15_CFG_REG_SD_STATUS15, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS15_CFG_REG_SD_STATUS15, 1); + sddc_csr.wfo(utra::sddc::CR_REG_SD_STATUS_CFG_REG_SD_STATUS15_CFG_REG_SD_STATUS15, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0_CFG_BASE_ADDR_MEM_FUNC0); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0_CFG_BASE_ADDR_MEM_FUNC0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0_CFG_BASE_ADDR_MEM_FUNC0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0_CFG_BASE_ADDR_MEM_FUNC0, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0_CFG_BASE_ADDR_MEM_FUNC0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1_CFG_BASE_ADDR_MEM_FUNC1); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1_CFG_BASE_ADDR_MEM_FUNC1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1_CFG_BASE_ADDR_MEM_FUNC1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1_CFG_BASE_ADDR_MEM_FUNC1, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1_CFG_BASE_ADDR_MEM_FUNC1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2_CFG_BASE_ADDR_MEM_FUNC2); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2_CFG_BASE_ADDR_MEM_FUNC2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2_CFG_BASE_ADDR_MEM_FUNC2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2_CFG_BASE_ADDR_MEM_FUNC2, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2_CFG_BASE_ADDR_MEM_FUNC2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3_CFG_BASE_ADDR_MEM_FUNC3); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3_CFG_BASE_ADDR_MEM_FUNC3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3_CFG_BASE_ADDR_MEM_FUNC3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3_CFG_BASE_ADDR_MEM_FUNC3, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3_CFG_BASE_ADDR_MEM_FUNC3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4_CFG_BASE_ADDR_MEM_FUNC4); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4_CFG_BASE_ADDR_MEM_FUNC4, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4_CFG_BASE_ADDR_MEM_FUNC4, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4_CFG_BASE_ADDR_MEM_FUNC4, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4_CFG_BASE_ADDR_MEM_FUNC4, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5_CFG_BASE_ADDR_MEM_FUNC5); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5_CFG_BASE_ADDR_MEM_FUNC5, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5_CFG_BASE_ADDR_MEM_FUNC5, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5_CFG_BASE_ADDR_MEM_FUNC5, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5_CFG_BASE_ADDR_MEM_FUNC5, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6_CFG_BASE_ADDR_MEM_FUNC6); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6_CFG_BASE_ADDR_MEM_FUNC6, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6_CFG_BASE_ADDR_MEM_FUNC6, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6_CFG_BASE_ADDR_MEM_FUNC6, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6_CFG_BASE_ADDR_MEM_FUNC6, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7_CFG_BASE_ADDR_MEM_FUNC7); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7_CFG_BASE_ADDR_MEM_FUNC7, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7_CFG_BASE_ADDR_MEM_FUNC7, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7_CFG_BASE_ADDR_MEM_FUNC7, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7_CFG_BASE_ADDR_MEM_FUNC7, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8_CFG_BASE_ADDR_MEM_FUNC8); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8_CFG_BASE_ADDR_MEM_FUNC8, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8_CFG_BASE_ADDR_MEM_FUNC8, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8_CFG_BASE_ADDR_MEM_FUNC8, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8_CFG_BASE_ADDR_MEM_FUNC8, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9_CFG_BASE_ADDR_MEM_FUNC9); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9_CFG_BASE_ADDR_MEM_FUNC9, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9_CFG_BASE_ADDR_MEM_FUNC9, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9_CFG_BASE_ADDR_MEM_FUNC9, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9_CFG_BASE_ADDR_MEM_FUNC9, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10_CFG_BASE_ADDR_MEM_FUNC10); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10_CFG_BASE_ADDR_MEM_FUNC10, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10_CFG_BASE_ADDR_MEM_FUNC10, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10_CFG_BASE_ADDR_MEM_FUNC10, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10_CFG_BASE_ADDR_MEM_FUNC10, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11_CFG_BASE_ADDR_MEM_FUNC11); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11_CFG_BASE_ADDR_MEM_FUNC11, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11_CFG_BASE_ADDR_MEM_FUNC11, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11_CFG_BASE_ADDR_MEM_FUNC11, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11_CFG_BASE_ADDR_MEM_FUNC11, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12_CFG_BASE_ADDR_MEM_FUNC12); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12_CFG_BASE_ADDR_MEM_FUNC12, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12_CFG_BASE_ADDR_MEM_FUNC12, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12_CFG_BASE_ADDR_MEM_FUNC12, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12_CFG_BASE_ADDR_MEM_FUNC12, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13_CFG_BASE_ADDR_MEM_FUNC13); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13_CFG_BASE_ADDR_MEM_FUNC13, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13_CFG_BASE_ADDR_MEM_FUNC13, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13_CFG_BASE_ADDR_MEM_FUNC13, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13_CFG_BASE_ADDR_MEM_FUNC13, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14_CFG_BASE_ADDR_MEM_FUNC14); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14_CFG_BASE_ADDR_MEM_FUNC14, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14_CFG_BASE_ADDR_MEM_FUNC14, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14_CFG_BASE_ADDR_MEM_FUNC14, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14_CFG_BASE_ADDR_MEM_FUNC14, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15_CFG_BASE_ADDR_MEM_FUNC15); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15_CFG_BASE_ADDR_MEM_FUNC15, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15_CFG_BASE_ADDR_MEM_FUNC15, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15_CFG_BASE_ADDR_MEM_FUNC15, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15_CFG_BASE_ADDR_MEM_FUNC15, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16_CFG_BASE_ADDR_MEM_FUNC16); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16_CFG_BASE_ADDR_MEM_FUNC16, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16_CFG_BASE_ADDR_MEM_FUNC16, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16_CFG_BASE_ADDR_MEM_FUNC16, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16_CFG_BASE_ADDR_MEM_FUNC16, baz); + + let foo = sddc_csr.r(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17); + sddc_csr.wo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17, foo); + let bar = sddc_csr.rf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17_CFG_BASE_ADDR_MEM_FUNC17); + sddc_csr.rmwf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17_CFG_BASE_ADDR_MEM_FUNC17, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17_CFG_BASE_ADDR_MEM_FUNC17, bar); + baz |= sddc_csr.ms(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17_CFG_BASE_ADDR_MEM_FUNC17, 1); + sddc_csr.wfo(utra::sddc::CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17_CFG_BASE_ADDR_MEM_FUNC17, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0_CFG_REG_FUNC_MANUFACT_CODE0); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0_CFG_REG_FUNC_MANUFACT_CODE0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0_CFG_REG_FUNC_MANUFACT_CODE0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0_CFG_REG_FUNC_MANUFACT_CODE0, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0_CFG_REG_FUNC_MANUFACT_CODE0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1_CFG_REG_FUNC_MANUFACT_CODE1); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1_CFG_REG_FUNC_MANUFACT_CODE1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1_CFG_REG_FUNC_MANUFACT_CODE1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1_CFG_REG_FUNC_MANUFACT_CODE1, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1_CFG_REG_FUNC_MANUFACT_CODE1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2_CFG_REG_FUNC_MANUFACT_CODE2); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2_CFG_REG_FUNC_MANUFACT_CODE2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2_CFG_REG_FUNC_MANUFACT_CODE2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2_CFG_REG_FUNC_MANUFACT_CODE2, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2_CFG_REG_FUNC_MANUFACT_CODE2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3_CFG_REG_FUNC_MANUFACT_CODE3); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3_CFG_REG_FUNC_MANUFACT_CODE3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3_CFG_REG_FUNC_MANUFACT_CODE3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3_CFG_REG_FUNC_MANUFACT_CODE3, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3_CFG_REG_FUNC_MANUFACT_CODE3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4_CFG_REG_FUNC_MANUFACT_CODE4); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4_CFG_REG_FUNC_MANUFACT_CODE4, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4_CFG_REG_FUNC_MANUFACT_CODE4, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4_CFG_REG_FUNC_MANUFACT_CODE4, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4_CFG_REG_FUNC_MANUFACT_CODE4, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5_CFG_REG_FUNC_MANUFACT_CODE5); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5_CFG_REG_FUNC_MANUFACT_CODE5, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5_CFG_REG_FUNC_MANUFACT_CODE5, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5_CFG_REG_FUNC_MANUFACT_CODE5, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5_CFG_REG_FUNC_MANUFACT_CODE5, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6_CFG_REG_FUNC_MANUFACT_CODE6); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6_CFG_REG_FUNC_MANUFACT_CODE6, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6_CFG_REG_FUNC_MANUFACT_CODE6, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6_CFG_REG_FUNC_MANUFACT_CODE6, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6_CFG_REG_FUNC_MANUFACT_CODE6, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0_CFG_REG_FUNC_MANUFACT_INFO0); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0_CFG_REG_FUNC_MANUFACT_INFO0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0_CFG_REG_FUNC_MANUFACT_INFO0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0_CFG_REG_FUNC_MANUFACT_INFO0, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0_CFG_REG_FUNC_MANUFACT_INFO0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1_CFG_REG_FUNC_MANUFACT_INFO1); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1_CFG_REG_FUNC_MANUFACT_INFO1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1_CFG_REG_FUNC_MANUFACT_INFO1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1_CFG_REG_FUNC_MANUFACT_INFO1, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1_CFG_REG_FUNC_MANUFACT_INFO1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2_CFG_REG_FUNC_MANUFACT_INFO2); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2_CFG_REG_FUNC_MANUFACT_INFO2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2_CFG_REG_FUNC_MANUFACT_INFO2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2_CFG_REG_FUNC_MANUFACT_INFO2, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2_CFG_REG_FUNC_MANUFACT_INFO2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3_CFG_REG_FUNC_MANUFACT_INFO3); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3_CFG_REG_FUNC_MANUFACT_INFO3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3_CFG_REG_FUNC_MANUFACT_INFO3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3_CFG_REG_FUNC_MANUFACT_INFO3, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3_CFG_REG_FUNC_MANUFACT_INFO3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4_CFG_REG_FUNC_MANUFACT_INFO4); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4_CFG_REG_FUNC_MANUFACT_INFO4, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4_CFG_REG_FUNC_MANUFACT_INFO4, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4_CFG_REG_FUNC_MANUFACT_INFO4, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4_CFG_REG_FUNC_MANUFACT_INFO4, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5_CFG_REG_FUNC_MANUFACT_INFO5); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5_CFG_REG_FUNC_MANUFACT_INFO5, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5_CFG_REG_FUNC_MANUFACT_INFO5, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5_CFG_REG_FUNC_MANUFACT_INFO5, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5_CFG_REG_FUNC_MANUFACT_INFO5, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6_CFG_REG_FUNC_MANUFACT_INFO6); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6_CFG_REG_FUNC_MANUFACT_INFO6, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6_CFG_REG_FUNC_MANUFACT_INFO6, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6_CFG_REG_FUNC_MANUFACT_INFO6, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6_CFG_REG_FUNC_MANUFACT_INFO6, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0_CFG_REG_FUNC_INFO0); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0_CFG_REG_FUNC_INFO0, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0_CFG_REG_FUNC_INFO0, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0_CFG_REG_FUNC_INFO0, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0_CFG_REG_FUNC_INFO0, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1_CFG_REG_FUNC_INFO1); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1_CFG_REG_FUNC_INFO1, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1_CFG_REG_FUNC_INFO1, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1_CFG_REG_FUNC_INFO1, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1_CFG_REG_FUNC_INFO1, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2_CFG_REG_FUNC_INFO2); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2_CFG_REG_FUNC_INFO2, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2_CFG_REG_FUNC_INFO2, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2_CFG_REG_FUNC_INFO2, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2_CFG_REG_FUNC_INFO2, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3_CFG_REG_FUNC_INFO3); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3_CFG_REG_FUNC_INFO3, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3_CFG_REG_FUNC_INFO3, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3_CFG_REG_FUNC_INFO3, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3_CFG_REG_FUNC_INFO3, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4_CFG_REG_FUNC_INFO4); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4_CFG_REG_FUNC_INFO4, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4_CFG_REG_FUNC_INFO4, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4_CFG_REG_FUNC_INFO4, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4_CFG_REG_FUNC_INFO4, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5_CFG_REG_FUNC_INFO5); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5_CFG_REG_FUNC_INFO5, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5_CFG_REG_FUNC_INFO5, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5_CFG_REG_FUNC_INFO5, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5_CFG_REG_FUNC_INFO5, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6); + sddc_csr.wo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6_CFG_REG_FUNC_INFO6); + sddc_csr.rmwf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6_CFG_REG_FUNC_INFO6, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6_CFG_REG_FUNC_INFO6, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6_CFG_REG_FUNC_INFO6, 1); + sddc_csr.wfo(utra::sddc::CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6_CFG_REG_FUNC_INFO6, baz); + + let foo = sddc_csr.r(utra::sddc::CR_REG_UHS_1_SUPPORT); + sddc_csr.wo(utra::sddc::CR_REG_UHS_1_SUPPORT, foo); + let bar = sddc_csr.rf(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_MAX_CURRENT); + sddc_csr.rmwf(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_MAX_CURRENT, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_MAX_CURRENT, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_MAX_CURRENT, 1); + sddc_csr.wfo(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_MAX_CURRENT, baz); + let bar = sddc_csr.rf(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_DATA_STRC_VERSION); + sddc_csr.rmwf(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_DATA_STRC_VERSION, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_DATA_STRC_VERSION, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_DATA_STRC_VERSION, 1); + sddc_csr.wfo(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_DATA_STRC_VERSION, baz); + let bar = sddc_csr.rf(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_UHS_1_SUPPORT); + sddc_csr.rmwf(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_UHS_1_SUPPORT, bar); + let mut baz = sddc_csr.zf(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_UHS_1_SUPPORT, bar); + baz |= sddc_csr.ms(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_UHS_1_SUPPORT, 1); + sddc_csr.wfo(utra::sddc::CR_REG_UHS_1_SUPPORT_CFG_REG_UHS_1_SUPPORT, baz); + } + #[test] #[ignore] fn compile_check_coresub_sramtrm_csr() { @@ -15189,6 +16713,101 @@ mod tests { mbox_apb_csr.wfo(utra::mbox_apb::SFR_DONE_SFR_DONE, baz); } + #[test] + #[ignore] + fn compile_check_rrc_csr() { + use super::*; + let mut rrc_csr = CSR::new(HW_RRC_BASE as *mut u32); + + let foo = rrc_csr.r(utra::rrc::SFR_RRCCR); + rrc_csr.wo(utra::rrc::SFR_RRCCR, foo); + let bar = rrc_csr.rf(utra::rrc::SFR_RRCCR_SFR_RRCCR); + rrc_csr.rmwf(utra::rrc::SFR_RRCCR_SFR_RRCCR, bar); + let mut baz = rrc_csr.zf(utra::rrc::SFR_RRCCR_SFR_RRCCR, bar); + baz |= rrc_csr.ms(utra::rrc::SFR_RRCCR_SFR_RRCCR, 1); + rrc_csr.wfo(utra::rrc::SFR_RRCCR_SFR_RRCCR, baz); + + let foo = rrc_csr.r(utra::rrc::SFR_RRCFD); + rrc_csr.wo(utra::rrc::SFR_RRCFD, foo); + let bar = rrc_csr.rf(utra::rrc::SFR_RRCFD_SFR_RRCFD); + rrc_csr.rmwf(utra::rrc::SFR_RRCFD_SFR_RRCFD, bar); + let mut baz = rrc_csr.zf(utra::rrc::SFR_RRCFD_SFR_RRCFD, bar); + baz |= rrc_csr.ms(utra::rrc::SFR_RRCFD_SFR_RRCFD, 1); + rrc_csr.wfo(utra::rrc::SFR_RRCFD_SFR_RRCFD, baz); + + let foo = rrc_csr.r(utra::rrc::SFR_RRCSR); + rrc_csr.wo(utra::rrc::SFR_RRCSR, foo); + let bar = rrc_csr.rf(utra::rrc::SFR_RRCSR_SFR_RRCSR); + rrc_csr.rmwf(utra::rrc::SFR_RRCSR_SFR_RRCSR, bar); + let mut baz = rrc_csr.zf(utra::rrc::SFR_RRCSR_SFR_RRCSR, bar); + baz |= rrc_csr.ms(utra::rrc::SFR_RRCSR_SFR_RRCSR, 1); + rrc_csr.wfo(utra::rrc::SFR_RRCSR_SFR_RRCSR, baz); + + let foo = rrc_csr.r(utra::rrc::SFR_RRCFR); + rrc_csr.wo(utra::rrc::SFR_RRCFR, foo); + let bar = rrc_csr.rf(utra::rrc::SFR_RRCFR_SFR_RRCFR); + rrc_csr.rmwf(utra::rrc::SFR_RRCFR_SFR_RRCFR, bar); + let mut baz = rrc_csr.zf(utra::rrc::SFR_RRCFR_SFR_RRCFR, bar); + baz |= rrc_csr.ms(utra::rrc::SFR_RRCFR_SFR_RRCFR, 1); + rrc_csr.wfo(utra::rrc::SFR_RRCFR_SFR_RRCFR, baz); + + let foo = rrc_csr.r(utra::rrc::SFR_RRCAR); + rrc_csr.wo(utra::rrc::SFR_RRCAR, foo); + let bar = rrc_csr.rf(utra::rrc::SFR_RRCAR_SFR_RRCAR); + rrc_csr.rmwf(utra::rrc::SFR_RRCAR_SFR_RRCAR, bar); + let mut baz = rrc_csr.zf(utra::rrc::SFR_RRCAR_SFR_RRCAR, bar); + baz |= rrc_csr.ms(utra::rrc::SFR_RRCAR_SFR_RRCAR, 1); + rrc_csr.wfo(utra::rrc::SFR_RRCAR_SFR_RRCAR, baz); + + let foo = rrc_csr.r(utra::rrc::SFR_RRCSR_SET0); + rrc_csr.wo(utra::rrc::SFR_RRCSR_SET0, foo); + let bar = rrc_csr.rf(utra::rrc::SFR_RRCSR_SET0_TRC_SET_FAILURE); + rrc_csr.rmwf(utra::rrc::SFR_RRCSR_SET0_TRC_SET_FAILURE, bar); + let mut baz = rrc_csr.zf(utra::rrc::SFR_RRCSR_SET0_TRC_SET_FAILURE, bar); + baz |= rrc_csr.ms(utra::rrc::SFR_RRCSR_SET0_TRC_SET_FAILURE, 1); + rrc_csr.wfo(utra::rrc::SFR_RRCSR_SET0_TRC_SET_FAILURE, baz); + + let foo = rrc_csr.r(utra::rrc::SFR_RRCSR_SET1); + rrc_csr.wo(utra::rrc::SFR_RRCSR_SET1, foo); + let bar = rrc_csr.rf(utra::rrc::SFR_RRCSR_SET1_TRC_SET_FAILURE); + rrc_csr.rmwf(utra::rrc::SFR_RRCSR_SET1_TRC_SET_FAILURE, bar); + let mut baz = rrc_csr.zf(utra::rrc::SFR_RRCSR_SET1_TRC_SET_FAILURE, bar); + baz |= rrc_csr.ms(utra::rrc::SFR_RRCSR_SET1_TRC_SET_FAILURE, 1); + rrc_csr.wfo(utra::rrc::SFR_RRCSR_SET1_TRC_SET_FAILURE, baz); + + let foo = rrc_csr.r(utra::rrc::SFR_RRCSR_RST0); + rrc_csr.wo(utra::rrc::SFR_RRCSR_RST0, foo); + let bar = rrc_csr.rf(utra::rrc::SFR_RRCSR_RST0_TRC_RESET_FAILURE); + rrc_csr.rmwf(utra::rrc::SFR_RRCSR_RST0_TRC_RESET_FAILURE, bar); + let mut baz = rrc_csr.zf(utra::rrc::SFR_RRCSR_RST0_TRC_RESET_FAILURE, bar); + baz |= rrc_csr.ms(utra::rrc::SFR_RRCSR_RST0_TRC_RESET_FAILURE, 1); + rrc_csr.wfo(utra::rrc::SFR_RRCSR_RST0_TRC_RESET_FAILURE, baz); + + let foo = rrc_csr.r(utra::rrc::SFR_RRCSR_RST1); + rrc_csr.wo(utra::rrc::SFR_RRCSR_RST1, foo); + let bar = rrc_csr.rf(utra::rrc::SFR_RRCSR_RST1_TRC_RESET_FAILURE); + rrc_csr.rmwf(utra::rrc::SFR_RRCSR_RST1_TRC_RESET_FAILURE, bar); + let mut baz = rrc_csr.zf(utra::rrc::SFR_RRCSR_RST1_TRC_RESET_FAILURE, bar); + baz |= rrc_csr.ms(utra::rrc::SFR_RRCSR_RST1_TRC_RESET_FAILURE, 1); + rrc_csr.wfo(utra::rrc::SFR_RRCSR_RST1_TRC_RESET_FAILURE, baz); + + let foo = rrc_csr.r(utra::rrc::SFR_RRCSR_RD0); + rrc_csr.wo(utra::rrc::SFR_RRCSR_RD0, foo); + let bar = rrc_csr.rf(utra::rrc::SFR_RRCSR_RD0_TRC_FOURTH_READ_FAILURE); + rrc_csr.rmwf(utra::rrc::SFR_RRCSR_RD0_TRC_FOURTH_READ_FAILURE, bar); + let mut baz = rrc_csr.zf(utra::rrc::SFR_RRCSR_RD0_TRC_FOURTH_READ_FAILURE, bar); + baz |= rrc_csr.ms(utra::rrc::SFR_RRCSR_RD0_TRC_FOURTH_READ_FAILURE, 1); + rrc_csr.wfo(utra::rrc::SFR_RRCSR_RD0_TRC_FOURTH_READ_FAILURE, baz); + + let foo = rrc_csr.r(utra::rrc::SFR_RRCSR_RD1); + rrc_csr.wo(utra::rrc::SFR_RRCSR_RD1, foo); + let bar = rrc_csr.rf(utra::rrc::SFR_RRCSR_RD1_TRC_FOURTH_READ_FAILURE); + rrc_csr.rmwf(utra::rrc::SFR_RRCSR_RD1_TRC_FOURTH_READ_FAILURE, bar); + let mut baz = rrc_csr.zf(utra::rrc::SFR_RRCSR_RD1_TRC_FOURTH_READ_FAILURE, bar); + baz |= rrc_csr.ms(utra::rrc::SFR_RRCSR_RD1_TRC_FOURTH_READ_FAILURE, 1); + rrc_csr.wfo(utra::rrc::SFR_RRCSR_RD1_TRC_FOURTH_READ_FAILURE, baz); + } + #[test] #[ignore] fn compile_check_gluechain_csr() { @@ -15228,6 +16847,625 @@ mod tests { gluechain_csr.wfo(utra::gluechain::SFR_GCTEST_GLUETEST, baz); } + #[test] + #[ignore] + fn compile_check_mesh_csr() { + use super::*; + let mut mesh_csr = CSR::new(HW_MESH_BASE as *mut u32); + + let foo = mesh_csr.r(utra::mesh::SFR_MLDRV_CR_MLDRV0); + mesh_csr.wo(utra::mesh::SFR_MLDRV_CR_MLDRV0, foo); + let bar = mesh_csr.rf(utra::mesh::SFR_MLDRV_CR_MLDRV0_CR_MLDRV0); + mesh_csr.rmwf(utra::mesh::SFR_MLDRV_CR_MLDRV0_CR_MLDRV0, bar); + let mut baz = mesh_csr.zf(utra::mesh::SFR_MLDRV_CR_MLDRV0_CR_MLDRV0, bar); + baz |= mesh_csr.ms(utra::mesh::SFR_MLDRV_CR_MLDRV0_CR_MLDRV0, 1); + mesh_csr.wfo(utra::mesh::SFR_MLDRV_CR_MLDRV0_CR_MLDRV0, baz); + + let foo = mesh_csr.r(utra::mesh::SFR_MLIE_CR_MLIE0); + mesh_csr.wo(utra::mesh::SFR_MLIE_CR_MLIE0, foo); + let bar = mesh_csr.rf(utra::mesh::SFR_MLIE_CR_MLIE0_CR_MLIE0); + mesh_csr.rmwf(utra::mesh::SFR_MLIE_CR_MLIE0_CR_MLIE0, bar); + let mut baz = mesh_csr.zf(utra::mesh::SFR_MLIE_CR_MLIE0_CR_MLIE0, bar); + baz |= mesh_csr.ms(utra::mesh::SFR_MLIE_CR_MLIE0_CR_MLIE0, 1); + mesh_csr.wfo(utra::mesh::SFR_MLIE_CR_MLIE0_CR_MLIE0, baz); + + let foo = mesh_csr.r(utra::mesh::SFR_MLSR_SR_MLSR0); + mesh_csr.wo(utra::mesh::SFR_MLSR_SR_MLSR0, foo); + let bar = mesh_csr.rf(utra::mesh::SFR_MLSR_SR_MLSR0_SR_MLSR0); + mesh_csr.rmwf(utra::mesh::SFR_MLSR_SR_MLSR0_SR_MLSR0, bar); + let mut baz = mesh_csr.zf(utra::mesh::SFR_MLSR_SR_MLSR0_SR_MLSR0, bar); + baz |= mesh_csr.ms(utra::mesh::SFR_MLSR_SR_MLSR0_SR_MLSR0, 1); + mesh_csr.wfo(utra::mesh::SFR_MLSR_SR_MLSR0_SR_MLSR0, baz); + + let foo = mesh_csr.r(utra::mesh::SFR_MLSR_SR_MLSR1); + mesh_csr.wo(utra::mesh::SFR_MLSR_SR_MLSR1, foo); + let bar = mesh_csr.rf(utra::mesh::SFR_MLSR_SR_MLSR1_SR_MLSR1); + mesh_csr.rmwf(utra::mesh::SFR_MLSR_SR_MLSR1_SR_MLSR1, bar); + let mut baz = mesh_csr.zf(utra::mesh::SFR_MLSR_SR_MLSR1_SR_MLSR1, bar); + baz |= mesh_csr.ms(utra::mesh::SFR_MLSR_SR_MLSR1_SR_MLSR1, 1); + mesh_csr.wfo(utra::mesh::SFR_MLSR_SR_MLSR1_SR_MLSR1, baz); + + let foo = mesh_csr.r(utra::mesh::SFR_MLSR_SR_MLSR2); + mesh_csr.wo(utra::mesh::SFR_MLSR_SR_MLSR2, foo); + let bar = mesh_csr.rf(utra::mesh::SFR_MLSR_SR_MLSR2_SR_MLSR2); + mesh_csr.rmwf(utra::mesh::SFR_MLSR_SR_MLSR2_SR_MLSR2, bar); + let mut baz = mesh_csr.zf(utra::mesh::SFR_MLSR_SR_MLSR2_SR_MLSR2, bar); + baz |= mesh_csr.ms(utra::mesh::SFR_MLSR_SR_MLSR2_SR_MLSR2, 1); + mesh_csr.wfo(utra::mesh::SFR_MLSR_SR_MLSR2_SR_MLSR2, baz); + + let foo = mesh_csr.r(utra::mesh::SFR_MLSR_SR_MLSR3); + mesh_csr.wo(utra::mesh::SFR_MLSR_SR_MLSR3, foo); + let bar = mesh_csr.rf(utra::mesh::SFR_MLSR_SR_MLSR3_SR_MLSR3); + mesh_csr.rmwf(utra::mesh::SFR_MLSR_SR_MLSR3_SR_MLSR3, bar); + let mut baz = mesh_csr.zf(utra::mesh::SFR_MLSR_SR_MLSR3_SR_MLSR3, bar); + baz |= mesh_csr.ms(utra::mesh::SFR_MLSR_SR_MLSR3_SR_MLSR3, 1); + mesh_csr.wfo(utra::mesh::SFR_MLSR_SR_MLSR3_SR_MLSR3, baz); + + let foo = mesh_csr.r(utra::mesh::SFR_MLSR_SR_MLSR4); + mesh_csr.wo(utra::mesh::SFR_MLSR_SR_MLSR4, foo); + let bar = mesh_csr.rf(utra::mesh::SFR_MLSR_SR_MLSR4_SR_MLSR4); + mesh_csr.rmwf(utra::mesh::SFR_MLSR_SR_MLSR4_SR_MLSR4, bar); + let mut baz = mesh_csr.zf(utra::mesh::SFR_MLSR_SR_MLSR4_SR_MLSR4, bar); + baz |= mesh_csr.ms(utra::mesh::SFR_MLSR_SR_MLSR4_SR_MLSR4, 1); + mesh_csr.wfo(utra::mesh::SFR_MLSR_SR_MLSR4_SR_MLSR4, baz); + + let foo = mesh_csr.r(utra::mesh::SFR_MLSR_SR_MLSR5); + mesh_csr.wo(utra::mesh::SFR_MLSR_SR_MLSR5, foo); + let bar = mesh_csr.rf(utra::mesh::SFR_MLSR_SR_MLSR5_SR_MLSR5); + mesh_csr.rmwf(utra::mesh::SFR_MLSR_SR_MLSR5_SR_MLSR5, bar); + let mut baz = mesh_csr.zf(utra::mesh::SFR_MLSR_SR_MLSR5_SR_MLSR5, bar); + baz |= mesh_csr.ms(utra::mesh::SFR_MLSR_SR_MLSR5_SR_MLSR5, 1); + mesh_csr.wfo(utra::mesh::SFR_MLSR_SR_MLSR5_SR_MLSR5, baz); + + let foo = mesh_csr.r(utra::mesh::SFR_MLSR_SR_MLSR6); + mesh_csr.wo(utra::mesh::SFR_MLSR_SR_MLSR6, foo); + let bar = mesh_csr.rf(utra::mesh::SFR_MLSR_SR_MLSR6_SR_MLSR6); + mesh_csr.rmwf(utra::mesh::SFR_MLSR_SR_MLSR6_SR_MLSR6, bar); + let mut baz = mesh_csr.zf(utra::mesh::SFR_MLSR_SR_MLSR6_SR_MLSR6, bar); + baz |= mesh_csr.ms(utra::mesh::SFR_MLSR_SR_MLSR6_SR_MLSR6, 1); + mesh_csr.wfo(utra::mesh::SFR_MLSR_SR_MLSR6_SR_MLSR6, baz); + + let foo = mesh_csr.r(utra::mesh::SFR_MLSR_SR_MLSR7); + mesh_csr.wo(utra::mesh::SFR_MLSR_SR_MLSR7, foo); + let bar = mesh_csr.rf(utra::mesh::SFR_MLSR_SR_MLSR7_SR_MLSR7); + mesh_csr.rmwf(utra::mesh::SFR_MLSR_SR_MLSR7_SR_MLSR7, bar); + let mut baz = mesh_csr.zf(utra::mesh::SFR_MLSR_SR_MLSR7_SR_MLSR7, bar); + baz |= mesh_csr.ms(utra::mesh::SFR_MLSR_SR_MLSR7_SR_MLSR7, 1); + mesh_csr.wfo(utra::mesh::SFR_MLSR_SR_MLSR7_SR_MLSR7, baz); + } + + #[test] + #[ignore] + fn compile_check_sensorc_csr() { + use super::*; + let mut sensorc_csr = CSR::new(HW_SENSORC_BASE as *mut u32); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDMASK0); + sensorc_csr.wo(utra::sensorc::SFR_VDMASK0, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDMASK0_CR_VDMASK0); + sensorc_csr.rmwf(utra::sensorc::SFR_VDMASK0_CR_VDMASK0, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDMASK0_CR_VDMASK0, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDMASK0_CR_VDMASK0, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDMASK0_CR_VDMASK0, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDMASK1); + sensorc_csr.wo(utra::sensorc::SFR_VDMASK1, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDMASK1_CR_VDMASK1); + sensorc_csr.rmwf(utra::sensorc::SFR_VDMASK1_CR_VDMASK1, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDMASK1_CR_VDMASK1, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDMASK1_CR_VDMASK1, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDMASK1_CR_VDMASK1, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDSR); + sensorc_csr.wo(utra::sensorc::SFR_VDSR, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDSR_VDFLAG); + sensorc_csr.rmwf(utra::sensorc::SFR_VDSR_VDFLAG, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDSR_VDFLAG, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDSR_VDFLAG, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDSR_VDFLAG, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDFR); + sensorc_csr.wo(utra::sensorc::SFR_VDFR, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDFR_VDFLAG); + sensorc_csr.rmwf(utra::sensorc::SFR_VDFR_VDFLAG, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDFR_VDFLAG, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDFR_VDFLAG, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDFR_VDFLAG, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_LDMASK); + sensorc_csr.wo(utra::sensorc::SFR_LDMASK, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_LDMASK_CR_LDMASK); + sensorc_csr.rmwf(utra::sensorc::SFR_LDMASK_CR_LDMASK, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_LDMASK_CR_LDMASK, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_LDMASK_CR_LDMASK, 1); + sensorc_csr.wfo(utra::sensorc::SFR_LDMASK_CR_LDMASK, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_LDSR); + sensorc_csr.wo(utra::sensorc::SFR_LDSR, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_LDSR_SR_LDSR); + sensorc_csr.rmwf(utra::sensorc::SFR_LDSR_SR_LDSR, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_LDSR_SR_LDSR, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_LDSR_SR_LDSR, 1); + sensorc_csr.wfo(utra::sensorc::SFR_LDSR_SR_LDSR, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_LDCFG); + sensorc_csr.wo(utra::sensorc::SFR_LDCFG, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_LDCFG_SFR_LDCFG); + sensorc_csr.rmwf(utra::sensorc::SFR_LDCFG_SFR_LDCFG, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_LDCFG_SFR_LDCFG, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_LDCFG_SFR_LDCFG, 1); + sensorc_csr.wfo(utra::sensorc::SFR_LDCFG_SFR_LDCFG, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDCFG_CR_VDCFG0); + sensorc_csr.wo(utra::sensorc::SFR_VDCFG_CR_VDCFG0, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDCFG_CR_VDCFG0_CR_VDCFG0); + sensorc_csr.rmwf(utra::sensorc::SFR_VDCFG_CR_VDCFG0_CR_VDCFG0, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDCFG_CR_VDCFG0_CR_VDCFG0, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDCFG_CR_VDCFG0_CR_VDCFG0, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDCFG_CR_VDCFG0_CR_VDCFG0, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDCFG_CR_VDCFG1); + sensorc_csr.wo(utra::sensorc::SFR_VDCFG_CR_VDCFG1, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDCFG_CR_VDCFG1_CR_VDCFG1); + sensorc_csr.rmwf(utra::sensorc::SFR_VDCFG_CR_VDCFG1_CR_VDCFG1, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDCFG_CR_VDCFG1_CR_VDCFG1, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDCFG_CR_VDCFG1_CR_VDCFG1, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDCFG_CR_VDCFG1_CR_VDCFG1, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDCFG_CR_VDCFG2); + sensorc_csr.wo(utra::sensorc::SFR_VDCFG_CR_VDCFG2, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDCFG_CR_VDCFG2_CR_VDCFG2); + sensorc_csr.rmwf(utra::sensorc::SFR_VDCFG_CR_VDCFG2_CR_VDCFG2, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDCFG_CR_VDCFG2_CR_VDCFG2, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDCFG_CR_VDCFG2_CR_VDCFG2, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDCFG_CR_VDCFG2_CR_VDCFG2, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDCFG_CR_VDCFG3); + sensorc_csr.wo(utra::sensorc::SFR_VDCFG_CR_VDCFG3, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDCFG_CR_VDCFG3_CR_VDCFG3); + sensorc_csr.rmwf(utra::sensorc::SFR_VDCFG_CR_VDCFG3_CR_VDCFG3, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDCFG_CR_VDCFG3_CR_VDCFG3, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDCFG_CR_VDCFG3_CR_VDCFG3, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDCFG_CR_VDCFG3_CR_VDCFG3, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDCFG_CR_VDCFG4); + sensorc_csr.wo(utra::sensorc::SFR_VDCFG_CR_VDCFG4, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDCFG_CR_VDCFG4_CR_VDCFG4); + sensorc_csr.rmwf(utra::sensorc::SFR_VDCFG_CR_VDCFG4_CR_VDCFG4, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDCFG_CR_VDCFG4_CR_VDCFG4, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDCFG_CR_VDCFG4_CR_VDCFG4, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDCFG_CR_VDCFG4_CR_VDCFG4, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDCFG_CR_VDCFG5); + sensorc_csr.wo(utra::sensorc::SFR_VDCFG_CR_VDCFG5, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDCFG_CR_VDCFG5_CR_VDCFG5); + sensorc_csr.rmwf(utra::sensorc::SFR_VDCFG_CR_VDCFG5_CR_VDCFG5, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDCFG_CR_VDCFG5_CR_VDCFG5, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDCFG_CR_VDCFG5_CR_VDCFG5, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDCFG_CR_VDCFG5_CR_VDCFG5, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDCFG_CR_VDCFG6); + sensorc_csr.wo(utra::sensorc::SFR_VDCFG_CR_VDCFG6, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDCFG_CR_VDCFG6_CR_VDCFG6); + sensorc_csr.rmwf(utra::sensorc::SFR_VDCFG_CR_VDCFG6_CR_VDCFG6, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDCFG_CR_VDCFG6_CR_VDCFG6, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDCFG_CR_VDCFG6_CR_VDCFG6, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDCFG_CR_VDCFG6_CR_VDCFG6, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDCFG_CR_VDCFG7); + sensorc_csr.wo(utra::sensorc::SFR_VDCFG_CR_VDCFG7, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDCFG_CR_VDCFG7_CR_VDCFG7); + sensorc_csr.rmwf(utra::sensorc::SFR_VDCFG_CR_VDCFG7_CR_VDCFG7, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDCFG_CR_VDCFG7_CR_VDCFG7, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDCFG_CR_VDCFG7_CR_VDCFG7, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDCFG_CR_VDCFG7_CR_VDCFG7, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDIP_ENA); + sensorc_csr.wo(utra::sensorc::SFR_VDIP_ENA, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDIP_ENA_VDENA); + sensorc_csr.rmwf(utra::sensorc::SFR_VDIP_ENA_VDENA, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDIP_ENA_VDENA, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDIP_ENA_VDENA, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDIP_ENA_VDENA, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_VDIP_TEST); + sensorc_csr.wo(utra::sensorc::SFR_VDIP_TEST, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_VDIP_TEST_VDTST); + sensorc_csr.rmwf(utra::sensorc::SFR_VDIP_TEST_VDTST, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDIP_TEST_VDTST, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_VDIP_TEST_VDTST, 1); + sensorc_csr.wfo(utra::sensorc::SFR_VDIP_TEST_VDTST, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_LDIP_TEST); + sensorc_csr.wo(utra::sensorc::SFR_LDIP_TEST, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_LDIP_TEST_LDTST); + sensorc_csr.rmwf(utra::sensorc::SFR_LDIP_TEST_LDTST, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_LDIP_TEST_LDTST, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_LDIP_TEST_LDTST, 1); + sensorc_csr.wfo(utra::sensorc::SFR_LDIP_TEST_LDTST, baz); + + let foo = sensorc_csr.r(utra::sensorc::SFR_LDIP_FD); + sensorc_csr.wo(utra::sensorc::SFR_LDIP_FD, foo); + let bar = sensorc_csr.rf(utra::sensorc::SFR_LDIP_FD_SFR_LDIP_FD); + sensorc_csr.rmwf(utra::sensorc::SFR_LDIP_FD_SFR_LDIP_FD, bar); + let mut baz = sensorc_csr.zf(utra::sensorc::SFR_LDIP_FD_SFR_LDIP_FD, bar); + baz |= sensorc_csr.ms(utra::sensorc::SFR_LDIP_FD_SFR_LDIP_FD, 1); + sensorc_csr.wfo(utra::sensorc::SFR_LDIP_FD_SFR_LDIP_FD, baz); + } + + #[test] + #[ignore] + fn compile_check_aobureg_csr() { + use super::*; + let mut aobureg_csr = CSR::new(HW_AOBUREG_BASE as *mut u32); + + let foo = aobureg_csr.r(utra::aobureg::SFR_BUREG_CR_BUREGS0); + aobureg_csr.wo(utra::aobureg::SFR_BUREG_CR_BUREGS0, foo); + let bar = aobureg_csr.rf(utra::aobureg::SFR_BUREG_CR_BUREGS0_CR_BUREGS0); + aobureg_csr.rmwf(utra::aobureg::SFR_BUREG_CR_BUREGS0_CR_BUREGS0, bar); + let mut baz = aobureg_csr.zf(utra::aobureg::SFR_BUREG_CR_BUREGS0_CR_BUREGS0, bar); + baz |= aobureg_csr.ms(utra::aobureg::SFR_BUREG_CR_BUREGS0_CR_BUREGS0, 1); + aobureg_csr.wfo(utra::aobureg::SFR_BUREG_CR_BUREGS0_CR_BUREGS0, baz); + + let foo = aobureg_csr.r(utra::aobureg::SFR_BUREG_CR_BUREGS1); + aobureg_csr.wo(utra::aobureg::SFR_BUREG_CR_BUREGS1, foo); + let bar = aobureg_csr.rf(utra::aobureg::SFR_BUREG_CR_BUREGS1_CR_BUREGS1); + aobureg_csr.rmwf(utra::aobureg::SFR_BUREG_CR_BUREGS1_CR_BUREGS1, bar); + let mut baz = aobureg_csr.zf(utra::aobureg::SFR_BUREG_CR_BUREGS1_CR_BUREGS1, bar); + baz |= aobureg_csr.ms(utra::aobureg::SFR_BUREG_CR_BUREGS1_CR_BUREGS1, 1); + aobureg_csr.wfo(utra::aobureg::SFR_BUREG_CR_BUREGS1_CR_BUREGS1, baz); + + let foo = aobureg_csr.r(utra::aobureg::SFR_BUREG_CR_BUREGS2); + aobureg_csr.wo(utra::aobureg::SFR_BUREG_CR_BUREGS2, foo); + let bar = aobureg_csr.rf(utra::aobureg::SFR_BUREG_CR_BUREGS2_CR_BUREGS2); + aobureg_csr.rmwf(utra::aobureg::SFR_BUREG_CR_BUREGS2_CR_BUREGS2, bar); + let mut baz = aobureg_csr.zf(utra::aobureg::SFR_BUREG_CR_BUREGS2_CR_BUREGS2, bar); + baz |= aobureg_csr.ms(utra::aobureg::SFR_BUREG_CR_BUREGS2_CR_BUREGS2, 1); + aobureg_csr.wfo(utra::aobureg::SFR_BUREG_CR_BUREGS2_CR_BUREGS2, baz); + + let foo = aobureg_csr.r(utra::aobureg::SFR_BUREG_CR_BUREGS3); + aobureg_csr.wo(utra::aobureg::SFR_BUREG_CR_BUREGS3, foo); + let bar = aobureg_csr.rf(utra::aobureg::SFR_BUREG_CR_BUREGS3_CR_BUREGS3); + aobureg_csr.rmwf(utra::aobureg::SFR_BUREG_CR_BUREGS3_CR_BUREGS3, bar); + let mut baz = aobureg_csr.zf(utra::aobureg::SFR_BUREG_CR_BUREGS3_CR_BUREGS3, bar); + baz |= aobureg_csr.ms(utra::aobureg::SFR_BUREG_CR_BUREGS3_CR_BUREGS3, 1); + aobureg_csr.wfo(utra::aobureg::SFR_BUREG_CR_BUREGS3_CR_BUREGS3, baz); + + let foo = aobureg_csr.r(utra::aobureg::SFR_BUREG_CR_BUREGS4); + aobureg_csr.wo(utra::aobureg::SFR_BUREG_CR_BUREGS4, foo); + let bar = aobureg_csr.rf(utra::aobureg::SFR_BUREG_CR_BUREGS4_CR_BUREGS4); + aobureg_csr.rmwf(utra::aobureg::SFR_BUREG_CR_BUREGS4_CR_BUREGS4, bar); + let mut baz = aobureg_csr.zf(utra::aobureg::SFR_BUREG_CR_BUREGS4_CR_BUREGS4, bar); + baz |= aobureg_csr.ms(utra::aobureg::SFR_BUREG_CR_BUREGS4_CR_BUREGS4, 1); + aobureg_csr.wfo(utra::aobureg::SFR_BUREG_CR_BUREGS4_CR_BUREGS4, baz); + + let foo = aobureg_csr.r(utra::aobureg::SFR_BUREG_CR_BUREGS5); + aobureg_csr.wo(utra::aobureg::SFR_BUREG_CR_BUREGS5, foo); + let bar = aobureg_csr.rf(utra::aobureg::SFR_BUREG_CR_BUREGS5_CR_BUREGS5); + aobureg_csr.rmwf(utra::aobureg::SFR_BUREG_CR_BUREGS5_CR_BUREGS5, bar); + let mut baz = aobureg_csr.zf(utra::aobureg::SFR_BUREG_CR_BUREGS5_CR_BUREGS5, bar); + baz |= aobureg_csr.ms(utra::aobureg::SFR_BUREG_CR_BUREGS5_CR_BUREGS5, 1); + aobureg_csr.wfo(utra::aobureg::SFR_BUREG_CR_BUREGS5_CR_BUREGS5, baz); + + let foo = aobureg_csr.r(utra::aobureg::SFR_BUREG_CR_BUREGS6); + aobureg_csr.wo(utra::aobureg::SFR_BUREG_CR_BUREGS6, foo); + let bar = aobureg_csr.rf(utra::aobureg::SFR_BUREG_CR_BUREGS6_CR_BUREGS6); + aobureg_csr.rmwf(utra::aobureg::SFR_BUREG_CR_BUREGS6_CR_BUREGS6, bar); + let mut baz = aobureg_csr.zf(utra::aobureg::SFR_BUREG_CR_BUREGS6_CR_BUREGS6, bar); + baz |= aobureg_csr.ms(utra::aobureg::SFR_BUREG_CR_BUREGS6_CR_BUREGS6, 1); + aobureg_csr.wfo(utra::aobureg::SFR_BUREG_CR_BUREGS6_CR_BUREGS6, baz); + + let foo = aobureg_csr.r(utra::aobureg::SFR_BUREG_CR_BUREGS7); + aobureg_csr.wo(utra::aobureg::SFR_BUREG_CR_BUREGS7, foo); + let bar = aobureg_csr.rf(utra::aobureg::SFR_BUREG_CR_BUREGS7_CR_BUREGS7); + aobureg_csr.rmwf(utra::aobureg::SFR_BUREG_CR_BUREGS7_CR_BUREGS7, bar); + let mut baz = aobureg_csr.zf(utra::aobureg::SFR_BUREG_CR_BUREGS7_CR_BUREGS7, bar); + baz |= aobureg_csr.ms(utra::aobureg::SFR_BUREG_CR_BUREGS7_CR_BUREGS7, 1); + aobureg_csr.wfo(utra::aobureg::SFR_BUREG_CR_BUREGS7_CR_BUREGS7, baz); + } + + #[test] + #[ignore] + fn compile_check_ao_sysctrl_csr() { + use super::*; + let mut ao_sysctrl_csr = CSR::new(HW_AO_SYSCTRL_BASE as *mut u32); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::CR_CLK32KSEL); + ao_sysctrl_csr.wo(utra::ao_sysctrl::CR_CLK32KSEL, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::CR_CLK32KSEL_CR_CLK32KSEL); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::CR_CLK32KSEL_CR_CLK32KSEL, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::CR_CLK32KSEL_CR_CLK32KSEL, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::CR_CLK32KSEL_CR_CLK32KSEL, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::CR_CLK32KSEL_CR_CLK32KSEL, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::CR_CLK1HZFD); + ao_sysctrl_csr.wo(utra::ao_sysctrl::CR_CLK1HZFD, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::CR_CLK1HZFD_CR_CLK1HZFD); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::CR_CLK1HZFD_CR_CLK1HZFD, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::CR_CLK1HZFD_CR_CLK1HZFD, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::CR_CLK1HZFD_CR_CLK1HZFD, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::CR_CLK1HZFD_CR_CLK1HZFD, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::CR_WKUPMASK); + ao_sysctrl_csr.wo(utra::ao_sysctrl::CR_WKUPMASK, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::CR_WKUPMASK_CR_WKUPMASK); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::CR_WKUPMASK_CR_WKUPMASK, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::CR_WKUPMASK_CR_WKUPMASK, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::CR_WKUPMASK_CR_WKUPMASK, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::CR_WKUPMASK_CR_WKUPMASK, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::CR_RSTCRMASK); + ao_sysctrl_csr.wo(utra::ao_sysctrl::CR_RSTCRMASK, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::CR_RSTCRMASK_CR_RSTCRMASK); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::CR_RSTCRMASK_CR_RSTCRMASK, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::CR_RSTCRMASK_CR_RSTCRMASK, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::CR_RSTCRMASK_CR_RSTCRMASK, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::CR_RSTCRMASK_CR_RSTCRMASK, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_PMUCR); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_PMUCR, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_PMUCR_SFRPMUCR); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_PMUCR_SFRPMUCR, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_PMUCR_SFRPMUCR, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_PMUCR_SFRPMUCR, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_PMUCR_SFRPMUCR, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_PMUCRLP); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_PMUCRLP, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_PMUCRLP_SFRPMUCRLP); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_PMUCRLP_SFRPMUCRLP, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_PMUCRLP_SFRPMUCRLP, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_PMUCRLP_SFRPMUCRLP, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_PMUCRLP_SFRPMUCRLP, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_PMUCRPD); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_PMUCRPD, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_PMUCRPD_SFRPMUCRPD); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_PMUCRPD_SFRPMUCRPD, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_PMUCRPD_SFRPMUCRPD, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_PMUCRPD_SFRPMUCRPD, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_PMUCRPD_SFRPMUCRPD, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_PMUDFT); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_PMUDFT, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_PMUDFT_SFRPMUDFT); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_PMUDFT_SFRPMUDFT, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_PMUDFT_SFRPMUDFT, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_PMUDFT_SFRPMUDFT, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_PMUDFT_SFRPMUDFT, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_PMUTRM0); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_PMUTRM0, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_PMUTRM0_SFRPMUTRM); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_PMUTRM0_SFRPMUTRM, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_PMUTRM0_SFRPMUTRM, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_PMUTRM0_SFRPMUTRM, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_PMUTRM0_SFRPMUTRM, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_PMUTRM1); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_PMUTRM1, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_PMUTRM1_SFRPMUTRM); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_PMUTRM1_SFRPMUTRM, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_PMUTRM1_SFRPMUTRM, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_PMUTRM1_SFRPMUTRM, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_PMUTRM1_SFRPMUTRM, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_PMUTRMLP0); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_PMUTRMLP0, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_PMUTRMLP0_SFRPMUTRMLP); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_PMUTRMLP0_SFRPMUTRMLP, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_PMUTRMLP0_SFRPMUTRMLP, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_PMUTRMLP0_SFRPMUTRMLP, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_PMUTRMLP0_SFRPMUTRMLP, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_PMUTRMLP1); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_PMUTRMLP1, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_PMUTRMLP1_SFRPMUTRMLP); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_PMUTRMLP1_SFRPMUTRMLP, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_PMUTRMLP1_SFRPMUTRMLP, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_PMUTRMLP1_SFRPMUTRMLP, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_PMUTRMLP1_SFRPMUTRMLP, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_OSCCR); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_OSCCR, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_OSCCR_SFROSCCR); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_OSCCR_SFROSCCR, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_OSCCR_SFROSCCR, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_OSCCR_SFROSCCR, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_OSCCR_SFROSCCR, baz); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_OSCCR_SFROSCTRM); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_OSCCR_SFROSCTRM, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_OSCCR_SFROSCTRM, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_OSCCR_SFROSCTRM, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_OSCCR_SFROSCTRM, baz); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_OSCCR_SFROSCCRLP); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_OSCCR_SFROSCCRLP, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_OSCCR_SFROSCCRLP, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_OSCCR_SFROSCCRLP, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_OSCCR_SFROSCCRLP, baz); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_OSCCR_SFROSCTRMLP); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_OSCCR_SFROSCTRMLP, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_OSCCR_SFROSCTRMLP, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_OSCCR_SFROSCTRMLP, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_OSCCR_SFROSCTRMLP, baz); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_OSCCR_SFROSCCRPD); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_OSCCR_SFROSCCRPD, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_OSCCR_SFROSCCRPD, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_OSCCR_SFROSCCRPD, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_OSCCR_SFROSCCRPD, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_PMUSR); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_PMUSR, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_PMUSR_SFR_PMUSR); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_PMUSR_SFR_PMUSR, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_PMUSR_SFR_PMUSR, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_PMUSR_SFR_PMUSR, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_PMUSR_SFR_PMUSR, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_PMUFR); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_PMUFR, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_PMUFR_SFR_PMUFR); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_PMUFR_SFR_PMUFR, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_PMUFR_SFR_PMUFR, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_PMUFR_SFR_PMUFR, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_PMUFR_SFR_PMUFR, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_AOFR); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_AOFR, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_AOFR_SFR_AOFR); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_AOFR_SFR_AOFR, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_AOFR_SFR_AOFR, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_AOFR_SFR_AOFR, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_AOFR_SFR_AOFR, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_PMUPDAR); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_PMUPDAR, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_PMUPDAR_SFR_PMUPDAR); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_PMUPDAR_SFR_PMUPDAR, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_PMUPDAR_SFR_PMUPDAR, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_PMUPDAR_SFR_PMUPDAR, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_PMUPDAR_SFR_PMUPDAR, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::AR_AOPERI_CLRINT); + ao_sysctrl_csr.wo(utra::ao_sysctrl::AR_AOPERI_CLRINT, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::AR_AOPERI_CLRINT_AR_AOPERI_CLRINT); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::AR_AOPERI_CLRINT_AR_AOPERI_CLRINT, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::AR_AOPERI_CLRINT_AR_AOPERI_CLRINT, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::AR_AOPERI_CLRINT_AR_AOPERI_CLRINT, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::AR_AOPERI_CLRINT_AR_AOPERI_CLRINT, baz); + + let foo = ao_sysctrl_csr.r(utra::ao_sysctrl::SFR_IOX); + ao_sysctrl_csr.wo(utra::ao_sysctrl::SFR_IOX, foo); + let bar = ao_sysctrl_csr.rf(utra::ao_sysctrl::SFR_IOX_SFR_IOX); + ao_sysctrl_csr.rmwf(utra::ao_sysctrl::SFR_IOX_SFR_IOX, bar); + let mut baz = ao_sysctrl_csr.zf(utra::ao_sysctrl::SFR_IOX_SFR_IOX, bar); + baz |= ao_sysctrl_csr.ms(utra::ao_sysctrl::SFR_IOX_SFR_IOX, 1); + ao_sysctrl_csr.wfo(utra::ao_sysctrl::SFR_IOX_SFR_IOX, baz); + } + + #[test] + #[ignore] + fn compile_check_dkpc_csr() { + use super::*; + let mut dkpc_csr = CSR::new(HW_DKPC_BASE as *mut u32); + + let foo = dkpc_csr.r(utra::dkpc::SFR_CFG0); + dkpc_csr.wo(utra::dkpc::SFR_CFG0, foo); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG0_KPOPO0); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG0_KPOPO0, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG0_KPOPO0, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG0_KPOPO0, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG0_KPOPO0, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG0_KPOPO1); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG0_KPOPO1, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG0_KPOPO1, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG0_KPOPO1, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG0_KPOPO1, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG0_KPOOE0); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG0_KPOOE0, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG0_KPOOE0, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG0_KPOOE0, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG0_KPOOE0, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG0_KPOOE1); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG0_KPOOE1, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG0_KPOOE1, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG0_KPOOE1, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG0_KPOOE1, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG0_DKPCEN); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG0_DKPCEN, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG0_DKPCEN, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG0_DKPCEN, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG0_DKPCEN, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG0_AUTOSLEEPEN); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG0_AUTOSLEEPEN, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG0_AUTOSLEEPEN, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG0_AUTOSLEEPEN, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG0_AUTOSLEEPEN, baz); + + let foo = dkpc_csr.r(utra::dkpc::SFR_CFG1); + dkpc_csr.wo(utra::dkpc::SFR_CFG1, foo); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG1_CFG_STEP); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG1_CFG_STEP, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG1_CFG_STEP, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG1_CFG_STEP, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG1_CFG_STEP, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG1_CFG_FILTER); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG1_CFG_FILTER, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG1_CFG_FILTER, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG1_CFG_FILTER, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG1_CFG_FILTER, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG1_CFG_CNT1MS); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG1_CFG_CNT1MS, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG1_CFG_CNT1MS, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG1_CFG_CNT1MS, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG1_CFG_CNT1MS, baz); + + let foo = dkpc_csr.r(utra::dkpc::SFR_CFG2); + dkpc_csr.wo(utra::dkpc::SFR_CFG2, foo); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG2_CFG_CNT); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG2_CFG_CNT, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG2_CFG_CNT, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG2_CFG_CNT, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG2_CFG_CNT, baz); + + let foo = dkpc_csr.r(utra::dkpc::SFR_CFG3); + dkpc_csr.wo(utra::dkpc::SFR_CFG3, foo); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG3_KPNODERISEEN); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG3_KPNODERISEEN, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG3_KPNODERISEEN, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG3_KPNODERISEEN, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG3_KPNODERISEEN, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG3_KPNODEFALLEN); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG3_KPNODEFALLEN, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG3_KPNODEFALLEN, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG3_KPNODEFALLEN, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG3_KPNODEFALLEN, baz); + + let foo = dkpc_csr.r(utra::dkpc::SFR_SR0); + dkpc_csr.wo(utra::dkpc::SFR_SR0, foo); + let bar = dkpc_csr.rf(utra::dkpc::SFR_SR0_KPNODEREG); + dkpc_csr.rmwf(utra::dkpc::SFR_SR0_KPNODEREG, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_SR0_KPNODEREG, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_SR0_KPNODEREG, 1); + dkpc_csr.wfo(utra::dkpc::SFR_SR0_KPNODEREG, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_SR0_KPI0_PI); + dkpc_csr.rmwf(utra::dkpc::SFR_SR0_KPI0_PI, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_SR0_KPI0_PI, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_SR0_KPI0_PI, 1); + dkpc_csr.wfo(utra::dkpc::SFR_SR0_KPI0_PI, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_SR0_KPI1_PI); + dkpc_csr.rmwf(utra::dkpc::SFR_SR0_KPI1_PI, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_SR0_KPI1_PI, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_SR0_KPI1_PI, 1); + dkpc_csr.wfo(utra::dkpc::SFR_SR0_KPI1_PI, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_SR0_KPI2_PI); + dkpc_csr.rmwf(utra::dkpc::SFR_SR0_KPI2_PI, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_SR0_KPI2_PI, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_SR0_KPI2_PI, 1); + dkpc_csr.wfo(utra::dkpc::SFR_SR0_KPI2_PI, baz); + let bar = dkpc_csr.rf(utra::dkpc::SFR_SR0_KPI3_PI); + dkpc_csr.rmwf(utra::dkpc::SFR_SR0_KPI3_PI, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_SR0_KPI3_PI, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_SR0_KPI3_PI, 1); + dkpc_csr.wfo(utra::dkpc::SFR_SR0_KPI3_PI, baz); + + let foo = dkpc_csr.r(utra::dkpc::SFR_SR1); + dkpc_csr.wo(utra::dkpc::SFR_SR1, foo); + let bar = dkpc_csr.rf(utra::dkpc::SFR_SR1_SFR_SR1); + dkpc_csr.rmwf(utra::dkpc::SFR_SR1_SFR_SR1, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_SR1_SFR_SR1, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_SR1_SFR_SR1, 1); + dkpc_csr.wfo(utra::dkpc::SFR_SR1_SFR_SR1, baz); + + let foo = dkpc_csr.r(utra::dkpc::SFR_CFG4); + dkpc_csr.wo(utra::dkpc::SFR_CFG4, foo); + let bar = dkpc_csr.rf(utra::dkpc::SFR_CFG4_SFR_CFG4); + dkpc_csr.rmwf(utra::dkpc::SFR_CFG4_SFR_CFG4, bar); + let mut baz = dkpc_csr.zf(utra::dkpc::SFR_CFG4_SFR_CFG4, bar); + baz |= dkpc_csr.ms(utra::dkpc::SFR_CFG4_SFR_CFG4, 1); + dkpc_csr.wfo(utra::dkpc::SFR_CFG4_SFR_CFG4, baz); + } + #[test] #[ignore] fn compile_check_udma_ctrl_csr() { @@ -16508,11 +18746,6 @@ mod tests { let mut baz = udma_i2c_0_csr.zf(utra::udma_i2c_0::REG_RX_CFG_R_RX_EN, bar); baz |= udma_i2c_0_csr.ms(utra::udma_i2c_0::REG_RX_CFG_R_RX_EN, 1); udma_i2c_0_csr.wfo(utra::udma_i2c_0::REG_RX_CFG_R_RX_EN, baz); - let bar = udma_i2c_0_csr.rf(utra::udma_i2c_0::REG_RX_CFG_R_RX_CLR); - udma_i2c_0_csr.rmwf(utra::udma_i2c_0::REG_RX_CFG_R_RX_CLR, bar); - let mut baz = udma_i2c_0_csr.zf(utra::udma_i2c_0::REG_RX_CFG_R_RX_CLR, bar); - baz |= udma_i2c_0_csr.ms(utra::udma_i2c_0::REG_RX_CFG_R_RX_CLR, 1); - udma_i2c_0_csr.wfo(utra::udma_i2c_0::REG_RX_CFG_R_RX_CLR, baz); let foo = udma_i2c_0_csr.r(utra::udma_i2c_0::REG_TX_SADDR); udma_i2c_0_csr.wo(utra::udma_i2c_0::REG_TX_SADDR, foo); @@ -16542,11 +18775,6 @@ mod tests { let mut baz = udma_i2c_0_csr.zf(utra::udma_i2c_0::REG_TX_CFG_R_TX_EN, bar); baz |= udma_i2c_0_csr.ms(utra::udma_i2c_0::REG_TX_CFG_R_TX_EN, 1); udma_i2c_0_csr.wfo(utra::udma_i2c_0::REG_TX_CFG_R_TX_EN, baz); - let bar = udma_i2c_0_csr.rf(utra::udma_i2c_0::REG_TX_CFG_R_TX_CLR); - udma_i2c_0_csr.rmwf(utra::udma_i2c_0::REG_TX_CFG_R_TX_CLR, bar); - let mut baz = udma_i2c_0_csr.zf(utra::udma_i2c_0::REG_TX_CFG_R_TX_CLR, bar); - baz |= udma_i2c_0_csr.ms(utra::udma_i2c_0::REG_TX_CFG_R_TX_CLR, 1); - udma_i2c_0_csr.wfo(utra::udma_i2c_0::REG_TX_CFG_R_TX_CLR, baz); let foo = udma_i2c_0_csr.r(utra::udma_i2c_0::REG_CMD_SADDR); udma_i2c_0_csr.wo(utra::udma_i2c_0::REG_CMD_SADDR, foo); @@ -16576,11 +18804,6 @@ mod tests { let mut baz = udma_i2c_0_csr.zf(utra::udma_i2c_0::REG_CMD_CFG_R_CMD_EN, bar); baz |= udma_i2c_0_csr.ms(utra::udma_i2c_0::REG_CMD_CFG_R_CMD_EN, 1); udma_i2c_0_csr.wfo(utra::udma_i2c_0::REG_CMD_CFG_R_CMD_EN, baz); - let bar = udma_i2c_0_csr.rf(utra::udma_i2c_0::REG_CMD_CFG_R_CMD_CLR); - udma_i2c_0_csr.rmwf(utra::udma_i2c_0::REG_CMD_CFG_R_CMD_CLR, bar); - let mut baz = udma_i2c_0_csr.zf(utra::udma_i2c_0::REG_CMD_CFG_R_CMD_CLR, bar); - baz |= udma_i2c_0_csr.ms(utra::udma_i2c_0::REG_CMD_CFG_R_CMD_CLR, 1); - udma_i2c_0_csr.wfo(utra::udma_i2c_0::REG_CMD_CFG_R_CMD_CLR, baz); let foo = udma_i2c_0_csr.r(utra::udma_i2c_0::REG_STATUS); udma_i2c_0_csr.wo(utra::udma_i2c_0::REG_STATUS, foo); @@ -16595,14 +18818,6 @@ mod tests { baz |= udma_i2c_0_csr.ms(utra::udma_i2c_0::REG_STATUS_R_AL, 1); udma_i2c_0_csr.wfo(utra::udma_i2c_0::REG_STATUS_R_AL, baz); - let foo = udma_i2c_0_csr.r(utra::udma_i2c_0::REG_SETUP); - udma_i2c_0_csr.wo(utra::udma_i2c_0::REG_SETUP, foo); - let bar = udma_i2c_0_csr.rf(utra::udma_i2c_0::REG_SETUP_R_DO_RST); - udma_i2c_0_csr.rmwf(utra::udma_i2c_0::REG_SETUP_R_DO_RST, bar); - let mut baz = udma_i2c_0_csr.zf(utra::udma_i2c_0::REG_SETUP_R_DO_RST, bar); - baz |= udma_i2c_0_csr.ms(utra::udma_i2c_0::REG_SETUP_R_DO_RST, 1); - udma_i2c_0_csr.wfo(utra::udma_i2c_0::REG_SETUP_R_DO_RST, baz); - let foo = udma_i2c_0_csr.r(utra::udma_i2c_0::REG_ACK); udma_i2c_0_csr.wo(utra::udma_i2c_0::REG_ACK, foo); let bar = udma_i2c_0_csr.rf(utra::udma_i2c_0::REG_ACK_R_NACK); @@ -16646,11 +18861,6 @@ mod tests { let mut baz = udma_i2c_1_csr.zf(utra::udma_i2c_1::REG_RX_CFG_R_RX_EN, bar); baz |= udma_i2c_1_csr.ms(utra::udma_i2c_1::REG_RX_CFG_R_RX_EN, 1); udma_i2c_1_csr.wfo(utra::udma_i2c_1::REG_RX_CFG_R_RX_EN, baz); - let bar = udma_i2c_1_csr.rf(utra::udma_i2c_1::REG_RX_CFG_R_RX_CLR); - udma_i2c_1_csr.rmwf(utra::udma_i2c_1::REG_RX_CFG_R_RX_CLR, bar); - let mut baz = udma_i2c_1_csr.zf(utra::udma_i2c_1::REG_RX_CFG_R_RX_CLR, bar); - baz |= udma_i2c_1_csr.ms(utra::udma_i2c_1::REG_RX_CFG_R_RX_CLR, 1); - udma_i2c_1_csr.wfo(utra::udma_i2c_1::REG_RX_CFG_R_RX_CLR, baz); let foo = udma_i2c_1_csr.r(utra::udma_i2c_1::REG_TX_SADDR); udma_i2c_1_csr.wo(utra::udma_i2c_1::REG_TX_SADDR, foo); @@ -16680,11 +18890,6 @@ mod tests { let mut baz = udma_i2c_1_csr.zf(utra::udma_i2c_1::REG_TX_CFG_R_TX_EN, bar); baz |= udma_i2c_1_csr.ms(utra::udma_i2c_1::REG_TX_CFG_R_TX_EN, 1); udma_i2c_1_csr.wfo(utra::udma_i2c_1::REG_TX_CFG_R_TX_EN, baz); - let bar = udma_i2c_1_csr.rf(utra::udma_i2c_1::REG_TX_CFG_R_TX_CLR); - udma_i2c_1_csr.rmwf(utra::udma_i2c_1::REG_TX_CFG_R_TX_CLR, bar); - let mut baz = udma_i2c_1_csr.zf(utra::udma_i2c_1::REG_TX_CFG_R_TX_CLR, bar); - baz |= udma_i2c_1_csr.ms(utra::udma_i2c_1::REG_TX_CFG_R_TX_CLR, 1); - udma_i2c_1_csr.wfo(utra::udma_i2c_1::REG_TX_CFG_R_TX_CLR, baz); let foo = udma_i2c_1_csr.r(utra::udma_i2c_1::REG_CMD_SADDR); udma_i2c_1_csr.wo(utra::udma_i2c_1::REG_CMD_SADDR, foo); @@ -16714,11 +18919,6 @@ mod tests { let mut baz = udma_i2c_1_csr.zf(utra::udma_i2c_1::REG_CMD_CFG_R_CMD_EN, bar); baz |= udma_i2c_1_csr.ms(utra::udma_i2c_1::REG_CMD_CFG_R_CMD_EN, 1); udma_i2c_1_csr.wfo(utra::udma_i2c_1::REG_CMD_CFG_R_CMD_EN, baz); - let bar = udma_i2c_1_csr.rf(utra::udma_i2c_1::REG_CMD_CFG_R_CMD_CLR); - udma_i2c_1_csr.rmwf(utra::udma_i2c_1::REG_CMD_CFG_R_CMD_CLR, bar); - let mut baz = udma_i2c_1_csr.zf(utra::udma_i2c_1::REG_CMD_CFG_R_CMD_CLR, bar); - baz |= udma_i2c_1_csr.ms(utra::udma_i2c_1::REG_CMD_CFG_R_CMD_CLR, 1); - udma_i2c_1_csr.wfo(utra::udma_i2c_1::REG_CMD_CFG_R_CMD_CLR, baz); let foo = udma_i2c_1_csr.r(utra::udma_i2c_1::REG_STATUS); udma_i2c_1_csr.wo(utra::udma_i2c_1::REG_STATUS, foo); @@ -16733,14 +18933,6 @@ mod tests { baz |= udma_i2c_1_csr.ms(utra::udma_i2c_1::REG_STATUS_R_AL, 1); udma_i2c_1_csr.wfo(utra::udma_i2c_1::REG_STATUS_R_AL, baz); - let foo = udma_i2c_1_csr.r(utra::udma_i2c_1::REG_SETUP); - udma_i2c_1_csr.wo(utra::udma_i2c_1::REG_SETUP, foo); - let bar = udma_i2c_1_csr.rf(utra::udma_i2c_1::REG_SETUP_R_DO_RST); - udma_i2c_1_csr.rmwf(utra::udma_i2c_1::REG_SETUP_R_DO_RST, bar); - let mut baz = udma_i2c_1_csr.zf(utra::udma_i2c_1::REG_SETUP_R_DO_RST, bar); - baz |= udma_i2c_1_csr.ms(utra::udma_i2c_1::REG_SETUP_R_DO_RST, 1); - udma_i2c_1_csr.wfo(utra::udma_i2c_1::REG_SETUP_R_DO_RST, baz); - let foo = udma_i2c_1_csr.r(utra::udma_i2c_1::REG_ACK); udma_i2c_1_csr.wo(utra::udma_i2c_1::REG_ACK, foo); let bar = udma_i2c_1_csr.rf(utra::udma_i2c_1::REG_ACK_R_NACK); @@ -16784,11 +18976,6 @@ mod tests { let mut baz = udma_i2c_2_csr.zf(utra::udma_i2c_2::REG_RX_CFG_R_RX_EN, bar); baz |= udma_i2c_2_csr.ms(utra::udma_i2c_2::REG_RX_CFG_R_RX_EN, 1); udma_i2c_2_csr.wfo(utra::udma_i2c_2::REG_RX_CFG_R_RX_EN, baz); - let bar = udma_i2c_2_csr.rf(utra::udma_i2c_2::REG_RX_CFG_R_RX_CLR); - udma_i2c_2_csr.rmwf(utra::udma_i2c_2::REG_RX_CFG_R_RX_CLR, bar); - let mut baz = udma_i2c_2_csr.zf(utra::udma_i2c_2::REG_RX_CFG_R_RX_CLR, bar); - baz |= udma_i2c_2_csr.ms(utra::udma_i2c_2::REG_RX_CFG_R_RX_CLR, 1); - udma_i2c_2_csr.wfo(utra::udma_i2c_2::REG_RX_CFG_R_RX_CLR, baz); let foo = udma_i2c_2_csr.r(utra::udma_i2c_2::REG_TX_SADDR); udma_i2c_2_csr.wo(utra::udma_i2c_2::REG_TX_SADDR, foo); @@ -16818,11 +19005,6 @@ mod tests { let mut baz = udma_i2c_2_csr.zf(utra::udma_i2c_2::REG_TX_CFG_R_TX_EN, bar); baz |= udma_i2c_2_csr.ms(utra::udma_i2c_2::REG_TX_CFG_R_TX_EN, 1); udma_i2c_2_csr.wfo(utra::udma_i2c_2::REG_TX_CFG_R_TX_EN, baz); - let bar = udma_i2c_2_csr.rf(utra::udma_i2c_2::REG_TX_CFG_R_TX_CLR); - udma_i2c_2_csr.rmwf(utra::udma_i2c_2::REG_TX_CFG_R_TX_CLR, bar); - let mut baz = udma_i2c_2_csr.zf(utra::udma_i2c_2::REG_TX_CFG_R_TX_CLR, bar); - baz |= udma_i2c_2_csr.ms(utra::udma_i2c_2::REG_TX_CFG_R_TX_CLR, 1); - udma_i2c_2_csr.wfo(utra::udma_i2c_2::REG_TX_CFG_R_TX_CLR, baz); let foo = udma_i2c_2_csr.r(utra::udma_i2c_2::REG_CMD_SADDR); udma_i2c_2_csr.wo(utra::udma_i2c_2::REG_CMD_SADDR, foo); @@ -16852,11 +19034,6 @@ mod tests { let mut baz = udma_i2c_2_csr.zf(utra::udma_i2c_2::REG_CMD_CFG_R_CMD_EN, bar); baz |= udma_i2c_2_csr.ms(utra::udma_i2c_2::REG_CMD_CFG_R_CMD_EN, 1); udma_i2c_2_csr.wfo(utra::udma_i2c_2::REG_CMD_CFG_R_CMD_EN, baz); - let bar = udma_i2c_2_csr.rf(utra::udma_i2c_2::REG_CMD_CFG_R_CMD_CLR); - udma_i2c_2_csr.rmwf(utra::udma_i2c_2::REG_CMD_CFG_R_CMD_CLR, bar); - let mut baz = udma_i2c_2_csr.zf(utra::udma_i2c_2::REG_CMD_CFG_R_CMD_CLR, bar); - baz |= udma_i2c_2_csr.ms(utra::udma_i2c_2::REG_CMD_CFG_R_CMD_CLR, 1); - udma_i2c_2_csr.wfo(utra::udma_i2c_2::REG_CMD_CFG_R_CMD_CLR, baz); let foo = udma_i2c_2_csr.r(utra::udma_i2c_2::REG_STATUS); udma_i2c_2_csr.wo(utra::udma_i2c_2::REG_STATUS, foo); @@ -16871,14 +19048,6 @@ mod tests { baz |= udma_i2c_2_csr.ms(utra::udma_i2c_2::REG_STATUS_R_AL, 1); udma_i2c_2_csr.wfo(utra::udma_i2c_2::REG_STATUS_R_AL, baz); - let foo = udma_i2c_2_csr.r(utra::udma_i2c_2::REG_SETUP); - udma_i2c_2_csr.wo(utra::udma_i2c_2::REG_SETUP, foo); - let bar = udma_i2c_2_csr.rf(utra::udma_i2c_2::REG_SETUP_R_DO_RST); - udma_i2c_2_csr.rmwf(utra::udma_i2c_2::REG_SETUP_R_DO_RST, bar); - let mut baz = udma_i2c_2_csr.zf(utra::udma_i2c_2::REG_SETUP_R_DO_RST, bar); - baz |= udma_i2c_2_csr.ms(utra::udma_i2c_2::REG_SETUP_R_DO_RST, 1); - udma_i2c_2_csr.wfo(utra::udma_i2c_2::REG_SETUP_R_DO_RST, baz); - let foo = udma_i2c_2_csr.r(utra::udma_i2c_2::REG_ACK); udma_i2c_2_csr.wo(utra::udma_i2c_2::REG_ACK, foo); let bar = udma_i2c_2_csr.rf(utra::udma_i2c_2::REG_ACK_R_NACK); @@ -16922,11 +19091,6 @@ mod tests { let mut baz = udma_i2c_3_csr.zf(utra::udma_i2c_3::REG_RX_CFG_R_RX_EN, bar); baz |= udma_i2c_3_csr.ms(utra::udma_i2c_3::REG_RX_CFG_R_RX_EN, 1); udma_i2c_3_csr.wfo(utra::udma_i2c_3::REG_RX_CFG_R_RX_EN, baz); - let bar = udma_i2c_3_csr.rf(utra::udma_i2c_3::REG_RX_CFG_R_RX_CLR); - udma_i2c_3_csr.rmwf(utra::udma_i2c_3::REG_RX_CFG_R_RX_CLR, bar); - let mut baz = udma_i2c_3_csr.zf(utra::udma_i2c_3::REG_RX_CFG_R_RX_CLR, bar); - baz |= udma_i2c_3_csr.ms(utra::udma_i2c_3::REG_RX_CFG_R_RX_CLR, 1); - udma_i2c_3_csr.wfo(utra::udma_i2c_3::REG_RX_CFG_R_RX_CLR, baz); let foo = udma_i2c_3_csr.r(utra::udma_i2c_3::REG_TX_SADDR); udma_i2c_3_csr.wo(utra::udma_i2c_3::REG_TX_SADDR, foo); @@ -16956,11 +19120,6 @@ mod tests { let mut baz = udma_i2c_3_csr.zf(utra::udma_i2c_3::REG_TX_CFG_R_TX_EN, bar); baz |= udma_i2c_3_csr.ms(utra::udma_i2c_3::REG_TX_CFG_R_TX_EN, 1); udma_i2c_3_csr.wfo(utra::udma_i2c_3::REG_TX_CFG_R_TX_EN, baz); - let bar = udma_i2c_3_csr.rf(utra::udma_i2c_3::REG_TX_CFG_R_TX_CLR); - udma_i2c_3_csr.rmwf(utra::udma_i2c_3::REG_TX_CFG_R_TX_CLR, bar); - let mut baz = udma_i2c_3_csr.zf(utra::udma_i2c_3::REG_TX_CFG_R_TX_CLR, bar); - baz |= udma_i2c_3_csr.ms(utra::udma_i2c_3::REG_TX_CFG_R_TX_CLR, 1); - udma_i2c_3_csr.wfo(utra::udma_i2c_3::REG_TX_CFG_R_TX_CLR, baz); let foo = udma_i2c_3_csr.r(utra::udma_i2c_3::REG_CMD_SADDR); udma_i2c_3_csr.wo(utra::udma_i2c_3::REG_CMD_SADDR, foo); @@ -16990,11 +19149,6 @@ mod tests { let mut baz = udma_i2c_3_csr.zf(utra::udma_i2c_3::REG_CMD_CFG_R_CMD_EN, bar); baz |= udma_i2c_3_csr.ms(utra::udma_i2c_3::REG_CMD_CFG_R_CMD_EN, 1); udma_i2c_3_csr.wfo(utra::udma_i2c_3::REG_CMD_CFG_R_CMD_EN, baz); - let bar = udma_i2c_3_csr.rf(utra::udma_i2c_3::REG_CMD_CFG_R_CMD_CLR); - udma_i2c_3_csr.rmwf(utra::udma_i2c_3::REG_CMD_CFG_R_CMD_CLR, bar); - let mut baz = udma_i2c_3_csr.zf(utra::udma_i2c_3::REG_CMD_CFG_R_CMD_CLR, bar); - baz |= udma_i2c_3_csr.ms(utra::udma_i2c_3::REG_CMD_CFG_R_CMD_CLR, 1); - udma_i2c_3_csr.wfo(utra::udma_i2c_3::REG_CMD_CFG_R_CMD_CLR, baz); let foo = udma_i2c_3_csr.r(utra::udma_i2c_3::REG_STATUS); udma_i2c_3_csr.wo(utra::udma_i2c_3::REG_STATUS, foo); @@ -17009,14 +19163,6 @@ mod tests { baz |= udma_i2c_3_csr.ms(utra::udma_i2c_3::REG_STATUS_R_AL, 1); udma_i2c_3_csr.wfo(utra::udma_i2c_3::REG_STATUS_R_AL, baz); - let foo = udma_i2c_3_csr.r(utra::udma_i2c_3::REG_SETUP); - udma_i2c_3_csr.wo(utra::udma_i2c_3::REG_SETUP, foo); - let bar = udma_i2c_3_csr.rf(utra::udma_i2c_3::REG_SETUP_R_DO_RST); - udma_i2c_3_csr.rmwf(utra::udma_i2c_3::REG_SETUP_R_DO_RST, bar); - let mut baz = udma_i2c_3_csr.zf(utra::udma_i2c_3::REG_SETUP_R_DO_RST, bar); - baz |= udma_i2c_3_csr.ms(utra::udma_i2c_3::REG_SETUP_R_DO_RST, 1); - udma_i2c_3_csr.wfo(utra::udma_i2c_3::REG_SETUP_R_DO_RST, baz); - let foo = udma_i2c_3_csr.r(utra::udma_i2c_3::REG_ACK); udma_i2c_3_csr.wo(utra::udma_i2c_3::REG_ACK, foo); let bar = udma_i2c_3_csr.rf(utra::udma_i2c_3::REG_ACK_R_NACK);