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Optimize Control Loops #1 #1

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areiter128 opened this issue Nov 22, 2019 · 0 comments
Open

Optimize Control Loops #1 #1

areiter128 opened this issue Nov 22, 2019 · 0 comments
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@areiter128 @mannggWP
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enhancement New feature or request
Milestone
APEC Demo

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@areiter128
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Optimize ISR Time

  • Type: Low Level System Feature
  • Priority: Medium/Low

CPU load of control loops take more than 70% CPU load and result in colliding ADC triggers and control loop execution. These issues force us to step down control frequency to 87.5 kHz. Design target would be 175 kHz. This target was nice to have but 87.5 kHz might be good enough to meet PD requirements. Thus priority is lower.
@areiter128 areiter128 added the enhancement New feature or request label Nov 22, 2019
@areiter128 areiter128 added this to the APEC Demo milestone Nov 22, 2019
areiter128 added a commit that referenced this issue Dec 18, 2019
@areiter128
Added fault objects for UVLO, OVLO, OVP, OCP, OTW and OTP for converter
6f38ffd 
#1 and #2
areiter128 added a commit that referenced this issue Dec 18, 2019
@areiter128
Completed fault object declaration and initialization of UVLO, OVLO, …
d12d50f 
…OVP, OCP, OTW and OTP for converter #1 and #2
areiter128 added a commit that referenced this issue Dec 18, 2019
@areiter128
Added fault objects for UVLO, OVLO, OVP, OCP, OTW and OTP for converter
87d985e 
#1 and #2
areiter128 added a commit that referenced this issue Dec 23, 2019
@areiter128
Fixed bug with overlapping fault bits between converter #1 and #2
9754abe
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@areiter128 areiter128

@mannggWP mannggWP

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enhancement New feature or request
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@areiter128 @mannggWP