Commit 4cd4a58
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Serial: Tx use FIFO plus fixes
This is a reasonably major update to the Serial(UART)
code base, which is mostly concentrated on the Output(TX)
side of it.
Simple part of the description:
The currently released code, did not use the FIFO object that
was built into the Serial object. Instead it would output one
character at a time and then wait for a callback from the lower
level code base, which could be TDRE or TEND (mostly likely TDRE)
before it would return from the call. There were several other
methods that did not work or were not implemented including:
flush(), availableForWrite().
Also the write with buffer and count did not work as it did
not have the same parameters as the one in the Print class, so
the print class simply enumerated each byte.
**More Complex stuff:**
**Write Call**
I added a 16 byte buffer to the UART class that I use to pass down to
the R_SCI_UART_Write calls, with as much data as I have up to 16 from the
write method if a write is not currently in process. If not active and
the FIFO is empty. I detect that and bypass using FIFO up to the first
16 characters. If write is active, the new data is added to the FIFO.
**UART_EVENT_TX_DATA_EMPTY**
Note: I mention TDRE here, but also cases for FIFO which are different.
When lower level completes the write, it will do a callback with the
event: UART_EVENT_TX_DATA_EMPTY. First try was to simply grab what is
available up to 16 bytes and recall R_SCI_UART_Write with that. But that
can lose data, as the callback is called when the ISR code has put the last
byte into the TDR register, and the Write call always tries to put the first
character out, which if the TDRE state is not set, will lose the last byte.
Found I needed to handle two cases:
1) If TDRE I call the write function again.
2) if not TDRE, I update the Buffer/count member variables and reset which interrupt
events which will happen.
**TIMING**
I was still running into conditions where either data was lost or the transfers did
not work correctly.
RingBuffer:
Found in several cases we were spending too much time in the ISR and
we could lose interrupts on either UARTS or the same UARTS but different Interrupt.
Found a lot of the time was spent in the SafeRingBufferN code, where it creates a class object
which disables all interrupts and maybe reenables them at the end. This is needed as the API/
RingBufferN code is inherently unsafe to use here. I created my own versions of these classes
that make the RingBuffer class safer such that the Safe version could be a minimal subset.
That decreased the overhead a lot.
FIFO Size:
When using one of the UARTS with FIFO, we filled the RX before any was returned. So the ISR might need to process 16 characters, which took awhile. I have it currently set to 8. I
updated all of the Variants to allow each to set their preference.
**RX**
As mentioned above, when we receive bytes and the ISR is triggered, it calls our callback with
the UART_EVENT_RX_CHAR event. For simple double buffer UARTS, we simply store one character away.
However for FIFO UARTS, it will callback to us one time for each character in the FIFO. Which
before took a lot of time. As for character it would setup the callback, call it, where we
disabled the interrupts...
The new cod instead extracts the remaining characters from the FIFO and stuffs them directly
back into our fifo queue.
To keep from having to look each time at, am I running on a FIFO queue or not, I have two
different callbacks, so they don't have to keep asking.
**DEBUG CODE**
Currently I have a fair amount of debug code built into the Serial class, to help
debug, including fast functions to set/clear/toggle digital pins as well as to maybe
save some state information. I have hopefully all of this under #ifdef1 parent e989e72 commit 4cd4a58
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9 files changed
+567
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lines changed- cores/arduino
- cm_backtrace
- variants
- MINIMA/includes/ra/fsp/inc/instances
- MUXTO/includes/ra/fsp/inc/instances
- PORTENTA_C33/includes/ra/fsp/inc/instances
- UNOWIFIR4/includes/ra/fsp/inc/instances
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+567
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