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magancarzmagancarz
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[#82535] remove unused find_internal_timing_paths flags and omit searching for internal paths if specific paths pins/instances are specified
1 parent 5019b32 commit 96e5df4

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4 files changed

+150
-5
lines changed

‎search/Search.tcl‎

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -233,8 +233,6 @@ define_cmd_args "find_internal_timing_paths_cmd" \
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[-through through_list|-rise_through through_list|-fall_through through_list]\
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[-to to_list|-rise_to to_list|-fall_to to_list]\
235235
[-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max]\
236-
[-unconstrained]
237-
[-corner corner]\
238236
[-group_path_count path_count] \
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[-endpoint_path_count path_count]\
240238
[-unique_paths_to_endpoint]\
@@ -247,11 +245,19 @@ proc find_internal_timing_paths_cmd { cmd args_var } {
247245
upvar 1 $args_var args
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249247
parse_key_args $cmd args \
250-
keys {-from -rise_from -fall_from -to -rise_to -fall_to \
251-
-path_delay -corner -group_count -endpoint_count \
248+
keys {-from -rise_from -fall_from \
249+
-to -rise_to -fall_to \
250+
-through -rise_through -fall_through \
251+
-path_delay -group_count -endpoint_count \
252252
-group_path_count -endpoint_path_count \
253253
-slack_max -slack_min -path_group} \
254-
flags {-unconstrained -sort_by_slack -unique_paths_to_endpoint} 0
254+
flags {-sort_by_slack -unique_paths_to_endpoint} 0
255+
256+
if { [info exists keys(-from)] || [info exists keys(-rise_from)] || [info exists keys(-fall_from)] ||
257+
[info exists keys(-through)] || [info exists keys(-rise_through)] || [info exists keys(-fall_through)] ||
258+
[info exists keys(-to)] || [info exists keys(-rise_to)] || [info exists keys(-fall_to)] } {
259+
return NULL
260+
}
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256262
set min_max "max"
257263
set end_rf "rise_fall"

‎test/internal_paths_top_skipped.ok‎

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,126 @@
1+
Startpoint: t1 (rising edge-triggered flip-flop clocked by clk)
2+
Endpoint: t3 (rising edge-triggered flip-flop clocked by clk)
3+
Path Group: custom
4+
Path Type: max
5+
6+
Delay Time Description
7+
---------------------------------------------------------
8+
0.00 0.00 clock clk (rise edge)
9+
0.00 0.00 clock network delay (ideal)
10+
0.00 0.00 ^ t1/r2/CLK (DFFHQx4_ASAP7_75t_R)
11+
63.94 63.94 ^ t1/r2/Q (DFFHQx4_ASAP7_75t_R)
12+
0.00 63.94 ^ t1/out (internal_paths_cell)
13+
17.77 82.53 ^ b1/Y (BUFx2_ASAP7_75t_R)
14+
17.88 100.42 ^ b2/Y (BUFx2_ASAP7_75t_R)
15+
0.00 100.42 ^ t3/in (internal_paths_cell)
16+
0.00 100.42 ^ t3/r1/D (DFFHQx4_ASAP7_75t_R)
17+
100.42 data arrival time
18+
19+
500.00 500.00 clock clk (rise edge)
20+
0.00 500.00 clock network delay (ideal)
21+
0.00 500.00 clock reconvergence pessimism
22+
500.00 ^ t3/clk (internal_paths_cell)
23+
-11.41 488.59 library setup time
24+
488.59 data required time
25+
---------------------------------------------------------
26+
488.59 data required time
27+
-100.42 data arrival time
28+
---------------------------------------------------------
29+
388.17 slack (MET)
30+
31+
32+
Startpoint: t1 (rising edge-triggered flip-flop clocked by clk)
33+
Endpoint: t2 (rising edge-triggered flip-flop clocked by clk)
34+
Path Group: custom
35+
Path Type: max
36+
37+
Delay Time Description
38+
---------------------------------------------------------
39+
0.00 0.00 clock clk (rise edge)
40+
0.00 0.00 clock network delay (ideal)
41+
0.00 0.00 ^ t1/r2/CLK (DFFHQx4_ASAP7_75t_R)
42+
63.94 63.94 ^ t1/r2/Q (DFFHQx4_ASAP7_75t_R)
43+
0.00 63.94 ^ t1/out (internal_paths_cell)
44+
17.77 82.53 ^ b1/Y (BUFx2_ASAP7_75t_R)
45+
0.00 82.53 ^ t2/in (internal_paths_cell)
46+
0.00 82.53 ^ t2/r1/D (DFFHQx4_ASAP7_75t_R)
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82.53 data arrival time
48+
49+
500.00 500.00 clock clk (rise edge)
50+
0.00 500.00 clock network delay (ideal)
51+
0.00 500.00 clock reconvergence pessimism
52+
500.00 ^ t2/clk (internal_paths_cell)
53+
-11.41 488.59 library setup time
54+
488.59 data required time
55+
---------------------------------------------------------
56+
488.59 data required time
57+
-82.53 data arrival time
58+
---------------------------------------------------------
59+
406.05 slack (MET)
60+
61+
62+
Startpoint: t1 (rising edge-triggered flip-flop clocked by clk)
63+
Endpoint: t5 (rising edge-triggered flip-flop clocked by clk)
64+
Path Group: long
65+
Path Type: max
66+
67+
Delay Time Description
68+
---------------------------------------------------------
69+
0.00 0.00 clock clk (rise edge)
70+
0.00 0.00 clock network delay (ideal)
71+
0.00 0.00 ^ t1/r2/CLK (DFFHQx4_ASAP7_75t_R)
72+
63.94 63.94 ^ t1/r2/Q (DFFHQx4_ASAP7_75t_R)
73+
0.00 63.94 ^ t1/out (internal_paths_cell)
74+
17.77 82.53 ^ b1/Y (BUFx2_ASAP7_75t_R)
75+
17.88 100.42 ^ b2/Y (BUFx2_ASAP7_75t_R)
76+
17.88 118.30 ^ b3/Y (BUFx2_ASAP7_75t_R)
77+
16.66 134.96 ^ b4/Y (BUFx2_ASAP7_75t_R)
78+
0.00 134.96 ^ t5/in (internal_paths_cell)
79+
0.00 134.96 ^ t5/r1/D (DFFHQx4_ASAP7_75t_R)
80+
134.96 data arrival time
81+
82+
500.00 500.00 clock clk (rise edge)
83+
0.00 500.00 clock network delay (ideal)
84+
0.00 500.00 clock reconvergence pessimism
85+
500.00 ^ t5/clk (internal_paths_cell)
86+
-11.41 488.59 library setup time
87+
488.59 data required time
88+
---------------------------------------------------------
89+
488.59 data required time
90+
-134.96 data arrival time
91+
---------------------------------------------------------
92+
353.63 slack (MET)
93+
94+
95+
Startpoint: t1 (rising edge-triggered flip-flop clocked by clk)
96+
Endpoint: t4 (rising edge-triggered flip-flop clocked by clk)
97+
Path Group: long
98+
Path Type: max
99+
100+
Delay Time Description
101+
---------------------------------------------------------
102+
0.00 0.00 clock clk (rise edge)
103+
0.00 0.00 clock network delay (ideal)
104+
0.00 0.00 ^ t1/r2/CLK (DFFHQx4_ASAP7_75t_R)
105+
63.94 63.94 ^ t1/r2/Q (DFFHQx4_ASAP7_75t_R)
106+
0.00 63.94 ^ t1/out (internal_paths_cell)
107+
17.77 82.53 ^ b1/Y (BUFx2_ASAP7_75t_R)
108+
17.88 100.42 ^ b2/Y (BUFx2_ASAP7_75t_R)
109+
17.88 118.30 ^ b3/Y (BUFx2_ASAP7_75t_R)
110+
0.00 118.30 ^ t4/in (internal_paths_cell)
111+
0.00 118.30 ^ t4/r1/D (DFFHQx4_ASAP7_75t_R)
112+
118.30 data arrival time
113+
114+
500.00 500.00 clock clk (rise edge)
115+
0.00 500.00 clock network delay (ideal)
116+
0.00 500.00 clock reconvergence pessimism
117+
500.00 ^ t4/clk (internal_paths_cell)
118+
-11.41 488.59 library setup time
119+
488.59 data required time
120+
---------------------------------------------------------
121+
488.59 data required time
122+
-118.30 data arrival time
123+
---------------------------------------------------------
124+
370.29 slack (MET)
125+
126+

‎test/internal_paths_top_skipped.tcl‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
read_liberty asap7_small.lib.gz
2+
read_liberty internal_paths_cell.ok
3+
read_verilog internal_paths_top.v
4+
link_design internal_paths_top
5+
6+
create_clock -name clk -period 500 {clk}
7+
set_input_delay -clock clk 0 {in}
8+
9+
group_path -name custom -to {t2 t3}
10+
group_path -name long -to {t4 t5}
11+
12+
report_checks -group_path_count 2 -from t1

‎test/regression_vars.tcl‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -179,6 +179,7 @@ record_sta_tests {
179179
internal_paths_cell
180180
internal_paths_top
181181
internal_paths_top_sorted
182+
internal_paths_top_skipped
182183
}
183184

184185
define_test_group fast [group_tests all]

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