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4 DIGIT Seven Segment Interface
multiplexed 4 digit seven segment with mdelay and mux4() function
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SEG4_MUX_EX01.c

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#include <iostm8s103.h>
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#define CLR_BIT(p,n) ((p) &= ~((1) << (n)))
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#define SET_BIT(p,n) ((p) |= (1 << (n)))
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#define CLR_SEG1 CLR_BIT(PB_ODR,4)
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#define CLR_SEG2 CLR_BIT(PC_ODR,3)
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#define CLR_SEG3 CLR_BIT(PC_ODR,4)
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#define CLR_SEG4 CLR_BIT(PC_ODR,5)
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#define SET_SEG1 SET_BIT(PB_ODR,4)
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#define SET_SEG2 SET_BIT(PC_ODR,3)
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#define SET_SEG3 SET_BIT(PC_ODR,4)
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#define SET_SEG4 SET_BIT(PC_ODR,5)
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#define CLR_SEGA CLR_BIT(PD_ODR,6)
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#define CLR_SEGB CLR_BIT(PD_ODR,5)
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#define CLR_SEGC CLR_BIT(PD_ODR,4)
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#define CLR_SEGD CLR_BIT(PD_ODR,3)
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#define CLR_SEGE CLR_BIT(PD_ODR,2)
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#define CLR_SEGF CLR_BIT(PC_ODR,7)
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#define CLR_SEGG CLR_BIT(PC_ODR,6)
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#define SET_SEGA SET_BIT(PD_ODR,6)
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#define SET_SEGB SET_BIT(PD_ODR,5)
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#define SET_SEGC SET_BIT(PD_ODR,4)
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#define SET_SEGD SET_BIT(PD_ODR,3)
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#define SET_SEGE SET_BIT(PD_ODR,2)
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#define SET_SEGF SET_BIT(PC_ODR,7)
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#define SET_SEGG SET_BIT(PC_ODR,6)
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#define SW1 1
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#define SW2 2
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#define SW3 3
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#define SW_DDR PA_DDR
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void display_num(char num);
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void mux4(void);
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void delay(long x);
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void mdelay(long x);
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unsigned char digits[4]={1,2,3,4};
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main()
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{
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unsigned int d;
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CLR_BIT(SW_DDR,SW1); //SET SW1 AS INPUT
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CLR_BIT(SW_DDR,SW2); //SET SW2 AS INPUT
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CLR_BIT(SW_DDR,SW3); //SET SW3 AS INPUT
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PB_DDR = 255; //PORTB AS OUTPUT
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PC_DDR = 255; //PORTC AS OUTPUT
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PD_DDR = 255;
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//PB_DDR = (1<<5);
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PB_CR1 = 255;
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PD_CR1 = 255;
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PC_CR1 = 255;
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CLR_SEG1;
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CLR_SEG2;
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CLR_SEG3;
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CLR_SEG4;
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while (1){
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int cnt = 0;
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PB_ODR |= (1<<5);
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mdelay(300);
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PB_ODR &= ~(1<<5);
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mdelay(300);
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}
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// mux4();
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/*for(cnt=0;cnt<11;cnt++){
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display_num(cnt);
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delay(500);
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PB_ODR |= (1<<5);
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delay(500);
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PB_ODR &= ~(1<<5);
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}
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}*/
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}
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void display_num(char num){
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switch(num){
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case 0:
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CLR_SEGA;CLR_SEGB;CLR_SEGC;CLR_SEGD;CLR_SEGE;CLR_SEGF;SET_SEGG;
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break;
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case 1:
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SET_SEGA;CLR_SEGB;CLR_SEGC;SET_SEGD;SET_SEGE;SET_SEGF;SET_SEGG;
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break;
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case 2:
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CLR_SEGA;CLR_SEGB;SET_SEGC;CLR_SEGD;CLR_SEGE;SET_SEGF;CLR_SEGG;
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break;
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case 3:
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CLR_SEGA;CLR_SEGB;CLR_SEGC;CLR_SEGD;SET_SEGE;SET_SEGF;CLR_SEGG;
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break;
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case 4:
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SET_SEGA;CLR_SEGB;CLR_SEGC;SET_SEGD;SET_SEGE;CLR_SEGF;CLR_SEGG;
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break;
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case 5:
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CLR_SEGA;SET_SEGB;CLR_SEGC;CLR_SEGD;SET_SEGE;CLR_SEGF;CLR_SEGG;
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break;
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case 6:
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CLR_SEGA;SET_SEGB;CLR_SEGC;CLR_SEGD;CLR_SEGE;CLR_SEGF;CLR_SEGG;
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break;
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case 7:
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CLR_SEGA;CLR_SEGB;CLR_SEGC;SET_SEGD;SET_SEGE;SET_SEGF;SET_SEGG;
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break;
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case 8:
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CLR_SEGA;CLR_SEGB;CLR_SEGC;CLR_SEGD;CLR_SEGE;CLR_SEGF;CLR_SEGG;
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break;
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case 9:
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CLR_SEGA;CLR_SEGB;CLR_SEGC;CLR_SEGD;SET_SEGE;CLR_SEGF;CLR_SEGG;
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break;
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default:
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SET_SEGA;SET_SEGB;SET_SEGC;SET_SEGD;SET_SEGE;SET_SEGF;SET_SEGG;
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break;
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}
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}
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void mux4(){
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SET_SEG1;SET_SEG2;SET_SEG3;SET_SEG4;
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display_num(digits[0]);
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CLR_SEG1;
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delay(1);
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SET_SEG1;
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delay(1);
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display_num(digits[1]);
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CLR_SEG2;
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delay(1);
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SET_SEG2;
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delay(1);
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display_num(digits[2]);
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CLR_SEG3;
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delay(1);
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SET_SEG3;
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delay(1);
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display_num(digits[3]);
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CLR_SEG4;
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delay(1);
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SET_SEG4;
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delay(1);
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}
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void delay(long x){
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char d=0;
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for(;x>0;x--)
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for (d = 0; d < 10; d++); //Delay ~ 1 second
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}
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void mdelay(long x){
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long i=0;
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for(i=0;i<x;i++){
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mux4();
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}
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}
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