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The command to run eqy -j $(nproc) -f eqy_tester.eqy
tester.vhdl =>
library ieee;
use ieee.std_logic_1164.all;
entity tester is
port(
clk_in: in std_logic;
sreset_in: in std_logic;
sink_valid_in: in std_logic;
src_ready_in: in std_logic;
full_out: out std_logic_vector(1 downto 0)
);
end;
architecture rtl of tester is
-- Enabling this line makes the eqy test fail
signal full: std_logic_vector(1 downto 0) := (others => '0');
-- Enabling this line makes the eqy test pass
-- signal full: std_logic_vector(1 downto 0) := (others => 'U');
signal head: integer range 0 to 1;
signal tail: integer range 0 to 1;
begin
process(clk_in)
begin
if rising_edge(clk_in) then
if sink_valid_in = '1' and full(tail) = '0' then
full(tail) <= '1';
tail <= (tail + 1) mod 2;
end if;
if src_ready_in = '1' and full(head) = '1' then
full(head) <= '0';
head <= (head + 1) mod 2;
end if;
if sreset_in = '1' then
tail <= 0;
head <= 0;
full <= (others => '0');
end if;
end if;
end process;
full_out <= full;
end;
tester.sv =>
module tester (
input logic clk_in,
input logic sreset_in,
input logic sink_valid_in,
input logic src_ready_in,
output logic [1:0] full_out
);
(* init = "00" *)logic[1:0] full = '0;
logic[0:0] head;
logic[0:0] tail;
always_ff @(posedge clk_in) begin
if ((sink_valid_in == 1) && (full[tail] == 0)) begin
full[tail] = 1;
tail = (tail + 1) % 2;
end
if (src_ready_in && full[head]) begin
full[head] = 0;
head = (head + 1) % 2;
end
if (sreset_in) begin
tail = 0;
head = 0;
full = '0;
end
end
assign full_out = full;
endmodule
When comparing tester.vhdl to tester.sv, the eqy cannot prove full, unless I make full initial value on vhdl side "UU".
Do I have correct initialization syntax for verilog?
Any other explanation for the fail other than tool failing?
Executed with https://github.com/YosysHQ/oss-cad-suite-build/releases/tag/2025-01-11 (linux x86) within ubuntu:24.04 docker container.
The command to run
eqy -j $(nproc) -f eqy_tester.eqytester.vhdl =>
tester.sv =>
eqy_tester.eqy =>
output =>
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