-
Notifications
You must be signed in to change notification settings - Fork 0
/
Assembly_main_co_project.py(1).py
502 lines (482 loc) · 22.1 KB
/
Assembly_main_co_project.py(1).py
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
import sys
input_file= sys.argv[1]
output_file= sys.argv[2]
def imm_convert(imm_val,bits):
if int(imm_val)>=-2**(int(bits)-1) and int(imm_val)<=((2**int(bits))-1):
decimal=int(imm_val)
bits=int(bits)
if_negative=decimal<0
p_decimal=abs(decimal) #converting the number to positive
bin=''
while p_decimal>0: # converting the imm to binary number
bin=str(p_decimal%2)+bin
p_decimal//= 2
bin=bin.rjust(bits, '0') #making the required bit binary number
if if_negative:
complement_bin=''.join(['1' if bit=='0' else '0' for bit in bin]) #complementing binary number
t_complement=''
carry = 1
for bit in complement_bin[::-1]: # adding 1 to the complement to make 2's complement
if bit=='0' and carry==1:
t_complement = '1' + t_complement
carry = 0
elif bit =='1' and carry == 1:
t_complement='0' + t_complement
else:
t_complement = bit + t_complement
bin = t_complement
return bin
else:
return "imm val out of range"
# R - type Functions
def add(rs1,rs2,rd):
value=isa_codes["add"]["f7"]+reg_codes[rs2]+reg_codes[rs1]+isa_codes["add"]["f3"]+reg_codes[rd]+isa_codes["add"]["opcode"]
return value
def sub(rs1,rs2,rd):
value = isa_codes["sub"]["f7"]+reg_codes[rs2]+reg_codes[rs1]+isa_codes["sub"]["f3"]+reg_codes[rd]+isa_codes["sub"]["opcode"]
return value
def sll(rs1,rs2,rd):
value = isa_codes["sll"]["f7"]+reg_codes[rs2]+reg_codes[rs1]+isa_codes["sll"]["f3"]+reg_codes[rd]+isa_codes["sll"]["opcode"]
return value
def slt(rs1,rs2,rd):
value = isa_codes["slt"]["f7"]+reg_codes[rs2]+reg_codes[rs1]+isa_codes["slt"]["f3"]+reg_codes[rd]+isa_codes["slt"]["opcode"]
return value
def sltu(rs1,rs2,rd):
value = isa_codes["sltu"]["f7"]+reg_codes[rs2]+reg_codes[rs1]+isa_codes["sltu"]["f3"]+reg_codes[rd]+isa_codes["sltu"]["opcode"]
return value
def xor(rs1,rs2,rd):
value = isa_codes["xor"]["f7"]+reg_codes[rs2]+reg_codes[rs1]+isa_codes["xor"]["f3"]+reg_codes[rd]+isa_codes["xor"]["opcode"]
return value
def srl(rs1,rs2,rd):
value = isa_codes["srl"]["f7"]+reg_codes[rs2]+reg_codes[rs1]+isa_codes["srl"]["f3"]+reg_codes[rd]+isa_codes["srl"]["opcode"]
return value
def OR(rs1,rs2,rd): #This is or function
value = isa_codes["or"]["f7"]+reg_codes[rs2]+reg_codes[rs1]+isa_codes["or"]["f3"]+reg_codes[rd]+isa_codes["or"]["opcode"]
return value
def AND(rs1,rs2,rd): #This is and function
value = isa_codes["and"]["f7"]+reg_codes[rs2]+reg_codes[rs1]+isa_codes["and"]["f3"]+reg_codes[rd]+isa_codes["and"]["opcode"]
return value
# I - type Functions
def lw(imm,rs1,rd): #configure imm
i1=imm_convert(str(imm),str(12))
if i1=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
value=str(i1)+reg_codes[rs1]+isa_codes["lw"]["f3"]+reg_codes[rd]+isa_codes["lw"]["opcode"]
return value
def addi(imm,rs1,rd): #configure imm
i1=imm_convert(str(imm),str(12))
if i1=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
value=str(i1)+reg_codes[rs1]+isa_codes["addi"]["f3"]+reg_codes[rd]+isa_codes["addi"]["opcode"]
return value
def sltiu(imm,rs1,rd): #configure imm
i1=imm_convert(str(imm),str(12))
if i1=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
value=str(i1)+reg_codes[rs1]+isa_codes["sltiu"]["f3"]+reg_codes[rd]+isa_codes["sltiu"]["opcode"]
return value
def jalr(imm,rs1,rd): #configure imm
i1=imm_convert(str(imm),str(12))
if i1=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
value=str(i1)+reg_codes[rs1]+isa_codes["jalr"]["f3"]+reg_codes[rd]+isa_codes["jalr"]["opcode"]
return value
# S - type Functions
def sw(imm,rs2,rs1): # configure imms || imm1 --> 11:5 || imm2 --> 4:0
si=imm_convert(str(imm),str(12))
if si=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
s1=si[0:7:1] #s1[6::-1] was used earlier but was giving reversed results
s2=si[7:12:1] #s2[11:6:-1] was used earlier but was giving reversed results
value=s1+reg_codes[rs2]+reg_codes[rs1]+isa_codes["sw"]["f3"]+s2+isa_codes["sw"]["opcode"]
return value
# U - type
def lui(imm,rd): #configure imm || 31:12
ui=imm_convert(str(imm),str(32))
if ui=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
u1=ui[0:20:1]
value=u1+reg_codes[rd]+isa_codes["lui"]["opcode"]
return value
def auipc(imm,rd): #configure imm || 31:12
ui=imm_convert(str(imm),str(32))
if ui=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
u1=ui[0:20:1]
value=u1+reg_codes[rd]+isa_codes["auipc"]["opcode"]
return value
# B - type # configure imms || imm1 --> 12|10:5 || imm2 --> 4:1|11
def beq(rs1,rs2,imm):
bi=imm_convert(str(imm),str(12))
if bi=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
b1=bi[-12]+bi[-11:-5:1]
b2=bi[-5:-1:1]+bi[-11]
value=b1+reg_codes[rs2]+reg_codes[rs1]+isa_codes["beq"]["f3"]+b2+isa_codes["beq"]["opcode"]
return value
def bne(rs1,rs2,imm):
bi=imm_convert(str(imm),str(12))
if bi=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
b1=bi[-12]+bi[-11:-5:1]
b2=bi[-5:-1:1]+bi[-11]
value=b1+reg_codes[rs2]+reg_codes[rs1]+isa_codes["bne"]["f3"]+b2+isa_codes["bne"]["opcode"]
return value
def blt(rs1,rs2,imm):
bi=imm_convert(str(imm),str(12))
if bi=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
b1=bi[-12]+bi[-11:-5:1]
b2=bi[-5:-1:1]+bi[-11]
value=b1+reg_codes[rs2]+reg_codes[rs1]+isa_codes["blt"]["f3"]+b2+isa_codes["blt"]["opcode"]
return value
def bge(rs1,rs2,imm):
bi=imm_convert(str(imm),str(12))
if bi=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
b1=bi[-12]+bi[-11:-5:1]
b2=bi[-5:-1:1]+bi[-11]
value=b1+reg_codes[rs2]+reg_codes[rs1]+isa_codes["bge"]["f3"]+b2+isa_codes["bge"]["opcode"]
return value
def bltu(rs1,rs2,imm):
bi=imm_convert(str(imm),str(12))
if bi=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
b1=bi[-12]+bi[-11:-5:1]
b2=bi[-5:-1:1]+bi[-11]
value=b1+reg_codes[rs2]+reg_codes[rs1]+isa_codes["bltu"]["f3"]+b2+isa_codes["bltu"]["opcode"]
return value
def bgeu(rs1,rs2,imm):
bi=imm_convert(str(imm),str(12))
if bi=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
b1=bi[-12]+bi[-11:-5:1]
b2=bi[-5:-1:1]+bi[-11]
value=b1+reg_codes[rs2]+reg_codes[rs1]+isa_codes["bgeu"]["f3"]+b2+isa_codes["bgeu"]["opcode"]
return value
# J - type #configure imm || 20|10:1|11|19:12
def jal(imm,rd):
#imm=ans[19]+ans[9:0:-1]+ans[10]+ans[18:10:-1]
ji=imm_convert(str(imm),str(20))
if ji=="imm val out of range":
Flags["immediate"]["Flag"]=True
return -1
j1=ji[-20]+ji[9:19:1]+ji[-11]+ji[-12:-20:-1] #ji[-1:-11:-1] was used earlier but was giving wrong result
value=j1+reg_codes[rd]+isa_codes["jal"]["opcode"]
return value
# Bonus - Type # || still need to build these out
def mul(rs1,rs2,rd):
value=isa_codes["mul"]["f7"]+reg_codes[rs2]+reg_codes[rs1]+isa_codes["mul"]["f3"]+reg_codes[rd]+isa_codes["mul"]["opcode"]
return value
def rst():
value=isa_codes["rst"]["f7"]+"00000000000000"+isa_codes["rst"]["opcode"]
return value
def halt():
value=isa_codes["halt"]["f7"]+"00000000000000"+isa_codes["halt"]["opcode"]
return value
def rvrs(rs,rd):
value=isa_codes["rvrs"]["f7"]+"11111"+reg_codes[rs]+isa_codes["rvrs"]["f3"]+reg_codes[rd]+isa_codes["rvrs"]["opcode"]
return value
reg_codes = {
"zero" : "00000" , # x0
"ra" : "00001" , # x1
"sp" : "00010" , # x2
"gp" : "00011" , # x3
"tp" : "00100" , # x4
"t0" : "00101" , # x5
"t1" : "00110" , # x6
"t2" : "00111" , # x7
"s0" : "01000" , # x8
"fp" : "01000" , # x8
"s1" : "01001" , # x9
"a0" : "01010" , # x10
"a1" : "01011" , # x11
"a2" : "01100" , # x12
"a3" : "01101" , # x13
"a4" : "01110" , # x14
"a5" : "01111" , # x15
"a6" : "10000" , # x16
"a7" : "10001" , # x17
"s2" : "10010" , # x18
"s3" : "10011" , # x19
"s4" : "10100" , # x20
"s5" : "10101" , # x21
"s6" : "10110" , # x22
"s7" : "10111" , # x23
"s8" : "11000" , # x24
"s9" : "11001" , # x25
"s10" : "11010" , # x26
"s11" : "11011" , # x27
"t3" : "11100" , # x28
"t4" : "11101" , # x29
"t5" : "11110" , # x30
"t6" : "11111" , # x31
}
isa_codes={
# r type
"add":{"opcode":"0110011","type":"r","f3":"000","f7":"0000000","function":add},
"sub":{"opcode":"0110011","type":"r","f3":"000","f7":"0100000","function":sub},
"sll":{"opcode":"0110011","type":"r","f3":"001","f7":"0000000","function":sll},
"slt":{"opcode":"0110011","type":"r","f3":"010","f7":"0000000","function":slt},
"sltu":{"opcode":"0110011","type":"r","f3":"011","f7":"0000000","function":sltu},
"xor":{"opcode":"0110011","type":"r","f3":"100","f7":"0000000","function":xor},
"srl":{"opcode":"0110011","type":"r","f3":"101","f7":"0000000","function":srl},
"or":{"opcode":"0110011","type":"r","f3":"110","f7":"0000000","function":OR},
"and":{"opcode":"0110011","type":"r","f3":"111","f7":"0000000","function":AND},
# i
"lw":{"opcode":"0000011","type":"i","f3":"010","function":lw},
"addi":{"opcode":"0010011","type":"i","f3":"000","function":addi},
"sltiu":{"opcode":"0010011","type":"i","f3":"011","function":sltiu},
"jalr":{"opcode":"1100111","type":"i","f3":"000","function":jalr},
# s
"sw":{"opcode":"0100011","type":"s","f3":"010","function":sw},
# b
"beq":{"opcode":"1100011","type":"b","f3":"000","function":beq},
"bne":{"opcode":"1100011","type":"b","f3":"001","function":bne},
"blt":{"opcode":"1100011","type":"b","f3":"100","function":blt},
"bge":{"opcode":"1100011","type":"b","f3":"101","function":bge},
"bltu":{"opcode":"1100011","type":"b","f3":"110","function":bltu},
"bgeu":{"opcode":"1100011","type":"b","f3":"111","function":bgeu},
# u
"lui":{"opcode":"0110111","type":"u","function":lui},
"auipc":{"opcode":"0010111","type":"u","function":auipc},
# J
"jal":{"opcode":"1101111","type":"j","function":jal},
# bonus -- configure -- special cases
"mul":{"Opcode":"0000000","type":"bonus","f7":"0000000","f3":"000","function":mul},
"rst":{"Opcode":"0101010","type":"bonus","f7":"0000000","f3":"000","function":rst},
"halt":{"Opcode":"1010101","type":"bonus","f7":"0000000","f3":"000","function":halt},
"rvrs":{"Opcode":"1111111","type":"bonus","f7":"1111111","f3":"111","function":rvrs}
}
#List of Regiters and ISAs
ISAs=list(isa_codes.keys())
registers=list(reg_codes.keys())
#For Errors
Flags={
"reg":{"Flag":False,"Name":[],"Line":[]},
"instruction":{"Flag":False,"Value":[],"Line":[]},
"immediate":{"Flag":False,"Value":[],"Line":[]},
"label":{"Flag":False,"Value":[],"Line":[]}
}
# file import of assembly code
with open(input_file,"r") as f:
data=f.readlines()
input_instruction = []
Output_instruction = []
counter=0
labels={"Present":False,"Labels":[],"line":[]} # Lable counter
Virtual_Halts=[]
for instruction in data: #Gives me everthing required in a list
instruct=instruction.rstrip()
if ":" in instruct:
index_=instruct.index(":")
if ("beq zero,zero,0\n" == instruct[index_+1:]):
Virtual_Halts.append(counter)
else:
if ("beq zero,zero,0\n" == instruct):
Virtual_Halts.append(counter)
input_instruction.append(instruct.split())
if input_instruction[0][-1]==":": #Should remove all labels and not their position
if " " in input_instruction[0]:
Flags["label"]["Flag"]=True
Flags["label"]["Value"]=input_instruction[0]
Flags["label"]["Line"]=counter
labels["Present"]=True
labels["Labels"].append(input_instruction[0])
labels["line"].append(counter) #Just not sure about the way to note it. here although i have used Positon rather than indexing think of lines.
input_instruction.pop(0)
counter+=4
#Converting the main program
counter=0
for instruction in input_instruction:
opperation=instruction[0]
#if opperation in isa_codes.keys(): #if a valid opperation
if opperation in ISAs: #if a valid opperation
op_type=isa_codes[opperation]["type"]
if op_type=="r": #for all r type instructions
rd,rs1,rs2=instruction[-1].split(",")
if rd not in registers:
Flags["reg"]["Flag"]=True
Flags["reg"]["Name"].append(rd)
Flags["reg"]["Line"].append(counter)
if rs1 not in registers:
Flags["reg"]["Flag"]=True
Flags["reg"]["Name"].append(rs1)
Flags["reg"]["Line"].append(counter)
if rs2 not in registers:
Flags["reg"]["Flag"]=True
Flags["reg"]["Name"].append(rs2)
Flags["reg"]["Line"].append(counter)
if Flags["reg"]["Flag"]==False:
Binary_Format=isa_codes[opperation]["function"](rs1,rs2,rd)
Output_instruction.append(Binary_Format)
elif op_type=="i": #for all i type instructions
if opperation != "lw":
rd,rs,imm=instruction[-1].split(",")
else:
rd,imm_rs=instruction[-1].split(",")
imm,rs=imm_rs.split("(")
rs=rs[:-1]
if rd not in registers:
Flags["reg"]["Flag"]=True
Flags["reg"]["Name"].append(rd)
Flags["reg"]["Line"].append(counter)
if rs not in registers:
Flags["reg"]["Flag"]=True
Flags["reg"]["Name"].append(rs)
Flags["reg"]["Line"].append(counter)
if Flags["reg"]["Flag"]==False:
Binary_Format=isa_codes[opperation]["function"](imm,rs,rd)
if Binary_Format==-1: #imm error toh nahi hai
Flags["immediate"]["Flag"]=True
Flags["immediate"]["Line"].append(counter)
Flags["immediate"]["Value"].append(imm)
continue
else:
Output_instruction.append(Binary_Format)
elif op_type=="s": #Should work fine ig
rs2,imm_rs1=instruction[-1].split(",")
imm,rs1=imm_rs1.split("(")
rs1=rs1[:-1]
if rs2 not in registers:
Flags["reg"]["Flag"]=True
Flags["reg"]["Name"].append(rs2)
Flags["reg"]["Line"].append(counter)
if rs1 not in registers:
Flags["reg"]["Flag"]=True
Flags["reg"]["Name"].append(rs1)
Flags["reg"]["Line"].append(counter)
if Flags["reg"]["Flag"]==False:
Binary_Format=isa_codes[opperation]["function"](imm,rs2,rs1)
if Binary_Format==-1: #imm error toh nahi hai
Flags["immediate"]["Flag"]=True
Flags["immediate"]["Line"].append(counter)
Flags["immediate"]["Value"].append(imm)
continue
else:
Output_instruction.append(Binary_Format)
elif op_type=="b": #for all b type instructions
rs1,rs2,imm=instruction[-1].split(",")
if imm in labels["Labels"]:
index_of_label=labels["line"].index(imm)
if (counter>index_of_label):
imm=counter-index_of_label
elif (counter<index_of_label):
imm=counter+index_of_label
else:
Flags["label"]["Flag"]=True
Flags["label"]["Line"].append(counter)
Flags["label"]["Value"].append(imm)
if rs2 not in registers:
Flags["reg"]["Flag"]=True
Flags["reg"]["Name"].append(rs2)
Flags["reg"]["Line"].append(counter)
if rs1 not in registers:
Flags["reg"]["Flag"]=True
Flags["reg"]["Name"].append(rs1)
Flags["reg"]["Line"].append(counter)
if (Flags["reg"]["Flag"]==False) and (Flags["label"]["Flag"]==False):
Binary_Format=isa_codes[opperation]["function"](rs1,rs2,imm)
if Binary_Format==-1:
Flags["immediate"]["Flag"]=True
Flags["immediate"]["Line"].append(counter)
Flags["immediate"]["Value"].append(imm)
continue
else:
Output_instruction.append(Binary_Format)
elif op_type=="u": #for all u type instructions
rd,imm=instruction[-1].split(",")
if rd not in registers:
Flags["reg"]["Flag"]=True
Flags["reg"]["Name"].append(rd)
Flags["reg"]["Line"].append(counter)
if Flags["reg"]["Flag"]==False:
Binary_Format=isa_codes[opperation]["function"](imm,rd)
if Binary_Format==-1:
Flags["immediate"]["Flag"]=True
Flags["immediate"]["Line"].append(counter)
Flags["immediate"]["Value"].append(imm)
continue
else:
Output_instruction.append(Binary_Format)
elif op_type=="j": #for all j type instructions
rd,imm=instruction[-1].split(",")
if imm in labels["Labels"]:
index_of_label=labels["line"].index(imm)
if (counter>index_of_label):
imm=counter-index_of_label
elif (counter<index_of_label):
imm=counter+index_of_label
else:
Flags["label"]["Flag"]=True
Flags["label"]["Line"].append(counter)
Flags["label"]["Value"].append(imm)
if rd not in registers:
Flags["reg"]["Flag"]=True
Flags["reg"]["Name"].append(rd)
Flags["reg"]["Line"].append(counter)
continue
if (Flags["reg"]["Flag"]==False) and (Flags["label"]["Flag"]==False):
Binary_Format=isa_codes[opperation]["function"](imm,rd)
if Binary_Format==-1:
Flags["immediate"]["Flag"]=True
Flags["immediate"]["Line"].append(counter)
Flags["immediate"]["Value"].append(imm)
continue
else:
Output_instruction.append(Binary_Format)
elif op_type=="bonus": #Still left
if opperation == "halt":
Binary_Format=halt()
Output_instruction.append(Binary_Format)
continue
elif opperation == "rst":
Binary_Format=rst()
Output_instruction.append(Binary_Format)
continue
elif opperation == "rvrs": #rvrs rd,rs
# write from here!!
pass
else: #give error of invalid opperation
Flags["instruction"]["Flag"]=True
Flags["instruction"]["Value"].append(opperation)
Flags["instruction"]["Line"].append(counter)
counter+=4
if ((Flags["reg"]["Flag"]==False) and (Flags["immediate"]["Flag"]==False) and (Flags["instruction"]["Flag"]==False) and (Flags["label"]["Flag"]==False)):
# creating a binary code text file
with open(output_file,"w") as f:
#f.writelines(Output_instruction)
for i in range(len(Output_instruction)):
f.write(Output_instruction[i])
if i<(len(Output_instruction)-1):
f.write("\n")
else: #return all errors
if (Flags["instruction"]["Flag"]==False):
for i in range(len(Flags["instruction"]["Value"])):
value,line = Flags["instruction"]["Value"][i],Flags["instruction"]["Line"][i]
print(f"Instruction '{value}' in line {(line//4)+1} is not a valid Instruction.")
if (Flags["reg"]["Flag"]):
for i in range(len(Flags["reg"]["Name"])):
name,line = Flags["reg"]["Name"][i] , Flags["reg"]["Line"][i]
print(f"Register '{name}' in line {(line//4)+1} is not a valid Register.")
if (Flags["immediate"]["Flag"]):
for i in range(len(Flags["immediate"]["Values"])):
value,line = Flags["immediate"]["Values"][i] , Flags["immediate"]["Line"][i]
print(f"Immediate '{value}' in line {(line//4)+1} is not a valid immediate.")
if (Flags["label"]["Flag"]):
for i in range(len(Flags["label"]["Value"])):
value,line = Flags["label"]["Value"][i],Flags["label"]["Line"][i]
print(f"Invalid Usage of Label '{value}' in line {(line//4)+1}.")