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Squashed 'tools/Vitis-AI-Runtime/VART/target_factory/' changes from f0c0200..79a9fd6
79a9fd6 [fix] update version number to v1.3.2 6e36487 [feat][target] xvdpu/dpuv2: extended maxpool kernel size to 1-8; xvdpu: extended conv stride size to 1-8 14551be [feat][target] xvdpu: added C16B1_DW_QT 880e32a [feat][cmake] remove the direct dependency on glog and limit the make parallel to the number of core process. git-subtree-dir: tools/Vitis-AI-Runtime/VART/target_factory git-subtree-split: 79a9fd627dd36cd23a943ed020d4dc0ea05098e1
1 parent 239dbf5 commit 495cc54

34 files changed

+191
-44
lines changed

‎CMakeLists.txt‎

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@@ -14,13 +14,12 @@
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# limitations under the License.
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#
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cmake_minimum_required(VERSION 3.5)
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project(target-factory VERSION 1.3.1 LANGUAGES C CXX)
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project(target-factory VERSION 1.3.2 LANGUAGES C CXX)
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include(${CMAKE_SOURCE_DIR}/cmake/VitisCommon.cmake)
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option(BUILD_TEST "build test" OFF)
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find_package(glog REQUIRED)
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find_package(Protobuf REQUIRED)
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find_package(unilog REQUIRED)
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‎cmake.sh‎

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@@ -111,7 +111,7 @@ else
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echo "cd $PWD"
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echo cmake "${args[@]}" "$script_path"
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cmake "${args[@]}" "$script_path"
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make -j
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make -j $(nproc)
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${build_only:=false} || make install
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${build_package:=false} && make package
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fi

‎src/create_target_v2.cpp‎

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@@ -150,7 +150,7 @@ const Target create_target_v2(const std::uint64_t fingerprint) {
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pool_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
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pool_engine->add_pool_type(Target::Pool::max);
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auto max_limit = pool_engine->mutable_max_limit();
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max_limit->set_kernel_size("2-8");
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max_limit->set_kernel_size("1-8");
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max_limit->set_stride("1-8");
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if (PL_AVG) {
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pool_engine->add_pool_type(Target::Pool::avg);

‎targets/DPUCVDX8G_ISA0_B16384C64B1.prototxt‎

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@@ -78,7 +78,7 @@ conv_engine {
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}
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conv_limit {
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kernel_size: "1-16"
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stride: "1-4"
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stride: "1-8"
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}
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}
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eltwise_engine {
@@ -105,7 +105,7 @@ pool_engine {
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}
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pool_type: max
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max_limit {
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kernel_size: "2-8"
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kernel_size: "1-8"
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stride: "1-4"
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}
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pool_type: avg

‎targets/DPUCVDX8G_ISA0_B16384C64B1_DW.prototxt‎

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@@ -94,7 +94,7 @@ conv_engine {
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}
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conv_limit {
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kernel_size: "1-16"
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stride: "1-4"
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stride: "1-8"
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}
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}
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eltwise_engine {
@@ -121,7 +121,7 @@ pool_engine {
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}
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pool_type: max
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max_limit {
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kernel_size: "2-8"
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kernel_size: "1-8"
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stride: "1-4"
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}
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pool_type: avg

‎targets/DPUCVDX8G_ISA0_B4096C16B1_DW_QT.prototxt‎

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@@ -0,0 +1,148 @@
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# Copyright 2019 Xilinx Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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name: "DPUCVDX8G_ISA0_B4096C16B1_DW_QT"
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type: "DPUCVDX8G"
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isa_version: 0x00
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feature_code: 0x0004f2022210
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bank_group {
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name: "VB0"
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type: "Virtual"
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base_id: 0
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bank_num: 8
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bank_width: 16
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bank_depth: 4096
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}
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bank_group {
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name: "VB1"
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type: "Virtual"
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base_id: 8
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bank_num: 8
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bank_width: 16
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bank_depth: 4096
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}
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bank_group {
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name: "CONVW"
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type: "Param"
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base_id: 16
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bank_num: 16
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bank_width: 16
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bank_depth: 4096
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}
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bank_group {
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name: "DWCONVW"
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type: "Param"
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base_id: 32
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bank_num: 1
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bank_width: 16
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bank_depth: 4096
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}
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bank_group {
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name: "BIAS"
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type: "Param"
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base_id: 33
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bank_num: 1
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bank_width: 16
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bank_depth: 2048
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}
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bank_group {
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name: "DWCVBIAS"
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type: "Param"
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base_id: 34
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bank_num: 1
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bank_width: 16
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bank_depth: 2048
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}
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load_engine {
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channel_parallel: 16
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output_bank: "VB0"
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output_bank: "VB1"
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}
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save_engine {
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channel_parallel: 16
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input_bank: "VB0"
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input_bank: "VB1"
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}
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conv_engine {
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input_channel_parallel: 16
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output_channel_parallel: 16
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pixel_parallel: 8
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input_bank: "VB0"
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input_bank: "VB1"
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output_bank: "VB0"
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output_bank: "VB1"
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weight_bank: "CONVW"
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bias_bank: "BIAS"
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nonlinear {
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nonlinear_type: relu
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nonlinear_type: leaky_relu
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nonlinear_type: relu_six
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}
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conv_limit {
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kernel_size: "1-16"
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stride: "1-8"
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}
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}
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eltwise_engine {
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channel_parallel: 16
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pixel_parallel: 2
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input_bank: "VB0"
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input_bank: "VB1"
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output_bank: "VB0"
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output_bank: "VB1"
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nonlinear {
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nonlinear_type: relu
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}
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elew_type: add
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}
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pool_engine {
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channel_parallel: 16
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pixel_parallel: 2
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input_bank: "VB0"
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input_bank: "VB1"
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output_bank: "VB0"
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output_bank: "VB1"
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nonlinear {
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nonlinear_type: relu
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}
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pool_type: max
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max_limit {
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kernel_size: "1-8"
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stride: "1-4"
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}
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pool_type: avg
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avg_limit {
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kernel_size: "2-8"
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stride: "1-4"
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}
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}
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dwconv_engine {
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channel_parallel: 16
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pixel_parallel: 2
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input_bank: "VB0"
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input_bank: "VB1"
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output_bank: "VB0"
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output_bank: "VB1"
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weight_bank: "DWCONVW"
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bias_bank: "DWCVBIAS"
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nonlinear {
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nonlinear_type: relu
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nonlinear_type: relu_six
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}
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dwconv_limit {
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kernel_size: "1-16"
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stride: "1-4"
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}
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}
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batch: 1

‎targets/DPUCVDX8G_ISA0_B4096C16B3_DW.prototxt‎

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@@ -94,7 +94,7 @@ conv_engine {
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}
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conv_limit {
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kernel_size: "1-16"
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stride: "1-4"
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stride: "1-8"
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}
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}
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eltwise_engine {
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}
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pool_type: max
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max_limit {
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kernel_size: "2-8"
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kernel_size: "1-8"
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stride: "1-4"
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}
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pool_type: avg

‎targets/DPUCVDX8G_ISA0_B8192C32B1.prototxt‎

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@@ -78,7 +78,7 @@ conv_engine {
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}
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conv_limit {
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kernel_size: "1-16"
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stride: "1-4"
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stride: "1-8"
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}
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}
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eltwise_engine {
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}
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pool_type: max
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max_limit {
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kernel_size: "2-8"
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kernel_size: "1-8"
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stride: "1-4"
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}
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pool_type: avg

‎targets/DPUCVDX8G_ISA0_B8192C32B1_ELP4.prototxt‎

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@@ -78,7 +78,7 @@ conv_engine {
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}
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conv_limit {
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kernel_size: "1-16"
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stride: "1-4"
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stride: "1-8"
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}
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}
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eltwise_engine {
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}
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pool_type: max
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max_limit {
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kernel_size: "2-8"
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kernel_size: "1-8"
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stride: "1-4"
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}
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pool_type: avg

‎targets/DPUCVDX8G_ISA0_B8192C32B3.prototxt‎

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@@ -78,7 +78,7 @@ conv_engine {
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}
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conv_limit {
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kernel_size: "1-16"
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stride: "1-4"
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stride: "1-8"
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}
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}
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eltwise_engine {
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}
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pool_type: max
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max_limit {
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kernel_size: "2-8"
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kernel_size: "1-8"
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stride: "1-4"
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}
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pool_type: avg

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