Update trace branch #453
Open
Update trace branch #453
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
* Fixed bug whereby excluded incorrectly speculated load results were still being forwarded to dependents * Fixed memory over-usage bug where instruction fetch continued during loop buffer usage * Memory leak fix on created AggregateWriteRequest objects
On more recent versions of MacOS, and more specifically with more recent versions of Apple Clang, SST is unable to be compiled due to unary_function and binary_function types being depricated (since c++11) and now removed from Apple Clang v15. There is a compile flag which re-enabled these types and this has been added to CMakeLists.txt if the user is on MacOS. These functions are only used in SST, and in more recent versions (i.e. SST v13) they have been replaced - so this issue may only be short term if SimEng's SST support is updated to version 13+
This PR for the most part addresses issue #329 - correcting the SVCR and Streaming Mode logic introduced with SME. This is summaried as: - If a program is in Streaming Mode and calls SMSTART again, ZA and Vector registers are not zeroed out. - SVE Vector registers (and their aliases such as NEON and Scalar registers) are only zeroed out when SVCR.SM bit changes - SME's ZA register is only zeroed out when SVCR.ZA bit changes - SVCR can now be correctly updated using a regulat msr svcr, xt instruction in addition to smstart/smstop/msr svcr, #imm - More tests surrounding the SVCR logic have been added Additional to this, logic for the NEON muti-struct store with post index instructions introduced in PR #335 has been corrected via a small change to the metadata to correctly identify if a #imm or xt is used as said post index.
This PR adds support for the RISC-V F and D extensions along with a dummy implementation of the Zicsr extension which requires further updates to Capstone. Static and dynamic rounding modes are supported through changing the C++ fenv (except RMM), with dynamic rounding modes causing a non-fatal exception to ensure atomicity. This PR includes docs. Many spelling updates have also been performed.
This PR looks to replace the use of Config.hh and YAML-CPP with SimInfo.hh and a single header yaml library rapidyaml. The SimInfo class acts as a central point for all model configuration values both defined manually and from a read-in yaml config file. Improvements to adding new config options have been included through a new expectation struct that places requirements on a specific config option and a default value. Through this, default config files can be created and are especially useful in the test suite.
This PR addresses two identified bugs. Firstly, a fix for the unsupported AArch64 ST1W instruction variant when the memory and source vector elements are of different widths. Secondly, a fix to prevent Alias NYI instruction's destination registers from being incorrectly rewound.
This PR fixes #359 by first checking whether it is valid to update a destination register. Other minor improvements are: - More accurate dummy value returned for the fsrm instruction - Removal of unused variables in execute
This PR adds extra checks to the model configuration to ensure memory interface type restrictions are enforced
This pull request aims to update the Unit test suite of SimEng such that all classes have comprehensive coverage of their functionality tested. Closes #340 No tests have been added / updated for the following classes due to radical changes / replacement in current Pull Requests or in the very near future: CoreInstance Soon to be removed/radically changed in near future MicroDecoder Logic should be tested via the MicroOperation.cc regression tests All functions except decode (as of this PR) are now private - this change was made to conform to standard OOP practices; given they are only used within the class itself. This PR also contains a fixes for issues #365, #202, #133.
…within the AArch64 namespace(#381)
Fixed a couple of bugs regarding configuration options. The two fixed in this PR are described as follows: [FIXED] Vector-Length being greater than Load-Bandwidth or Store-Bandwidth caused progression to halt with no error. A simple check is added in ModelConfig.cc to ensure this is not the case, and to error out if it is the case. Any tests impacted by this are fixed [FIXED] Fetch-Block-Size being greater than 128 (despite being a valid value) caused a large memory leak. This was due to the precision of bufferedBytes_ and bufferOffset being 8 bit, as was the bytesAvailable parameter of the function predecode. This led to an infinite loop of instruction fetches. This has been solved by changing the precision to 16 bit, which covers the full range of configuration options for Fetch-Block-Size.
* Adding PerceptronPredictor * Updating default config options to include Branch Predictor Type * Adding tests for PerceptronPredictor * Updating Docs
This PR updates the names of many variables for code clarity and consistency which are listed below. operands -> sourceValues_ to prevent conflict with metadata.operands which contains both source and destination registers -operandsPending -> sourceOperandsPending_ getStackPointer -> getInitialStackPointer this name was chosen as to not conflict with Linux.getInitialStackPointer for human readability Underscores added throughout architecture specific header files
* Added headers to ProcessStateChange.hh and moved Register struct to new Register.hh. * Added memory directory and namespace.
* Introduced Container class for aarch64 instructions. Allows nonSME instructions to benefit from speed of std::array, and SME instructions to have variable size of structures. * Added unit tests for operandContainer.
Within this PR, updates and additions to the Syscall and Exception test suites in both AArch64 and RISCV namespaces have been implemented to improve the test coverage of supported system calls and instruction exceptions.
This PR implements the RISC-V compressed instructions and tests. Each instruction is treated like a pseudoinstruction which is expanded during metadata instantiation into a typical rv64g instruction. This means there are no changes to instruction execute. The fetch unit has been minorly updated to allow for these instructions and the associated unit tests have been added. Immediate values are now extracted during decode and stored in the imm field.
Fix all warnings across the entire code base. We now use the Werror flag to prevent any further warnings throughout future development
Correctly set the shift.value for the CSET alias. This was causing differences in pipeline behaviour within the CI as these instructions were assigned different groups under different compilers. Temporary extra checks are now performed before declaring an instruction is a shift type in case of other mis-reverted aliases.
…#417) Also enusres all exceptions are completed within 1 cycle too
This PR updates logic used to decode compressed instructions. Previously, assertions were used to check for invalid usages of instructions but unfortunately these could be falsely triggered by speculated instructions which did not retire. Logic has been updated to cause an exception if one of these instructions reaches the commit stage. RISC-V and AArch64 instruction objects now carry a small string to provide extra information when the exception is printed. Instructions with parameters that encode HINTS are now allowed to pass freely through the pipeline as they will cause no architectural state change. Quote from the spec: "HINTs are encoded as integer computational instructions with rd=x0. Hence, like the NOP instruction, HINTs do not change any architecturally visible state, except for advancing the pc and any applicable performance counters. Implementations are always allowed to ignore the encoded hints. ... [They] are usually used to communicate performance hints to the microarchitecture"
* Updating how a LoopBuffer is begun; and correcting how branch mispredicts are calculated * Adding comments to explain bug fix in FetchUnit.cc * Adding comments to explain bug fix in FetchUnit.cc * Adding comments to explain bug fix in FetchUnit.cc * Adding comments to explain bug fix in FetchUnit.cc * Updating simulated cycles * Updating comments
Adding speculative global history, moving update to ROB, and replacing BTBHistory with FTQ
Add infrastructure for testing the groups assigned to each micro-op of a macro-op, along with tests for all RISC-V instructions and most AArch64 aliases. Expected micro-op groups should be provided in the order which micro-ops are held in the MacroOp structure.
Upstreaming CI/CD pipeline developed by Leo Lai --------- Co-authored-by: Leo Lai <[email protected]> Co-authored-by: Finn Wilkinson <[email protected]>
Adjusting bash script in testing pipeline to allow GCC7 to work with Ubuntu 20
* Made more balanced RS allocation in DI unit by not stalling on first port allocation failure but instead cycling through all possible RSs. * Added port allocator config option.
* Getting rid of checkEarlyMispredict() function * Cleaning up tests
FinnWilkinson
requested review from
dANW34V3R,
jj16791,
JosephMoore25 and
ABenC377
and removed request for
dANW34V3R,
JosephMoore25 and
ABenC377
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Update the
tracebranch to be inline withdevand add support for SST so traces are generated with SimEng and SimEng+SST simulations.