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liangzhanhaoliangzhanhao
committedSep 25, 2020
fix(patch): reduce modification for keeping UCB coding in floating-point load
fix(patch): addr port from VPU to FPU for requesting floating-point scalar style(VPUIO.scala): keep blank align
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-41
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‎0001-feat-integrate-VPU-which-is-based-on-0.8-release-SPE.patch

+17-20
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
From c082597fa778343bdb2f8834abc9de835d9d270a Mon Sep 17 00:00:00 2001
1+
From 56a2f047a9ac33350f2726afa0f3b3f40e43616b Mon Sep 17 00:00:00 2001
22
From: liangzhanhao <549830592@qq.com>
33
Date: Mon, 14 Sep 2020 19:11:34 +0800
44
Subject: [PATCH] feat: integrate VPU which is based on 0.8-release SPEC
@@ -13,10 +13,10 @@ Subject: [PATCH] feat: integrate VPU which is based on 0.8-release SPEC
1313
src/main/scala/system/Configs.scala | 9 +-
1414
src/main/scala/tile/BaseTile.scala | 6 +-
1515
src/main/scala/tile/Core.scala | 8 +
16-
src/main/scala/tile/FPU.scala | 31 ++
17-
src/main/scala/tile/RocketTile.scala | 24 +-
16+
src/main/scala/tile/FPU.scala | 25 +
17+
src/main/scala/tile/RocketTile.scala | 23 +-
1818
src/main/scala/vpuwrapper/VPUWrapper.scala | 53 ++
19-
12 files changed, 927 insertions(+), 295 deletions(-)
19+
12 files changed, 920 insertions(+), 295 deletions(-)
2020
create mode 100644 src/main/scala/vpuwrapper/VPUWrapper.scala
2121

2222
diff --git a/build.sbt b/build.sbt
@@ -1640,7 +1640,7 @@ index 63314dd4e..cbc28dee4 100644
16401640
val trace = Vec(coreParams.retireWidth, new TracedInstruction).asOutput
16411641
val bpwatch = Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)).asOutput
16421642
diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
1643-
index ee646cc8a..d6d1dd8a1 100644
1643+
index ee646cc8a..6821b1d2f 100644
16441644
--- a/src/main/scala/tile/FPU.scala
16451645
+++ b/src/main/scala/tile/FPU.scala
16461646
@@ -140,6 +140,11 @@ class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
@@ -1677,17 +1677,21 @@ index ee646cc8a..d6d1dd8a1 100644
16771677
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
16781678
val rm = Bits(width = FPConstants.RM_SZ)
16791679
val typ = Bits(width = 2)
1680-
@@ -736,6 +749,9 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
1680+
@@ -733,9 +746,13 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
1681+
assert(consistent(wdata))
1682+
if (enableCommitLog)
1683+
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32, load_wb_data)
1684+
+ io.wrfr.ready := false.B //add for VPU
16811685
}
16821686

16831687
val ex_rs = ex_ra.map(a => regfile(a))
16841688
+
1685-
+ io.vpu_data := regfile.read(io.vpu_addr) //add for VPU
1689+
+ io.vpu_data := regfile(io.vpu_addr) //add for VPU
16861690
+
16871691
when (io.valid) {
16881692
when (id_ctrl.ren1) {
16891693
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
1690-
@@ -857,12 +873,27 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
1694+
@@ -857,12 +874,20 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
16911695
val wdouble = Mux(divSqrt_wen, divSqrt_typeTag, !wbInfo(0).single)
16921696
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wdouble)
16931697
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
@@ -1696,13 +1700,6 @@ index ee646cc8a..d6d1dd8a1 100644
16961700
+ when(io.wrfr.fire()) {
16971701
+ regfile(io.wrfr.bits.rd) := io.wrfr.bits.wdata
16981702
+ }
1699-
+ when(load_wb) {
1700-
+ regfile(load_wb_tag) := load_wb_data
1701-
+ assert(consistent(wdata))
1702-
+ if (enableCommitLog)
1703-
+ printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32, load_wb_data)
1704-
+ io.wrfr.ready := false.B
1705-
+ }
17061703
+ //add for VPU
17071704
+
17081705
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
@@ -1716,7 +1713,7 @@ index ee646cc8a..d6d1dd8a1 100644
17161713
when (wbInfo(0).cp && wen(0)) {
17171714
io.cp_resp.bits.data := wdata
17181715
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
1719-
index 05b5614ef..0d438c743 100644
1716+
index 05b5614ef..588f1d93c 100644
17201717
--- a/src/main/scala/tile/RocketTile.scala
17211718
+++ b/src/main/scala/tile/RocketTile.scala
17221719
@@ -13,6 +13,7 @@ import freechips.rocketchip.tilelink._
@@ -1744,11 +1741,12 @@ index 05b5614ef..0d438c743 100644
17441741
with HasLazyRoCCModule
17451742
with HasICacheFrontendModule {
17461743
Annotated.params(this, outer.rocketParams)
1747-
@@ -157,6 +159,20 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
1744+
@@ -157,7 +159,20 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
17481745
// Connect the core pipeline to other intra-tile modules
17491746
outer.frontend.module.io.cpu <> core.io.imem
17501747
dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
17511748
+
1749+
fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
17521750
+ //add for VPU
17531751
+ vpuOpt.map{ case vpu => { dcachePorts += vpu.io.dmem }}
17541752
+ vpuOpt foreach { vpu => core.io.vpu <> vpu.io.core }
@@ -1761,11 +1759,10 @@ index 05b5614ef..0d438c743 100644
17611759
+ vpu.io.fpu.resp.ready := fpu.io.wrfr.ready
17621760
+ }
17631761
+ //add for VPU
1764-
+
1765-
fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
17661762
core.io.ptw <> ptw.io.dpath
17671763

1768-
@@ -186,3 +202,9 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
1764+
// Connect the coprocessor interfaces
1765+
@@ -186,3 +201,9 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
17691766
trait HasFpuOpt { this: RocketTileModuleImp =>
17701767
val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p)))
17711768
}

‎vpu/src/main/scala/VPUIO.scala

+21-21
Original file line numberDiff line numberDiff line change
@@ -30,14 +30,14 @@
3030
* io.core.vcsr_vl : output[XLEN-1:0], data, value to write CSR vl
3131
* io.core.vcsr_vtype : output[XLEN-1:0], data, value to write CSR vtype
3232
*
33-
* io.core.ctrl_killx : input, control, kill the vector instruction executed at EXE stage
34-
* io.core.ctrl_killm : input, control, kill the vector instruction executed at MEM stage
35-
* io.core.ctrl_killw : input, control, kill the vector instruction executed at WB stage
36-
* io.core.eret : input, control, take the trap finish
37-
* io.core.vxcpt_precise : output, control, precise exception signal generated at VPU, it connect to WB stage
33+
* io.core.ctrl_killx : input, control, kill the vector instruction executed at EXE stage
34+
* io.core.ctrl_killm : input, control, kill the vector instruction executed at MEM stage
35+
* io.core.ctrl_killw : input, control, kill the vector instruction executed at WB stage
36+
* io.core.eret : input, control, take the trap finish
37+
* io.core.vxcpt_precise : output, control, precise exception signal generated at VPU, it connect to WB stage
3838
* io.core.vxcpt_imprecise : output, control, imprecise exception signal generated at VPU, it connect to ID stage
3939
* io.core.vxcpt_imprecise_resp : input, control, inform VPU that exception has been received
40-
* io.core.vcause : output[XLEN-1:0], data, exception cause
40+
* io.core.vcause : output[XLEN-1:0], data, exception cause
4141
* io.core.vmtval : output[XLEN-1:0], data,
4242
* io.core.vnack : output, control, imform Rocket that a vector inst has not been executed
4343
* io.core.dcache_blocked : output, control, showing VPU is occupying DCache
@@ -50,22 +50,22 @@
5050
* io.fpu.resp.bits.toFData : output[FLEN-1:0], data, result from VPU to FPU
5151
* io.fpu.resp.bits.rd : output[4:0], data, address of writing result to floating-point registers
5252
*
53-
* io.respValid : input, control, showing DCache response valid
54-
* io.respTag : input[6:0], control, return tag of request for in order receive
55-
* io.respSize : input[2:0], control, data width
56-
* io.respHasData : input, control, showing response has data
57-
* io.respData : input[XLEN-1:0], data, response data
58-
* io.respS2Xcpt : input HellaCacheExceptions, data, response exception information
53+
* io.respValid : input, control, showing DCache response valid
54+
* io.respTag : input[6:0], control, return tag of request for in order receive
55+
* io.respSize : input[2:0], control, data width
56+
* io.respHasData : input, control, showing response has data
57+
* io.respData : input[XLEN-1:0], data, response data
58+
* io.respS2Xcpt : input HellaCacheExceptions, data, response exception information
5959
*
60-
* io.reqReady : input, control, showing DCache is ready to receive a request
61-
* io.s2Nack : input, control, not-acknowledge request
62-
* io.reqValid : output, control, showing request valid
63-
* io.reqAddr : output[XLEN-1:0], control, address of memory data
64-
* io.reqTag : output[6:0], control, tag of request for in order receive
65-
* io.reqCmd : output[4:0], control, showing load or store action
66-
* io.reqSize : output[2:0], control, data width
67-
* io.s1Data : output[XLEN-1:0], data, data to store in memory
68-
* io.s1Kill : output, control, kill s1 stage of DCache
60+
* io.reqReady : input, control, showing DCache is ready to receive a request
61+
* io.s2Nack : input, control, not-acknowledge request
62+
* io.reqValid : output, control, showing request valid
63+
* io.reqAddr : output[XLEN-1:0], control, address of memory data
64+
* io.reqTag : output[6:0], control, tag of request for in order receive
65+
* io.reqCmd : output[4:0], control, showing load or store action
66+
* io.reqSize : output[2:0], control, data width
67+
* io.s1Data : output[XLEN-1:0], data, data to store in memory
68+
* io.s1Kill : output, control, kill s1 stage of DCache
6969
*
7070
************************************************************/
7171
package vpu

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