PDN pitch error

[kirubakaran-g]

Description

While processing the openlane flow of the built-in design namely 'spm', all the forty steps in flow are complete, and the required reports and logs are generated.

But, while processing the openlane flow for a simple Half Adder Logic, I got the following error while generating the PDN:

[STEP 6]
[INFO]: Generating PDN (log: designs/ha/runs/RUN_2023.11.18_10.26.24/logs/floorplan/6-pdn.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/pdn.tcl
[ERROR]: Log: designs/ha/runs/RUN_2023.11.18_10.26.24/logs/floorplan/6-pdn.log
[ERROR]: Last 10 lines:
[INFO]: Setting input delay to: 2.0
[WARNING STA-0337] port 'wb_clk_i' not found.
[INFO]: Setting load to: 0.033442
[INFO]: Setting clock uncertainty to: 0.25
[INFO]: Setting clock transition to: 0.15
[WARNING STA-0559] transition time can not be specified for virtual clocks.
[INFO]: Setting timing derate to: 5.0 %
[ERROR PDN-0175] Pitch 1.8400 is too small for, must be atleast 6.6000
Error: pdn_cfg.tcl, 92 PDN-0175
child process exited abnormally

[ERROR]: Creating issue reproducible...

What might be the issue? Thanks in advance.

Expected Behavior

The flow must be complete. But showing an error in 'PITCH'.

Environment report

open_pdks 2a38e86d557197f06d3eefca0fbc161db9e09924
Kernel: Linux v5.15.133.1-microsoft-standard-WSL2
Distribution: ubuntu 22.04
Python: v3.10.12 (OK)
Container Engine: docker v24.0.7 (OK)
OpenLane Git Version: 1e9efe9d0c4f8044d917d022a05ee1706651ed48
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: MISMATCH
The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: 2a38e86d557197f06d3eefca0fbc161db9e09924, tested: dd7771c384ed36b91a25e9f8b314355fc26561be)
This may introduce some issues. You may want to re-install the PDK by invoking `make pdk`.
---
Git Log (Last 3 Commits)

1e9efe9d 2023-11-16T08:28:57+02:00 Support `VERILOG_INCLUDE_DIRS` for linting (#2046) - piotro888 -  (HEAD -> master, tag: 2023.11.17, origin/master, origin/HEAD)
63cb841b 2023-11-14T12:54:37+00:00 Update Verilator (#2045) - Mohamed Gaber -  (tag: 2023.11.15)
64d43462 2023-11-14T07:53:24+02:00 Add tests for most checkers (#2044) - Kareem Farid -  ()
---
Git Remotes

origin  https://github.com/The-OpenROAD-Project/OpenLane.git (fetch)
origin  https://github.com/The-OpenROAD-Project/OpenLane.git (push)

Reproduction material

halfadder_issue.zip

Relevant log output

root@LAPTOP-QQMU2CQ2:/openlane# ./flow.tcl -design ha
OpenLane 1e9efe9d0c4f8044d917d022a05ee1706651ed48
All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.
Available under the Apache License, version 2.0. See the LICENSE file for more details.

[INFO]: Using configuration in 'designs/ha/config.json'...
[INFO]: PDK Root: /root/.volare
[INFO]: Process Design Kit: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd
[INFO]: Run Directory: /openlane/designs/ha/runs/RUN_2023.11.19_08.15.55
[INFO]: Saving runtime environment...
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[WARNING]: PNR_SDC_FILE is not set. It is recommended to write a custom SDC file for the design. Defaulting to BASE_SDC_FILE
[WARNING]: SIGNOFF_SDC_FILE is not set. It is recommended to write a custom SDC file for the design. Defaulting to BASE_SDC_FILE
[INFO]: Running linter (Verilator) (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/synthesis/linter.log)...
[INFO]: 0 errors found by linter
[INFO]: 0 warnings found by linter
[STEP 1]
[INFO]: Running Synthesis (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/synthesis/1-synthesis.log)...
[STEP 2]
[INFO]: Running Single-Corner Static Timing Analysis (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/synthesis/2-sta.log)...
[STEP 3]
[INFO]: Running Initial Floorplanning (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/floorplan/3-initial_fp.log)...
[WARNING]: Current core area is too small for the power grid settings chosen. The power grid will be scaled down.
[INFO]: Floorplanned with width 7.36 and height 5.44.
[STEP 4]
[INFO]: Running IO Placement (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/floorplan/4-io.log)...
[STEP 5]
[INFO]: Running Tap/Decap Insertion (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/floorplan/5-tap.log)...
[INFO]: Power planning with power {VPWR} and ground {VGND}...
[STEP 6]
[INFO]: Generating PDN (log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/floorplan/6-pdn.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/pdn.tcl
[ERROR]: Log: designs/ha/runs/RUN_2023.11.19_08.15.55/logs/floorplan/6-pdn.log
[ERROR]: Last 10 lines:
[INFO]: Setting input delay to: 2.0
[WARNING STA-0337] port '__VIRTUAL_CLK__' not found.
[INFO]: Setting load to: 0.033442
[INFO]: Setting clock uncertainty to: 0.25
[INFO]: Setting clock transition to: 0.15
[WARNING STA-0559] transition time can not be specified for virtual clocks.
[INFO]: Setting timing derate to: 5.0 %
[ERROR PDN-0175] Pitch 1.8400 is too small for, must be atleast 6.6000
Error: pdn_cfg.tcl, 92 PDN-0175
child process exited abnormally

[ERROR]: Creating issue reproducible...
[INFO]: Saving runtime environment...
OpenLane TCL Issue Packager

EFABLESS CORPORATION AND ALL AUTHORS OF THE OPENLANE PROJECT SHALL NOT BE HELD
LIABLE FOR ANY LEAKS THAT MAY OCCUR TO ANY PROPRIETARY DATA AS A RESULT OF USING
THIS SCRIPT. THIS SCRIPT IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND.

BY USING THIS SCRIPT, YOU ACKNOWLEDGE THAT YOU FULLY UNDERSTAND THIS DISCLAIMER
AND ALL IT ENTAILS.

Parsing config file(s)…
Setting up /openlane/designs/ha/runs/RUN_2023.11.19_08.15.55/issue_reproducible…
Done.
[INFO]: Reproducible packaged at 'designs/ha/runs/RUN_2023.11.19_08.15.55/issue_reproducible'.
root@LAPTOP-QQMU2CQ2:/openlane# exit

[kareefardi]

The specified PDN pitch is too small given other PDN configuration such as stripe width, spacing, etc. Also the design is a bit small. You might want to increase it's area a bit.